1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2022 MediaTek Inc. |
4 | * Author: Garmin Chang <garmin.chang@mediatek.com> |
5 | */ |
6 | |
7 | #include <dt-bindings/clock/mediatek,mt8188-clk.h> |
8 | #include <linux/clk-provider.h> |
9 | #include <linux/platform_device.h> |
10 | |
11 | #include "clk-gate.h" |
12 | #include "clk-mtk.h" |
13 | |
14 | static const struct mtk_gate_regs vpp1_0_cg_regs = { |
15 | .set_ofs = 0x104, |
16 | .clr_ofs = 0x108, |
17 | .sta_ofs = 0x100, |
18 | }; |
19 | |
20 | static const struct mtk_gate_regs vpp1_1_cg_regs = { |
21 | .set_ofs = 0x114, |
22 | .clr_ofs = 0x118, |
23 | .sta_ofs = 0x110, |
24 | }; |
25 | |
26 | #define GATE_VPP1_0(_id, _name, _parent, _shift) \ |
27 | GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
28 | |
29 | #define GATE_VPP1_1(_id, _name, _parent, _shift) \ |
30 | GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
31 | |
32 | static const struct mtk_gate vpp1_clks[] = { |
33 | /* VPP1_0 */ |
34 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl" , "top_vpp" , 0), |
35 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc" , "top_vpp" , 1), |
36 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot" , "top_vpp" , 2), |
37 | GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad" , "top_vpp" , 3), |
38 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot" , "top_vpp" , 4), |
39 | GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad" , "top_vpp" , 5), |
40 | GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot" , "top_vpp" , 6), |
41 | GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad" , "top_vpp" , 7), |
42 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma" , "top_vpp" , 8), |
43 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg" , "top_vpp" , 9), |
44 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma" , "top_vpp" , 10), |
45 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg" , "top_vpp" , 11), |
46 | GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma" , "top_vpp" , 12), |
47 | GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg" , "top_vpp" , 13), |
48 | GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split" , "top_vpp" , 14), |
49 | GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay" , "top_vpp" , 15), |
50 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz" , "top_vpp" , 16), |
51 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp" , "top_vpp" , 17), |
52 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color" , "top_vpp" , 18), |
53 | GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay" , "top_vpp" , 19), |
54 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz" , "top_vpp" , 20), |
55 | GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge" , "top_vpp" , 21), |
56 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp" , "top_vpp" , 22), |
57 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color" , "top_vpp" , 23), |
58 | GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz" , "top_vpp" , 24), |
59 | GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge" , "top_vpp" , 25), |
60 | GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp" , "top_vpp" , 26), |
61 | GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color" , "top_vpp" , 27), |
62 | GATE_VPP1_0(CLK_VPP1_GALS5, "vpp1_gals5" , "top_vpp" , 28), |
63 | GATE_VPP1_0(CLK_VPP1_GALS6, "vpp1_gals6" , "top_vpp" , 29), |
64 | GATE_VPP1_0(CLK_VPP1_LARB5, "vpp1_larb5" , "top_vpp" , 30), |
65 | GATE_VPP1_0(CLK_VPP1_LARB6, "vpp1_larb6" , "top_vpp" , 31), |
66 | /* VPP1_1 */ |
67 | GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr" , "top_vpp" , 0), |
68 | GATE_VPP1_1(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal" , "top_vpp" , 1), |
69 | GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr" , "top_vpp" , 2), |
70 | GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal" , "top_vpp" , 3), |
71 | GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr" , "top_vpp" , 4), |
72 | GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal" , "top_vpp" , 5), |
73 | GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex" , "top_vpp" , 7), |
74 | GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay" , "top_vpp" , 8), |
75 | GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay" , "top_vpp" , 9), |
76 | GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async" , "top_vpp" , 10), |
77 | GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay" , "top_vpp" , 11), |
78 | GATE_VPP1_1(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng" , "top_vpp" , 12), |
79 | GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng" , "top_vpp" , 13), |
80 | GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta" , "top_vpp" , 16), |
81 | GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi" , "top_vpp" , 17), |
82 | GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in" , "top_vpp" , 18), |
83 | GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out" , "top_vpp" , 19), |
84 | GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi" , "top_vpp" , 20), |
85 | GATE_VPP1_1(CLK_VPP1_DL_CON_OCC, "vpp1_dl_con_occ" , "top_vpp" , 21), |
86 | GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m" , "top_vpp" , 26), |
87 | }; |
88 | |
89 | static const struct mtk_clk_desc vpp1_desc = { |
90 | .clks = vpp1_clks, |
91 | .num_clks = ARRAY_SIZE(vpp1_clks), |
92 | }; |
93 | |
94 | static const struct platform_device_id clk_mt8188_vpp1_id_table[] = { |
95 | { .name = "clk-mt8188-vpp1" , .driver_data = (kernel_ulong_t)&vpp1_desc }, |
96 | { /* sentinel */ } |
97 | }; |
98 | MODULE_DEVICE_TABLE(platform, clk_mt8188_vpp1_id_table); |
99 | |
100 | static struct platform_driver clk_mt8188_vpp1_drv = { |
101 | .probe = mtk_clk_pdev_probe, |
102 | .remove_new = mtk_clk_pdev_remove, |
103 | .driver = { |
104 | .name = "clk-mt8188-vpp1" , |
105 | }, |
106 | .id_table = clk_mt8188_vpp1_id_table, |
107 | }; |
108 | module_platform_driver(clk_mt8188_vpp1_drv); |
109 | MODULE_LICENSE("GPL" ); |
110 | |