1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Copyright (c) 2021 MediaTek Inc. |
4 | // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
5 | |
6 | #include <linux/clk-provider.h> |
7 | #include <linux/mod_devicetable.h> |
8 | #include <linux/platform_device.h> |
9 | |
10 | #include "clk-mtk.h" |
11 | #include "clk-gate.h" |
12 | |
13 | #include <dt-bindings/clock/mt8192-clk.h> |
14 | |
15 | static const struct mtk_gate_regs mdp0_cg_regs = { |
16 | .set_ofs = 0x104, |
17 | .clr_ofs = 0x108, |
18 | .sta_ofs = 0x100, |
19 | }; |
20 | |
21 | static const struct mtk_gate_regs mdp1_cg_regs = { |
22 | .set_ofs = 0x124, |
23 | .clr_ofs = 0x128, |
24 | .sta_ofs = 0x120, |
25 | }; |
26 | |
27 | #define GATE_MDP0(_id, _name, _parent, _shift) \ |
28 | GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
29 | |
30 | #define GATE_MDP1(_id, _name, _parent, _shift) \ |
31 | GATE_MTK(_id, _name, _parent, &mdp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
32 | |
33 | static const struct mtk_gate mdp_clks[] = { |
34 | /* MDP0 */ |
35 | GATE_MDP0(CLK_MDP_RDMA0, "mdp_mdp_rdma0" , "mdp_sel" , 0), |
36 | GATE_MDP0(CLK_MDP_TDSHP0, "mdp_mdp_tdshp0" , "mdp_sel" , 1), |
37 | GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0" , "mdp_sel" , 2), |
38 | GATE_MDP0(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1" , "mdp_sel" , 3), |
39 | GATE_MDP0(CLK_MDP_RDMA1, "mdp_mdp_rdma1" , "mdp_sel" , 4), |
40 | GATE_MDP0(CLK_MDP_TDSHP1, "mdp_mdp_tdshp1" , "mdp_sel" , 5), |
41 | GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0" , "mdp_sel" , 6), |
42 | GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus" , "mdp_sel" , 7), |
43 | GATE_MDP0(CLK_MDP_WROT0, "mdp_mdp_wrot0" , "mdp_sel" , 8), |
44 | GATE_MDP0(CLK_MDP_RSZ0, "mdp_mdp_rsz0" , "mdp_sel" , 9), |
45 | GATE_MDP0(CLK_MDP_HDR0, "mdp_mdp_hdr0" , "mdp_sel" , 10), |
46 | GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mdp_mutex0" , "mdp_sel" , 11), |
47 | GATE_MDP0(CLK_MDP_WROT1, "mdp_mdp_wrot1" , "mdp_sel" , 12), |
48 | GATE_MDP0(CLK_MDP_RSZ1, "mdp_mdp_rsz1" , "mdp_sel" , 13), |
49 | GATE_MDP0(CLK_MDP_HDR1, "mdp_mdp_hdr1" , "mdp_sel" , 14), |
50 | GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_mdp_fake_eng0" , "mdp_sel" , 15), |
51 | GATE_MDP0(CLK_MDP_AAL0, "mdp_mdp_aal0" , "mdp_sel" , 16), |
52 | GATE_MDP0(CLK_MDP_AAL1, "mdp_mdp_aal1" , "mdp_sel" , 17), |
53 | GATE_MDP0(CLK_MDP_COLOR0, "mdp_mdp_color0" , "mdp_sel" , 18), |
54 | GATE_MDP0(CLK_MDP_COLOR1, "mdp_mdp_color1" , "mdp_sel" , 19), |
55 | /* MDP1 */ |
56 | GATE_MDP1(CLK_MDP_IMG_DL_RELAY0_ASYNC0, "mdp_img_dl_relay0_async0" , "mdp_sel" , 0), |
57 | GATE_MDP1(CLK_MDP_IMG_DL_RELAY1_ASYNC1, "mdp_img_dl_relay1_async1" , "mdp_sel" , 8), |
58 | }; |
59 | |
60 | static const struct mtk_clk_desc mdp_desc = { |
61 | .clks = mdp_clks, |
62 | .num_clks = ARRAY_SIZE(mdp_clks), |
63 | }; |
64 | |
65 | static const struct of_device_id of_match_clk_mt8192_mdp[] = { |
66 | { |
67 | .compatible = "mediatek,mt8192-mdpsys" , |
68 | .data = &mdp_desc, |
69 | }, { |
70 | /* sentinel */ |
71 | } |
72 | }; |
73 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_mdp); |
74 | |
75 | static struct platform_driver clk_mt8192_mdp_drv = { |
76 | .probe = mtk_clk_simple_probe, |
77 | .remove_new = mtk_clk_simple_remove, |
78 | .driver = { |
79 | .name = "clk-mt8192-mdp" , |
80 | .of_match_table = of_match_clk_mt8192_mdp, |
81 | }, |
82 | }; |
83 | module_platform_driver(clk_mt8192_mdp_drv); |
84 | MODULE_LICENSE("GPL" ); |
85 | |