| 1 | // SPDX-License-Identifier: GPL-2.0-only |
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| 2 | // |
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| 3 | // Copyright (c) 2021 MediaTek Inc. |
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| 4 | // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
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| 5 | |
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| 6 | #include <linux/clk-provider.h> |
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| 7 | #include <linux/mod_devicetable.h> |
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| 8 | #include <linux/platform_device.h> |
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| 9 | |
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| 10 | #include "clk-mtk.h" |
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| 11 | #include "clk-gate.h" |
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| 12 | |
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| 13 | #include <dt-bindings/clock/mt8192-clk.h> |
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| 14 | |
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| 15 | static const struct mtk_gate_regs msdc_top_cg_regs = { |
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| 16 | .set_ofs = 0x0, |
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| 17 | .clr_ofs = 0x0, |
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| 18 | .sta_ofs = 0x0, |
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| 19 | }; |
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| 20 | |
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| 21 | #define GATE_MSDC_TOP(_id, _name, _parent, _shift) \ |
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| 22 | GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
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| 23 | |
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| 24 | static const struct mtk_gate msdc_top_clks[] = { |
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| 25 | GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p" , "aes_msdcfde_sel" , 0), |
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| 26 | GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_0P, "msdc_top_src_0p" , "infra_msdc0_src" , 1), |
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| 27 | GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_1P, "msdc_top_src_1p" , "infra_msdc1_src" , 2), |
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| 28 | GATE_MSDC_TOP(CLK_MSDC_TOP_SRC_2P, "msdc_top_src_2p" , "infra_msdc2_src" , 3), |
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| 29 | GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC0, "msdc_top_p_msdc0" , "axi_sel" , 4), |
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| 30 | GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC1, "msdc_top_p_msdc1" , "axi_sel" , 5), |
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| 31 | GATE_MSDC_TOP(CLK_MSDC_TOP_P_MSDC2, "msdc_top_p_msdc2" , "axi_sel" , 6), |
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| 32 | GATE_MSDC_TOP(CLK_MSDC_TOP_P_CFG, "msdc_top_p_cfg" , "axi_sel" , 7), |
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| 33 | GATE_MSDC_TOP(CLK_MSDC_TOP_AXI, "msdc_top_axi" , "axi_sel" , 8), |
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| 34 | GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_0P, "msdc_top_h_mst_0p" , "infra_msdc0" , 9), |
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| 35 | GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_1P, "msdc_top_h_mst_1p" , "infra_msdc1" , 10), |
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| 36 | GATE_MSDC_TOP(CLK_MSDC_TOP_H_MST_2P, "msdc_top_h_mst_2p" , "infra_msdc2" , 11), |
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| 37 | GATE_MSDC_TOP(CLK_MSDC_TOP_MEM_OFF_DLY_26M, "msdc_top_mem_off_dly_26m" , "clk26m" , 12), |
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| 38 | GATE_MSDC_TOP(CLK_MSDC_TOP_32K, "msdc_top_32k" , "clk32k" , 13), |
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| 39 | GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi" , "axi_sel" , 14), |
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| 40 | }; |
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| 41 | |
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| 42 | static const struct mtk_clk_desc msdc_top_desc = { |
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| 43 | .clks = msdc_top_clks, |
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| 44 | .num_clks = ARRAY_SIZE(msdc_top_clks), |
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| 45 | }; |
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| 46 | |
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| 47 | static const struct of_device_id of_match_clk_mt8192_msdc[] = { |
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| 48 | { |
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| 49 | .compatible = "mediatek,mt8192-msdc_top" , |
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| 50 | .data = &msdc_top_desc, |
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| 51 | }, { |
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| 52 | /* sentinel */ |
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| 53 | } |
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| 54 | }; |
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| 55 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_msdc); |
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| 56 | |
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| 57 | static struct platform_driver clk_mt8192_msdc_drv = { |
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| 58 | .probe = mtk_clk_simple_probe, |
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| 59 | .remove = mtk_clk_simple_remove, |
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| 60 | .driver = { |
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| 61 | .name = "clk-mt8192-msdc" , |
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| 62 | .of_match_table = of_match_clk_mt8192_msdc, |
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| 63 | }, |
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| 64 | }; |
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| 65 | module_platform_driver(clk_mt8192_msdc_drv); |
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| 66 | |
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| 67 | MODULE_DESCRIPTION("MediaTek MT8192 MMC/SD Controller clocks driver" ); |
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| 68 | MODULE_LICENSE("GPL" ); |
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| 69 | |
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