1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Copyright (c) 2021 MediaTek Inc. |
4 | // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
5 | |
6 | #include <linux/clk-provider.h> |
7 | #include <linux/mod_devicetable.h> |
8 | #include <linux/platform_device.h> |
9 | |
10 | #include "clk-mtk.h" |
11 | #include "clk-gate.h" |
12 | |
13 | #include <dt-bindings/clock/mt8192-clk.h> |
14 | |
15 | static const struct mtk_gate_regs vdec0_cg_regs = { |
16 | .set_ofs = 0x0, |
17 | .clr_ofs = 0x4, |
18 | .sta_ofs = 0x0, |
19 | }; |
20 | |
21 | static const struct mtk_gate_regs vdec1_cg_regs = { |
22 | .set_ofs = 0x200, |
23 | .clr_ofs = 0x204, |
24 | .sta_ofs = 0x200, |
25 | }; |
26 | |
27 | static const struct mtk_gate_regs vdec2_cg_regs = { |
28 | .set_ofs = 0x8, |
29 | .clr_ofs = 0xc, |
30 | .sta_ofs = 0x8, |
31 | }; |
32 | |
33 | #define GATE_VDEC0(_id, _name, _parent, _shift) \ |
34 | GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) |
35 | |
36 | #define GATE_VDEC1(_id, _name, _parent, _shift) \ |
37 | GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) |
38 | |
39 | #define GATE_VDEC2(_id, _name, _parent, _shift) \ |
40 | GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) |
41 | |
42 | static const struct mtk_gate vdec_clks[] = { |
43 | /* VDEC0 */ |
44 | GATE_VDEC0(CLK_VDEC_VDEC, "vdec_vdec" , "vdec_sel" , 0), |
45 | GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active" , "vdec_sel" , 4), |
46 | /* VDEC1 */ |
47 | GATE_VDEC1(CLK_VDEC_LAT, "vdec_lat" , "vdec_sel" , 0), |
48 | GATE_VDEC1(CLK_VDEC_LAT_ACTIVE, "vdec_lat_active" , "vdec_sel" , 4), |
49 | /* VDEC2 */ |
50 | GATE_VDEC2(CLK_VDEC_LARB1, "vdec_larb1" , "vdec_sel" , 0), |
51 | }; |
52 | |
53 | static const struct mtk_gate vdec_soc_clks[] = { |
54 | /* VDEC_SOC0 */ |
55 | GATE_VDEC0(CLK_VDEC_SOC_VDEC, "vdec_soc_vdec" , "vdec_sel" , 0), |
56 | GATE_VDEC0(CLK_VDEC_SOC_VDEC_ACTIVE, "vdec_soc_vdec_active" , "vdec_sel" , 4), |
57 | /* VDEC_SOC1 */ |
58 | GATE_VDEC1(CLK_VDEC_SOC_LAT, "vdec_soc_lat" , "vdec_sel" , 0), |
59 | GATE_VDEC1(CLK_VDEC_SOC_LAT_ACTIVE, "vdec_soc_lat_active" , "vdec_sel" , 4), |
60 | /* VDEC_SOC2 */ |
61 | GATE_VDEC2(CLK_VDEC_SOC_LARB1, "vdec_soc_larb1" , "vdec_sel" , 0), |
62 | }; |
63 | |
64 | static const struct mtk_clk_desc vdec_desc = { |
65 | .clks = vdec_clks, |
66 | .num_clks = ARRAY_SIZE(vdec_clks), |
67 | }; |
68 | |
69 | static const struct mtk_clk_desc vdec_soc_desc = { |
70 | .clks = vdec_soc_clks, |
71 | .num_clks = ARRAY_SIZE(vdec_soc_clks), |
72 | }; |
73 | |
74 | static const struct of_device_id of_match_clk_mt8192_vdec[] = { |
75 | { |
76 | .compatible = "mediatek,mt8192-vdecsys" , |
77 | .data = &vdec_desc, |
78 | }, { |
79 | .compatible = "mediatek,mt8192-vdecsys_soc" , |
80 | .data = &vdec_soc_desc, |
81 | }, { |
82 | /* sentinel */ |
83 | } |
84 | }; |
85 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8192_vdec); |
86 | |
87 | static struct platform_driver clk_mt8192_vdec_drv = { |
88 | .probe = mtk_clk_simple_probe, |
89 | .remove_new = mtk_clk_simple_remove, |
90 | .driver = { |
91 | .name = "clk-mt8192-vdec" , |
92 | .of_match_table = of_match_clk_mt8192_vdec, |
93 | }, |
94 | }; |
95 | module_platform_driver(clk_mt8192_vdec_drv); |
96 | MODULE_LICENSE("GPL" ); |
97 | |