1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Copyright (c) 2021 MediaTek Inc. |
4 | // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
5 | |
6 | #include "clk-gate.h" |
7 | #include "clk-mtk.h" |
8 | |
9 | #include <dt-bindings/clock/mt8195-clk.h> |
10 | #include <linux/clk-provider.h> |
11 | #include <linux/platform_device.h> |
12 | |
13 | static const struct mtk_gate_regs vdo0_0_cg_regs = { |
14 | .set_ofs = 0x104, |
15 | .clr_ofs = 0x108, |
16 | .sta_ofs = 0x100, |
17 | }; |
18 | |
19 | static const struct mtk_gate_regs vdo0_1_cg_regs = { |
20 | .set_ofs = 0x114, |
21 | .clr_ofs = 0x118, |
22 | .sta_ofs = 0x110, |
23 | }; |
24 | |
25 | static const struct mtk_gate_regs vdo0_2_cg_regs = { |
26 | .set_ofs = 0x124, |
27 | .clr_ofs = 0x128, |
28 | .sta_ofs = 0x120, |
29 | }; |
30 | |
31 | #define GATE_VDO0_0(_id, _name, _parent, _shift) \ |
32 | GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
33 | |
34 | #define GATE_VDO0_1(_id, _name, _parent, _shift) \ |
35 | GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
36 | |
37 | #define GATE_VDO0_2(_id, _name, _parent, _shift) \ |
38 | GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
39 | |
40 | #define GATE_VDO0_2_FLAGS(_id, _name, _parent, _shift, _flags) \ |
41 | GATE_MTK_FLAGS(_id, _name, _parent, &vdo0_2_cg_regs, _shift, \ |
42 | &mtk_clk_gate_ops_setclr, _flags) |
43 | |
44 | static const struct mtk_gate vdo0_clks[] = { |
45 | /* VDO0_0 */ |
46 | GATE_VDO0_0(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0" , "top_vpp" , 0), |
47 | GATE_VDO0_0(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0" , "top_vpp" , 2), |
48 | GATE_VDO0_0(CLK_VDO0_DISP_COLOR1, "vdo0_disp_color1" , "top_vpp" , 3), |
49 | GATE_VDO0_0(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0" , "top_vpp" , 4), |
50 | GATE_VDO0_0(CLK_VDO0_DISP_CCORR1, "vdo0_disp_ccorr1" , "top_vpp" , 5), |
51 | GATE_VDO0_0(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0" , "top_vpp" , 6), |
52 | GATE_VDO0_0(CLK_VDO0_DISP_AAL1, "vdo0_disp_aal1" , "top_vpp" , 7), |
53 | GATE_VDO0_0(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0" , "top_vpp" , 8), |
54 | GATE_VDO0_0(CLK_VDO0_DISP_GAMMA1, "vdo0_disp_gamma1" , "top_vpp" , 9), |
55 | GATE_VDO0_0(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0" , "top_vpp" , 10), |
56 | GATE_VDO0_0(CLK_VDO0_DISP_DITHER1, "vdo0_disp_dither1" , "top_vpp" , 11), |
57 | GATE_VDO0_0(CLK_VDO0_DISP_OVL1, "vdo0_disp_ovl1" , "top_vpp" , 16), |
58 | GATE_VDO0_0(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0" , "top_vpp" , 17), |
59 | GATE_VDO0_0(CLK_VDO0_DISP_WDMA1, "vdo0_disp_wdma1" , "top_vpp" , 18), |
60 | GATE_VDO0_0(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0" , "top_vpp" , 19), |
61 | GATE_VDO0_0(CLK_VDO0_DISP_RDMA1, "vdo0_disp_rdma1" , "top_vpp" , 20), |
62 | GATE_VDO0_0(CLK_VDO0_DSI0, "vdo0_dsi0" , "top_vpp" , 21), |
63 | GATE_VDO0_0(CLK_VDO0_DSI1, "vdo0_dsi1" , "top_vpp" , 22), |
64 | GATE_VDO0_0(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0" , "top_vpp" , 23), |
65 | GATE_VDO0_0(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0" , "top_vpp" , 24), |
66 | GATE_VDO0_0(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0" , "top_vpp" , 25), |
67 | GATE_VDO0_0(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0" , "top_vpp" , 26), |
68 | GATE_VDO0_0(CLK_VDO0_DISP_IL_ROT0, "vdo0_disp_il_rot0" , "top_vpp" , 27), |
69 | GATE_VDO0_0(CLK_VDO0_APB_BUS, "vdo0_apb_bus" , "top_vpp" , 28), |
70 | GATE_VDO0_0(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0" , "top_vpp" , 29), |
71 | GATE_VDO0_0(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1" , "top_vpp" , 30), |
72 | /* VDO0_1 */ |
73 | GATE_VDO0_1(CLK_VDO0_DL_ASYNC0, "vdo0_dl_async0" , "top_vpp" , 0), |
74 | GATE_VDO0_1(CLK_VDO0_DL_ASYNC1, "vdo0_dl_async1" , "top_vpp" , 1), |
75 | GATE_VDO0_1(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2" , "top_vpp" , 2), |
76 | GATE_VDO0_1(CLK_VDO0_DL_ASYNC3, "vdo0_dl_async3" , "top_vpp" , 3), |
77 | GATE_VDO0_1(CLK_VDO0_DL_ASYNC4, "vdo0_dl_async4" , "top_vpp" , 4), |
78 | GATE_VDO0_1(CLK_VDO0_DISP_MONITOR0, "vdo0_disp_monitor0" , "top_vpp" , 5), |
79 | GATE_VDO0_1(CLK_VDO0_DISP_MONITOR1, "vdo0_disp_monitor1" , "top_vpp" , 6), |
80 | GATE_VDO0_1(CLK_VDO0_DISP_MONITOR2, "vdo0_disp_monitor2" , "top_vpp" , 7), |
81 | GATE_VDO0_1(CLK_VDO0_DISP_MONITOR3, "vdo0_disp_monitor3" , "top_vpp" , 8), |
82 | GATE_VDO0_1(CLK_VDO0_DISP_MONITOR4, "vdo0_disp_monitor4" , "top_vpp" , 9), |
83 | GATE_VDO0_1(CLK_VDO0_SMI_GALS, "vdo0_smi_gals" , "top_vpp" , 10), |
84 | GATE_VDO0_1(CLK_VDO0_SMI_COMMON, "vdo0_smi_common" , "top_vpp" , 11), |
85 | GATE_VDO0_1(CLK_VDO0_SMI_EMI, "vdo0_smi_emi" , "top_vpp" , 12), |
86 | GATE_VDO0_1(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu" , "top_vpp" , 13), |
87 | GATE_VDO0_1(CLK_VDO0_SMI_LARB, "vdo0_smi_larb" , "top_vpp" , 14), |
88 | GATE_VDO0_1(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi" , "top_vpp" , 15), |
89 | /* VDO0_2 */ |
90 | GATE_VDO0_2(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi" , "top_dsi_occ" , 0), |
91 | GATE_VDO0_2(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi" , "top_dsi_occ" , 8), |
92 | GATE_VDO0_2_FLAGS(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf" , |
93 | "top_edp" , 16, CLK_SET_RATE_PARENT), |
94 | }; |
95 | |
96 | static const struct mtk_clk_desc vdo0_desc = { |
97 | .clks = vdo0_clks, |
98 | .num_clks = ARRAY_SIZE(vdo0_clks), |
99 | }; |
100 | |
101 | static const struct platform_device_id clk_mt8195_vdo0_id_table[] = { |
102 | { .name = "clk-mt8195-vdo0" , .driver_data = (kernel_ulong_t)&vdo0_desc }, |
103 | { /* sentinel */ } |
104 | }; |
105 | MODULE_DEVICE_TABLE(platform, clk_mt8195_vdo0_id_table); |
106 | |
107 | static struct platform_driver clk_mt8195_vdo0_drv = { |
108 | .probe = mtk_clk_pdev_probe, |
109 | .remove_new = mtk_clk_pdev_remove, |
110 | .driver = { |
111 | .name = "clk-mt8195-vdo0" , |
112 | }, |
113 | .id_table = clk_mt8195_vdo0_id_table, |
114 | }; |
115 | module_platform_driver(clk_mt8195_vdo0_drv); |
116 | MODULE_LICENSE("GPL" ); |
117 | |