1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Copyright (c) 2021 MediaTek Inc. |
4 | // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
5 | |
6 | #include "clk-gate.h" |
7 | #include "clk-mtk.h" |
8 | |
9 | #include <dt-bindings/clock/mt8195-clk.h> |
10 | #include <linux/clk-provider.h> |
11 | #include <linux/platform_device.h> |
12 | |
13 | static const struct mtk_gate_regs vdo1_0_cg_regs = { |
14 | .set_ofs = 0x104, |
15 | .clr_ofs = 0x108, |
16 | .sta_ofs = 0x100, |
17 | }; |
18 | |
19 | static const struct mtk_gate_regs vdo1_1_cg_regs = { |
20 | .set_ofs = 0x124, |
21 | .clr_ofs = 0x128, |
22 | .sta_ofs = 0x120, |
23 | }; |
24 | |
25 | static const struct mtk_gate_regs vdo1_2_cg_regs = { |
26 | .set_ofs = 0x134, |
27 | .clr_ofs = 0x138, |
28 | .sta_ofs = 0x130, |
29 | }; |
30 | |
31 | static const struct mtk_gate_regs vdo1_3_cg_regs = { |
32 | .set_ofs = 0x144, |
33 | .clr_ofs = 0x148, |
34 | .sta_ofs = 0x140, |
35 | }; |
36 | |
37 | static const struct mtk_gate_regs vdo1_4_cg_regs = { |
38 | .set_ofs = 0x400, |
39 | .clr_ofs = 0x400, |
40 | .sta_ofs = 0x400, |
41 | }; |
42 | |
43 | #define GATE_VDO1_0(_id, _name, _parent, _shift) \ |
44 | GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
45 | |
46 | #define GATE_VDO1_1(_id, _name, _parent, _shift) \ |
47 | GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
48 | |
49 | #define GATE_VDO1_2(_id, _name, _parent, _shift) \ |
50 | GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
51 | |
52 | #define GATE_VDO1_2_FLAGS(_id, _name, _parent, _shift, _flags) \ |
53 | GATE_MTK_FLAGS(_id, _name, _parent, &vdo1_2_cg_regs, _shift, \ |
54 | &mtk_clk_gate_ops_setclr, _flags) |
55 | |
56 | #define GATE_VDO1_3(_id, _name, _parent, _shift) \ |
57 | GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
58 | |
59 | #define GATE_VDO1_4(_id, _name, _parent, _shift) \ |
60 | GATE_MTK(_id, _name, _parent, &vdo1_4_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
61 | |
62 | static const struct mtk_gate vdo1_clks[] = { |
63 | /* VDO1_0 */ |
64 | GATE_VDO1_0(CLK_VDO1_SMI_LARB2, "vdo1_smi_larb2" , "top_vpp" , 0), |
65 | GATE_VDO1_0(CLK_VDO1_SMI_LARB3, "vdo1_smi_larb3" , "top_vpp" , 1), |
66 | GATE_VDO1_0(CLK_VDO1_GALS, "vdo1_gals" , "top_vpp" , 2), |
67 | GATE_VDO1_0(CLK_VDO1_FAKE_ENG0, "vdo1_fake_eng0" , "top_vpp" , 3), |
68 | GATE_VDO1_0(CLK_VDO1_FAKE_ENG, "vdo1_fake_eng" , "top_vpp" , 4), |
69 | GATE_VDO1_0(CLK_VDO1_MDP_RDMA0, "vdo1_mdp_rdma0" , "top_vpp" , 5), |
70 | GATE_VDO1_0(CLK_VDO1_MDP_RDMA1, "vdo1_mdp_rdma1" , "top_vpp" , 6), |
71 | GATE_VDO1_0(CLK_VDO1_MDP_RDMA2, "vdo1_mdp_rdma2" , "top_vpp" , 7), |
72 | GATE_VDO1_0(CLK_VDO1_MDP_RDMA3, "vdo1_mdp_rdma3" , "top_vpp" , 8), |
73 | GATE_VDO1_0(CLK_VDO1_VPP_MERGE0, "vdo1_vpp_merge0" , "top_vpp" , 9), |
74 | GATE_VDO1_0(CLK_VDO1_VPP_MERGE1, "vdo1_vpp_merge1" , "top_vpp" , 10), |
75 | GATE_VDO1_0(CLK_VDO1_VPP_MERGE2, "vdo1_vpp_merge2" , "top_vpp" , 11), |
76 | GATE_VDO1_0(CLK_VDO1_VPP_MERGE3, "vdo1_vpp_merge3" , "top_vpp" , 12), |
77 | GATE_VDO1_0(CLK_VDO1_VPP_MERGE4, "vdo1_vpp_merge4" , "top_vpp" , 13), |
78 | GATE_VDO1_0(CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC, "vdo1_vpp2_to_vdo1_dl_async" , "top_vpp" , 14), |
79 | GATE_VDO1_0(CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC, "vdo1_vpp3_to_vdo1_dl_async" , "top_vpp" , 15), |
80 | GATE_VDO1_0(CLK_VDO1_DISP_MUTEX, "vdo1_disp_mutex" , "top_vpp" , 16), |
81 | GATE_VDO1_0(CLK_VDO1_MDP_RDMA4, "vdo1_mdp_rdma4" , "top_vpp" , 17), |
82 | GATE_VDO1_0(CLK_VDO1_MDP_RDMA5, "vdo1_mdp_rdma5" , "top_vpp" , 18), |
83 | GATE_VDO1_0(CLK_VDO1_MDP_RDMA6, "vdo1_mdp_rdma6" , "top_vpp" , 19), |
84 | GATE_VDO1_0(CLK_VDO1_MDP_RDMA7, "vdo1_mdp_rdma7" , "top_vpp" , 20), |
85 | GATE_VDO1_0(CLK_VDO1_DP_INTF0_MM, "vdo1_dp_intf0_mm" , "top_vpp" , 21), |
86 | GATE_VDO1_0(CLK_VDO1_DPI0_MM, "vdo1_dpi0_mm" , "top_vpp" , 22), |
87 | GATE_VDO1_0(CLK_VDO1_DPI1_MM, "vdo1_dpi1_mm" , "top_vpp" , 23), |
88 | GATE_VDO1_0(CLK_VDO1_DISP_MONITOR, "vdo1_disp_monitor" , "top_vpp" , 24), |
89 | GATE_VDO1_0(CLK_VDO1_MERGE0_DL_ASYNC, "vdo1_merge0_dl_async" , "top_vpp" , 25), |
90 | GATE_VDO1_0(CLK_VDO1_MERGE1_DL_ASYNC, "vdo1_merge1_dl_async" , "top_vpp" , 26), |
91 | GATE_VDO1_0(CLK_VDO1_MERGE2_DL_ASYNC, "vdo1_merge2_dl_async" , "top_vpp" , 27), |
92 | GATE_VDO1_0(CLK_VDO1_MERGE3_DL_ASYNC, "vdo1_merge3_dl_async" , "top_vpp" , 28), |
93 | GATE_VDO1_0(CLK_VDO1_MERGE4_DL_ASYNC, "vdo1_merge4_dl_async" , "top_vpp" , 29), |
94 | GATE_VDO1_0(CLK_VDO1_VDO0_DSC_TO_VDO1_DL_ASYNC, "vdo1_vdo0_dsc_to_vdo1_dl_async" , |
95 | "top_vpp" , 30), |
96 | GATE_VDO1_0(CLK_VDO1_VDO0_MERGE_TO_VDO1_DL_ASYNC, "vdo1_vdo0_merge_to_vdo1_dl_async" , |
97 | "top_vpp" , 31), |
98 | /* VDO1_1 */ |
99 | GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE0, "vdo1_hdr_vdo_fe0" , "top_vpp" , 0), |
100 | GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE0, "vdo1_hdr_gfx_fe0" , "top_vpp" , 1), |
101 | GATE_VDO1_1(CLK_VDO1_HDR_VDO_BE, "vdo1_hdr_vdo_be" , "top_vpp" , 2), |
102 | GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE1, "vdo1_hdr_vdo_fe1" , "top_vpp" , 16), |
103 | GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE1, "vdo1_hdr_gfx_fe1" , "top_vpp" , 17), |
104 | GATE_VDO1_1(CLK_VDO1_DISP_MIXER, "vdo1_disp_mixer" , "top_vpp" , 18), |
105 | GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE0_DL_ASYNC, "vdo1_hdr_vdo_fe0_dl_async" , "top_vpp" , 19), |
106 | GATE_VDO1_1(CLK_VDO1_HDR_VDO_FE1_DL_ASYNC, "vdo1_hdr_vdo_fe1_dl_async" , "top_vpp" , 20), |
107 | GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE0_DL_ASYNC, "vdo1_hdr_gfx_fe0_dl_async" , "top_vpp" , 21), |
108 | GATE_VDO1_1(CLK_VDO1_HDR_GFX_FE1_DL_ASYNC, "vdo1_hdr_gfx_fe1_dl_async" , "top_vpp" , 22), |
109 | GATE_VDO1_1(CLK_VDO1_HDR_VDO_BE_DL_ASYNC, "vdo1_hdr_vdo_be_dl_async" , "top_vpp" , 23), |
110 | /* VDO1_2 */ |
111 | GATE_VDO1_2(CLK_VDO1_DPI0, "vdo1_dpi0" , "top_vpp" , 0), |
112 | GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI0, "vdo1_disp_monitor_dpi0" , "top_vpp" , 1), |
113 | GATE_VDO1_2(CLK_VDO1_DPI1, "vdo1_dpi1" , "top_vpp" , 8), |
114 | GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPI1, "vdo1_disp_monitor_dpi1" , "top_vpp" , 9), |
115 | GATE_VDO1_2_FLAGS(CLK_VDO1_DPINTF, "vdo1_dpintf" , "top_dp" , 16, CLK_SET_RATE_PARENT), |
116 | GATE_VDO1_2(CLK_VDO1_DISP_MONITOR_DPINTF, "vdo1_disp_monitor_dpintf" , "top_vpp" , 17), |
117 | /* VDO1_3 */ |
118 | GATE_VDO1_3(CLK_VDO1_26M_SLOW, "vdo1_26m_slow" , "clk26m" , 8), |
119 | /* VDO1_4 */ |
120 | GATE_VDO1_4(CLK_VDO1_DPI1_HDMI, "vdo1_dpi1_hdmi" , "hdmi_txpll" , 0), |
121 | }; |
122 | |
123 | static const struct mtk_clk_desc vdo1_desc = { |
124 | .clks = vdo1_clks, |
125 | .num_clks = ARRAY_SIZE(vdo1_clks), |
126 | }; |
127 | |
128 | static const struct platform_device_id clk_mt8195_vdo1_id_table[] = { |
129 | { .name = "clk-mt8195-vdo1" , .driver_data = (kernel_ulong_t)&vdo1_desc }, |
130 | { /* sentinel */ } |
131 | }; |
132 | MODULE_DEVICE_TABLE(platform, clk_mt8195_vdo1_id_table); |
133 | |
134 | static struct platform_driver clk_mt8195_vdo1_drv = { |
135 | .probe = mtk_clk_pdev_probe, |
136 | .remove_new = mtk_clk_pdev_remove, |
137 | .driver = { |
138 | .name = "clk-mt8195-vdo1" , |
139 | }, |
140 | .id_table = clk_mt8195_vdo1_id_table, |
141 | }; |
142 | module_platform_driver(clk_mt8195_vdo1_drv); |
143 | MODULE_LICENSE("GPL" ); |
144 | |