1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Copyright (c) 2021 MediaTek Inc. |
4 | // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
5 | |
6 | #include "clk-gate.h" |
7 | #include "clk-mtk.h" |
8 | |
9 | #include <dt-bindings/clock/mt8195-clk.h> |
10 | #include <linux/clk-provider.h> |
11 | #include <linux/platform_device.h> |
12 | |
13 | static const struct mtk_gate_regs vpp1_0_cg_regs = { |
14 | .set_ofs = 0x104, |
15 | .clr_ofs = 0x108, |
16 | .sta_ofs = 0x100, |
17 | }; |
18 | |
19 | static const struct mtk_gate_regs vpp1_1_cg_regs = { |
20 | .set_ofs = 0x114, |
21 | .clr_ofs = 0x118, |
22 | .sta_ofs = 0x110, |
23 | }; |
24 | |
25 | #define GATE_VPP1_0(_id, _name, _parent, _shift) \ |
26 | GATE_MTK(_id, _name, _parent, &vpp1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
27 | |
28 | #define GATE_VPP1_1(_id, _name, _parent, _shift) \ |
29 | GATE_MTK(_id, _name, _parent, &vpp1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) |
30 | |
31 | static const struct mtk_gate vpp1_clks[] = { |
32 | /* VPP1_0 */ |
33 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_OVL, "vpp1_svpp1_mdp_ovl" , "top_vpp" , 0), |
34 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TCC, "vpp1_svpp1_mdp_tcc" , "top_vpp" , 1), |
35 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_WROT, "vpp1_svpp1_mdp_wrot" , "top_vpp" , 2), |
36 | GATE_VPP1_0(CLK_VPP1_SVPP1_VPP_PAD, "vpp1_svpp1_vpp_pad" , "top_vpp" , 3), |
37 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_WROT, "vpp1_svpp2_mdp_wrot" , "top_vpp" , 4), |
38 | GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_PAD, "vpp1_svpp2_vpp_pad" , "top_vpp" , 5), |
39 | GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_WROT, "vpp1_svpp3_mdp_wrot" , "top_vpp" , 6), |
40 | GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_PAD, "vpp1_svpp3_vpp_pad" , "top_vpp" , 7), |
41 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RDMA, "vpp1_svpp1_mdp_rdma" , "top_vpp" , 8), |
42 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_FG, "vpp1_svpp1_mdp_fg" , "top_vpp" , 9), |
43 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_RDMA, "vpp1_svpp2_mdp_rdma" , "top_vpp" , 10), |
44 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_FG, "vpp1_svpp2_mdp_fg" , "top_vpp" , 11), |
45 | GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_RDMA, "vpp1_svpp3_mdp_rdma" , "top_vpp" , 12), |
46 | GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_FG, "vpp1_svpp3_mdp_fg" , "top_vpp" , 13), |
47 | GATE_VPP1_0(CLK_VPP1_VPP_SPLIT, "vpp1_vpp_split" , "top_vpp" , 14), |
48 | GATE_VPP1_0(CLK_VPP1_SVPP2_VDO0_DL_RELAY, "vpp1_svpp2_vdo0_dl_relay" , "top_vpp" , 15), |
49 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_TDSHP, "vpp1_svpp1_mdp_tdshp" , "top_vpp" , 16), |
50 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_COLOR, "vpp1_svpp1_mdp_color" , "top_vpp" , 17), |
51 | GATE_VPP1_0(CLK_VPP1_SVPP3_VDO1_DL_RELAY, "vpp1_svpp3_vdo1_dl_relay" , "top_vpp" , 18), |
52 | GATE_VPP1_0(CLK_VPP1_SVPP2_VPP_MERGE, "vpp1_svpp2_vpp_merge" , "top_vpp" , 19), |
53 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_COLOR, "vpp1_svpp2_mdp_color" , "top_vpp" , 20), |
54 | GATE_VPP1_0(CLK_VPP1_VPPSYS1_GALS, "vpp1_vppsys1_gals" , "top_vpp" , 21), |
55 | GATE_VPP1_0(CLK_VPP1_SVPP3_VPP_MERGE, "vpp1_svpp3_vpp_merge" , "top_vpp" , 22), |
56 | GATE_VPP1_0(CLK_VPP1_SVPP3_MDP_COLOR, "vpp1_svpp3_mdp_color" , "top_vpp" , 23), |
57 | GATE_VPP1_0(CLK_VPP1_VPPSYS1_LARB, "vpp1_vppsys1_larb" , "top_vpp" , 24), |
58 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_RSZ, "vpp1_svpp1_mdp_rsz" , "top_vpp" , 25), |
59 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_HDR, "vpp1_svpp1_mdp_hdr" , "top_vpp" , 26), |
60 | GATE_VPP1_0(CLK_VPP1_SVPP1_MDP_AAL, "vpp1_svpp1_mdp_aal" , "top_vpp" , 27), |
61 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_HDR, "vpp1_svpp2_mdp_hdr" , "top_vpp" , 28), |
62 | GATE_VPP1_0(CLK_VPP1_SVPP2_MDP_AAL, "vpp1_svpp2_mdp_aal" , "top_vpp" , 29), |
63 | GATE_VPP1_0(CLK_VPP1_DL_ASYNC, "vpp1_dl_async" , "top_vpp" , 30), |
64 | GATE_VPP1_0(CLK_VPP1_LARB5_FAKE_ENG, "vpp1_larb5_fake_eng" , "top_vpp" , 31), |
65 | /* VPP1_1 */ |
66 | GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_HDR, "vpp1_svpp3_mdp_hdr" , "top_vpp" , 0), |
67 | GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_AAL, "vpp1_svpp3_mdp_aal" , "top_vpp" , 1), |
68 | GATE_VPP1_1(CLK_VPP1_SVPP2_VDO1_DL_RELAY, "vpp1_svpp2_vdo1_dl_relay" , "top_vpp" , 2), |
69 | GATE_VPP1_1(CLK_VPP1_LARB6_FAKE_ENG, "vpp1_larb6_fake_eng" , "top_vpp" , 3), |
70 | GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_RSZ, "vpp1_svpp2_mdp_rsz" , "top_vpp" , 4), |
71 | GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_RSZ, "vpp1_svpp3_mdp_rsz" , "top_vpp" , 5), |
72 | GATE_VPP1_1(CLK_VPP1_SVPP3_VDO0_DL_RELAY, "vpp1_svpp3_vdo0_dl_relay" , "top_vpp" , 6), |
73 | GATE_VPP1_1(CLK_VPP1_DISP_MUTEX, "vpp1_disp_mutex" , "top_vpp" , 7), |
74 | GATE_VPP1_1(CLK_VPP1_SVPP2_MDP_TDSHP, "vpp1_svpp2_mdp_tdshp" , "top_vpp" , 8), |
75 | GATE_VPP1_1(CLK_VPP1_SVPP3_MDP_TDSHP, "vpp1_svpp3_mdp_tdshp" , "top_vpp" , 9), |
76 | GATE_VPP1_1(CLK_VPP1_VPP0_DL1_RELAY, "vpp1_vpp0_dl1_relay" , "top_vpp" , 10), |
77 | GATE_VPP1_1(CLK_VPP1_HDMI_META, "vpp1_hdmi_meta" , "hdmirx_p" , 11), |
78 | GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_HDMI, "vpp1_vpp_split_hdmi" , "hdmirx_p" , 12), |
79 | GATE_VPP1_1(CLK_VPP1_DGI_IN, "vpp1_dgi_in" , "in_dgi" , 13), |
80 | GATE_VPP1_1(CLK_VPP1_DGI_OUT, "vpp1_dgi_out" , "top_dgi_out" , 14), |
81 | GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_DGI, "vpp1_vpp_split_dgi" , "top_dgi_out" , 15), |
82 | GATE_VPP1_1(CLK_VPP1_VPP0_DL_ASYNC, "vpp1_vpp0_dl_async" , "top_vpp" , 16), |
83 | GATE_VPP1_1(CLK_VPP1_VPP0_DL_RELAY, "vpp1_vpp0_dl_relay" , "top_vpp" , 17), |
84 | GATE_VPP1_1(CLK_VPP1_VPP_SPLIT_26M, "vpp1_vpp_split_26m" , "clk26m" , 26), |
85 | }; |
86 | |
87 | static const struct mtk_clk_desc vpp1_desc = { |
88 | .clks = vpp1_clks, |
89 | .num_clks = ARRAY_SIZE(vpp1_clks), |
90 | }; |
91 | |
92 | static const struct platform_device_id clk_mt8195_vpp1_id_table[] = { |
93 | { .name = "clk-mt8195-vpp1" , .driver_data = (kernel_ulong_t)&vpp1_desc }, |
94 | { /* sentinel */ } |
95 | }; |
96 | MODULE_DEVICE_TABLE(platform, clk_mt8195_vpp1_id_table); |
97 | |
98 | static struct platform_driver clk_mt8195_vpp1_drv = { |
99 | .probe = mtk_clk_pdev_probe, |
100 | .remove_new = mtk_clk_pdev_remove, |
101 | .driver = { |
102 | .name = "clk-mt8195-vpp1" , |
103 | }, |
104 | .id_table = clk_mt8195_vpp1_id_table, |
105 | }; |
106 | module_platform_driver(clk_mt8195_vpp1_drv); |
107 | MODULE_LICENSE("GPL" ); |
108 | |