1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | // |
3 | // Copyright (c) 2021 MediaTek Inc. |
4 | // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> |
5 | |
6 | #include "clk-gate.h" |
7 | #include "clk-mtk.h" |
8 | |
9 | #include <dt-bindings/clock/mt8195-clk.h> |
10 | #include <linux/clk-provider.h> |
11 | #include <linux/platform_device.h> |
12 | |
13 | static const struct mtk_gate_regs wpe_cg_regs = { |
14 | .set_ofs = 0x0, |
15 | .clr_ofs = 0x0, |
16 | .sta_ofs = 0x0, |
17 | }; |
18 | |
19 | static const struct mtk_gate_regs wpe_vpp0_cg_regs = { |
20 | .set_ofs = 0x58, |
21 | .clr_ofs = 0x58, |
22 | .sta_ofs = 0x58, |
23 | }; |
24 | |
25 | static const struct mtk_gate_regs wpe_vpp1_cg_regs = { |
26 | .set_ofs = 0x5c, |
27 | .clr_ofs = 0x5c, |
28 | .sta_ofs = 0x5c, |
29 | }; |
30 | |
31 | #define GATE_WPE(_id, _name, _parent, _shift) \ |
32 | GATE_MTK(_id, _name, _parent, &wpe_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
33 | |
34 | #define GATE_WPE_VPP0(_id, _name, _parent, _shift) \ |
35 | GATE_MTK(_id, _name, _parent, &wpe_vpp0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
36 | |
37 | #define GATE_WPE_VPP1(_id, _name, _parent, _shift) \ |
38 | GATE_MTK(_id, _name, _parent, &wpe_vpp1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) |
39 | |
40 | static const struct mtk_gate wpe_clks[] = { |
41 | GATE_WPE(CLK_WPE_VPP0, "wpe_vpp0" , "top_wpe_vpp" , 16), |
42 | GATE_WPE(CLK_WPE_VPP1, "wpe_vpp1" , "top_wpe_vpp" , 17), |
43 | GATE_WPE(CLK_WPE_SMI_LARB7, "wpe_smi_larb7" , "top_wpe_vpp" , 18), |
44 | GATE_WPE(CLK_WPE_SMI_LARB8, "wpe_smi_larb8" , "top_wpe_vpp" , 19), |
45 | GATE_WPE(CLK_WPE_EVENT_TX, "wpe_event_tx" , "top_wpe_vpp" , 20), |
46 | GATE_WPE(CLK_WPE_SMI_LARB7_P, "wpe_smi_larb7_p" , "top_wpe_vpp" , 24), |
47 | GATE_WPE(CLK_WPE_SMI_LARB8_P, "wpe_smi_larb8_p" , "top_wpe_vpp" , 25), |
48 | }; |
49 | |
50 | static const struct mtk_gate wpe_vpp0_clks[] = { |
51 | /* WPE_VPP0 */ |
52 | GATE_WPE_VPP0(CLK_WPE_VPP0_VGEN, "wpe_vpp0_vgen" , "top_img" , 0), |
53 | GATE_WPE_VPP0(CLK_WPE_VPP0_EXT, "wpe_vpp0_ext" , "top_img" , 1), |
54 | GATE_WPE_VPP0(CLK_WPE_VPP0_VFC, "wpe_vpp0_vfc" , "top_img" , 2), |
55 | GATE_WPE_VPP0(CLK_WPE_VPP0_CACH0_TOP, "wpe_vpp0_cach0_top" , "top_img" , 3), |
56 | GATE_WPE_VPP0(CLK_WPE_VPP0_CACH0_DMA, "wpe_vpp0_cach0_dma" , "top_img" , 4), |
57 | GATE_WPE_VPP0(CLK_WPE_VPP0_CACH1_TOP, "wpe_vpp0_cach1_top" , "top_img" , 5), |
58 | GATE_WPE_VPP0(CLK_WPE_VPP0_CACH1_DMA, "wpe_vpp0_cach1_dma" , "top_img" , 6), |
59 | GATE_WPE_VPP0(CLK_WPE_VPP0_CACH2_TOP, "wpe_vpp0_cach2_top" , "top_img" , 7), |
60 | GATE_WPE_VPP0(CLK_WPE_VPP0_CACH2_DMA, "wpe_vpp0_cach2_dma" , "top_img" , 8), |
61 | GATE_WPE_VPP0(CLK_WPE_VPP0_CACH3_TOP, "wpe_vpp0_cach3_top" , "top_img" , 9), |
62 | GATE_WPE_VPP0(CLK_WPE_VPP0_CACH3_DMA, "wpe_vpp0_cach3_dma" , "top_img" , 10), |
63 | GATE_WPE_VPP0(CLK_WPE_VPP0_PSP, "wpe_vpp0_psp" , "top_img" , 11), |
64 | GATE_WPE_VPP0(CLK_WPE_VPP0_PSP2, "wpe_vpp0_psp2" , "top_img" , 12), |
65 | GATE_WPE_VPP0(CLK_WPE_VPP0_SYNC, "wpe_vpp0_sync" , "top_img" , 13), |
66 | GATE_WPE_VPP0(CLK_WPE_VPP0_C24, "wpe_vpp0_c24" , "top_img" , 14), |
67 | GATE_WPE_VPP0(CLK_WPE_VPP0_MDP_CROP, "wpe_vpp0_mdp_crop" , "top_img" , 15), |
68 | GATE_WPE_VPP0(CLK_WPE_VPP0_ISP_CROP, "wpe_vpp0_isp_crop" , "top_img" , 16), |
69 | GATE_WPE_VPP0(CLK_WPE_VPP0_TOP, "wpe_vpp0_top" , "top_img" , 17), |
70 | /* WPE_VPP1 */ |
71 | GATE_WPE_VPP1(CLK_WPE_VPP0_VECI, "wpe_vpp0_veci" , "top_img" , 0), |
72 | GATE_WPE_VPP1(CLK_WPE_VPP0_VEC2I, "wpe_vpp0_vec2i" , "top_img" , 1), |
73 | GATE_WPE_VPP1(CLK_WPE_VPP0_VEC3I, "wpe_vpp0_vec3i" , "top_img" , 2), |
74 | GATE_WPE_VPP1(CLK_WPE_VPP0_WPEO, "wpe_vpp0_wpeo" , "top_img" , 3), |
75 | GATE_WPE_VPP1(CLK_WPE_VPP0_MSKO, "wpe_vpp0_msko" , "top_img" , 4), |
76 | }; |
77 | |
78 | static const struct mtk_gate wpe_vpp1_clks[] = { |
79 | /* WPE_VPP0 */ |
80 | GATE_WPE_VPP0(CLK_WPE_VPP1_VGEN, "wpe_vpp1_vgen" , "top_img" , 0), |
81 | GATE_WPE_VPP0(CLK_WPE_VPP1_EXT, "wpe_vpp1_ext" , "top_img" , 1), |
82 | GATE_WPE_VPP0(CLK_WPE_VPP1_VFC, "wpe_vpp1_vfc" , "top_img" , 2), |
83 | GATE_WPE_VPP0(CLK_WPE_VPP1_CACH0_TOP, "wpe_vpp1_cach0_top" , "top_img" , 3), |
84 | GATE_WPE_VPP0(CLK_WPE_VPP1_CACH0_DMA, "wpe_vpp1_cach0_dma" , "top_img" , 4), |
85 | GATE_WPE_VPP0(CLK_WPE_VPP1_CACH1_TOP, "wpe_vpp1_cach1_top" , "top_img" , 5), |
86 | GATE_WPE_VPP0(CLK_WPE_VPP1_CACH1_DMA, "wpe_vpp1_cach1_dma" , "top_img" , 6), |
87 | GATE_WPE_VPP0(CLK_WPE_VPP1_CACH2_TOP, "wpe_vpp1_cach2_top" , "top_img" , 7), |
88 | GATE_WPE_VPP0(CLK_WPE_VPP1_CACH2_DMA, "wpe_vpp1_cach2_dma" , "top_img" , 8), |
89 | GATE_WPE_VPP0(CLK_WPE_VPP1_CACH3_TOP, "wpe_vpp1_cach3_top" , "top_img" , 9), |
90 | GATE_WPE_VPP0(CLK_WPE_VPP1_CACH3_DMA, "wpe_vpp1_cach3_dma" , "top_img" , 10), |
91 | GATE_WPE_VPP0(CLK_WPE_VPP1_PSP, "wpe_vpp1_psp" , "top_img" , 11), |
92 | GATE_WPE_VPP0(CLK_WPE_VPP1_PSP2, "wpe_vpp1_psp2" , "top_img" , 12), |
93 | GATE_WPE_VPP0(CLK_WPE_VPP1_SYNC, "wpe_vpp1_sync" , "top_img" , 13), |
94 | GATE_WPE_VPP0(CLK_WPE_VPP1_C24, "wpe_vpp1_c24" , "top_img" , 14), |
95 | GATE_WPE_VPP0(CLK_WPE_VPP1_MDP_CROP, "wpe_vpp1_mdp_crop" , "top_img" , 15), |
96 | GATE_WPE_VPP0(CLK_WPE_VPP1_ISP_CROP, "wpe_vpp1_isp_crop" , "top_img" , 16), |
97 | GATE_WPE_VPP0(CLK_WPE_VPP1_TOP, "wpe_vpp1_top" , "top_img" , 17), |
98 | /* WPE_VPP1 */ |
99 | GATE_WPE_VPP1(CLK_WPE_VPP1_VECI, "wpe_vpp1_veci" , "top_img" , 0), |
100 | GATE_WPE_VPP1(CLK_WPE_VPP1_VEC2I, "wpe_vpp1_vec2i" , "top_img" , 1), |
101 | GATE_WPE_VPP1(CLK_WPE_VPP1_VEC3I, "wpe_vpp1_vec3i" , "top_img" , 2), |
102 | GATE_WPE_VPP1(CLK_WPE_VPP1_WPEO, "wpe_vpp1_wpeo" , "top_img" , 3), |
103 | GATE_WPE_VPP1(CLK_WPE_VPP1_MSKO, "wpe_vpp1_msko" , "top_img" , 4), |
104 | }; |
105 | |
106 | static const struct mtk_clk_desc wpe_desc = { |
107 | .clks = wpe_clks, |
108 | .num_clks = ARRAY_SIZE(wpe_clks), |
109 | }; |
110 | |
111 | static const struct mtk_clk_desc wpe_vpp0_desc = { |
112 | .clks = wpe_vpp0_clks, |
113 | .num_clks = ARRAY_SIZE(wpe_vpp0_clks), |
114 | }; |
115 | |
116 | static const struct mtk_clk_desc wpe_vpp1_desc = { |
117 | .clks = wpe_vpp1_clks, |
118 | .num_clks = ARRAY_SIZE(wpe_vpp1_clks), |
119 | }; |
120 | |
121 | static const struct of_device_id of_match_clk_mt8195_wpe[] = { |
122 | { |
123 | .compatible = "mediatek,mt8195-wpesys" , |
124 | .data = &wpe_desc, |
125 | }, { |
126 | .compatible = "mediatek,mt8195-wpesys_vpp0" , |
127 | .data = &wpe_vpp0_desc, |
128 | }, { |
129 | .compatible = "mediatek,mt8195-wpesys_vpp1" , |
130 | .data = &wpe_vpp1_desc, |
131 | }, { |
132 | /* sentinel */ |
133 | } |
134 | }; |
135 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_wpe); |
136 | |
137 | static struct platform_driver clk_mt8195_wpe_drv = { |
138 | .probe = mtk_clk_simple_probe, |
139 | .remove_new = mtk_clk_simple_remove, |
140 | .driver = { |
141 | .name = "clk-mt8195-wpe" , |
142 | .of_match_table = of_match_clk_mt8195_wpe, |
143 | }, |
144 | }; |
145 | module_platform_driver(clk_mt8195_wpe_drv); |
146 | MODULE_LICENSE("GPL" ); |
147 | |