1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2025 MediaTek Inc.
4 * Guangjie Song <guangjie.song@mediatek.com>
5 * Copyright (c) 2025 Collabora Ltd.
6 * Laura Nao <laura.nao@collabora.com>
7 */
8#include <dt-bindings/clock/mediatek,mt8196-clock.h>
9
10#include <linux/clk.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16
17#include "clk-mtk.h"
18#include "clk-mux.h"
19
20/* MUX SEL REG */
21#define CKSYS2_CLK_CFG_UPDATE 0x0004
22#define CKSYS2_CLK_CFG_0 0x0010
23#define CKSYS2_CLK_CFG_0_SET 0x0014
24#define CKSYS2_CLK_CFG_0_CLR 0x0018
25#define CKSYS2_CLK_CFG_1 0x0020
26#define CKSYS2_CLK_CFG_1_SET 0x0024
27#define CKSYS2_CLK_CFG_1_CLR 0x0028
28#define CKSYS2_CLK_CFG_2 0x0030
29#define CKSYS2_CLK_CFG_2_SET 0x0034
30#define CKSYS2_CLK_CFG_2_CLR 0x0038
31#define CKSYS2_CLK_CFG_3 0x0040
32#define CKSYS2_CLK_CFG_3_SET 0x0044
33#define CKSYS2_CLK_CFG_3_CLR 0x0048
34#define CKSYS2_CLK_CFG_4 0x0050
35#define CKSYS2_CLK_CFG_4_SET 0x0054
36#define CKSYS2_CLK_CFG_4_CLR 0x0058
37#define CKSYS2_CLK_CFG_5 0x0060
38#define CKSYS2_CLK_CFG_5_SET 0x0064
39#define CKSYS2_CLK_CFG_5_CLR 0x0068
40#define CKSYS2_CLK_CFG_6 0x0070
41#define CKSYS2_CLK_CFG_6_SET 0x0074
42#define CKSYS2_CLK_CFG_6_CLR 0x0078
43#define CKSYS2_CLK_FENC_STATUS_MON_0 0x0174
44
45/* MUX SHIFT */
46#define TOP_MUX_SENINF0_SHIFT 0
47#define TOP_MUX_SENINF1_SHIFT 1
48#define TOP_MUX_SENINF2_SHIFT 2
49#define TOP_MUX_SENINF3_SHIFT 3
50#define TOP_MUX_SENINF4_SHIFT 4
51#define TOP_MUX_SENINF5_SHIFT 5
52#define TOP_MUX_IMG1_SHIFT 6
53#define TOP_MUX_IPE_SHIFT 7
54#define TOP_MUX_CAM_SHIFT 8
55#define TOP_MUX_CAMTM_SHIFT 9
56#define TOP_MUX_DPE_SHIFT 10
57#define TOP_MUX_VDEC_SHIFT 11
58#define TOP_MUX_CCUSYS_SHIFT 12
59#define TOP_MUX_CCUTM_SHIFT 13
60#define TOP_MUX_VENC_SHIFT 14
61#define TOP_MUX_DVO_SHIFT 15
62#define TOP_MUX_DVO_FAVT_SHIFT 16
63#define TOP_MUX_DP1_SHIFT 17
64#define TOP_MUX_DP0_SHIFT 18
65#define TOP_MUX_DISP_SHIFT 19
66#define TOP_MUX_MDP_SHIFT 20
67#define TOP_MUX_MMINFRA_SHIFT 21
68#define TOP_MUX_MMINFRA_SNOC_SHIFT 22
69#define TOP_MUX_MMUP_SHIFT 23
70#define TOP_MUX_MMINFRA_AO_SHIFT 26
71
72/* HW Voter REG */
73#define HWV_CG_30_SET 0x0058
74#define HWV_CG_30_CLR 0x005c
75#define HWV_CG_30_DONE 0x2c2c
76
77#define MM_HWV_CG_30_SET 0x00f0
78#define MM_HWV_CG_30_CLR 0x00f4
79#define MM_HWV_CG_30_DONE 0x2c78
80#define MM_HWV_CG_31_SET 0x00f8
81#define MM_HWV_CG_31_CLR 0x00fc
82#define MM_HWV_CG_31_DONE 0x2c7c
83#define MM_HWV_CG_32_SET 0x0100
84#define MM_HWV_CG_32_CLR 0x0104
85#define MM_HWV_CG_32_DONE 0x2c80
86#define MM_HWV_CG_33_SET 0x0108
87#define MM_HWV_CG_33_CLR 0x010c
88#define MM_HWV_CG_33_DONE 0x2c84
89#define MM_HWV_CG_34_SET 0x0110
90#define MM_HWV_CG_34_CLR 0x0114
91#define MM_HWV_CG_34_DONE 0x2c88
92#define MM_HWV_CG_35_SET 0x0118
93#define MM_HWV_CG_35_CLR 0x011c
94#define MM_HWV_CG_35_DONE 0x2c8c
95#define MM_HWV_CG_36_SET 0x0120
96#define MM_HWV_CG_36_CLR 0x0124
97#define MM_HWV_CG_36_DONE 0x2c90
98#define MM_HWV_MUX_UPDATE_31_0 0x0240
99
100static const struct mtk_fixed_factor top_divs[] = {
101 FACTOR(CLK_TOP2_MAINPLL2_D2, "mainpll2_d2", "mainpll2", 1, 2),
102 FACTOR(CLK_TOP2_MAINPLL2_D3, "mainpll2_d3", "mainpll2", 1, 3),
103 FACTOR(CLK_TOP2_MAINPLL2_D4, "mainpll2_d4", "mainpll2", 1, 4),
104 FACTOR(CLK_TOP2_MAINPLL2_D4_D2, "mainpll2_d4_d2", "mainpll2", 1, 8),
105 FACTOR(CLK_TOP2_MAINPLL2_D4_D4, "mainpll2_d4_d4", "mainpll2", 1, 16),
106 FACTOR(CLK_TOP2_MAINPLL2_D5, "mainpll2_d5", "mainpll2", 1, 5),
107 FACTOR(CLK_TOP2_MAINPLL2_D5_D2, "mainpll2_d5_d2", "mainpll2", 1, 10),
108 FACTOR(CLK_TOP2_MAINPLL2_D6, "mainpll2_d6", "mainpll2", 1, 6),
109 FACTOR(CLK_TOP2_MAINPLL2_D6_D2, "mainpll2_d6_d2", "mainpll2", 1, 12),
110 FACTOR(CLK_TOP2_MAINPLL2_D7, "mainpll2_d7", "mainpll2", 1, 7),
111 FACTOR(CLK_TOP2_MAINPLL2_D7_D2, "mainpll2_d7_d2", "mainpll2", 1, 14),
112 FACTOR(CLK_TOP2_MAINPLL2_D9, "mainpll2_d9", "mainpll2", 1, 9),
113 FACTOR(CLK_TOP2_UNIVPLL2_D3, "univpll2_d3", "univpll2", 1, 3),
114 FACTOR(CLK_TOP2_UNIVPLL2_D4, "univpll2_d4", "univpll2", 1, 4),
115 FACTOR(CLK_TOP2_UNIVPLL2_D4_D2, "univpll2_d4_d2", "univpll2", 1, 8),
116 FACTOR(CLK_TOP2_UNIVPLL2_D5, "univpll2_d5", "univpll2", 1, 5),
117 FACTOR(CLK_TOP2_UNIVPLL2_D5_D2, "univpll2_d5_d2", "univpll2", 1, 10),
118 FACTOR(CLK_TOP2_UNIVPLL2_D6, "univpll2_d6", "univpll2", 1, 6),
119 FACTOR(CLK_TOP2_UNIVPLL2_D6_D2, "univpll2_d6_d2", "univpll2", 1, 12),
120 FACTOR(CLK_TOP2_UNIVPLL2_D6_D4, "univpll2_d6_d4", "univpll2", 1, 24),
121 FACTOR(CLK_TOP2_UNIVPLL2_D7, "univpll2_d7", "univpll2", 1, 7),
122 FACTOR(CLK_TOP2_IMGPLL_D2, "imgpll_d2", "imgpll", 1, 2),
123 FACTOR(CLK_TOP2_IMGPLL_D4, "imgpll_d4", "imgpll", 1, 4),
124 FACTOR(CLK_TOP2_IMGPLL_D5, "imgpll_d5", "imgpll", 1, 5),
125 FACTOR(CLK_TOP2_IMGPLL_D5_D2, "imgpll_d5_d2", "imgpll", 1, 10),
126 FACTOR(CLK_TOP2_MMPLL2_D3, "mmpll2_d3", "mmpll2", 1, 3),
127 FACTOR(CLK_TOP2_MMPLL2_D4, "mmpll2_d4", "mmpll2", 1, 4),
128 FACTOR(CLK_TOP2_MMPLL2_D4_D2, "mmpll2_d4_d2", "mmpll2", 1, 8),
129 FACTOR(CLK_TOP2_MMPLL2_D5, "mmpll2_d5", "mmpll2", 1, 5),
130 FACTOR(CLK_TOP2_MMPLL2_D5_D2, "mmpll2_d5_d2", "mmpll2", 1, 10),
131 FACTOR(CLK_TOP2_MMPLL2_D6, "mmpll2_d6", "mmpll2", 1, 6),
132 FACTOR(CLK_TOP2_MMPLL2_D6_D2, "mmpll2_d6_d2", "mmpll2", 1, 12),
133 FACTOR(CLK_TOP2_MMPLL2_D7, "mmpll2_d7", "mmpll2", 1, 7),
134 FACTOR(CLK_TOP2_MMPLL2_D9, "mmpll2_d9", "mmpll2", 1, 9),
135 FACTOR(CLK_TOP2_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
136 FACTOR(CLK_TOP2_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
137 FACTOR(CLK_TOP2_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 1, 16),
138 FACTOR(CLK_TOP2_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
139 FACTOR(CLK_TOP2_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
140 FACTOR(CLK_TOP2_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
141 FACTOR(CLK_TOP2_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 92, 1473),
142 FACTOR(CLK_TOP2_TVDPLL3_D2, "tvdpll3_d2", "tvdpll3", 1, 2),
143 FACTOR(CLK_TOP2_TVDPLL3_D4, "tvdpll3_d4", "tvdpll3", 1, 4),
144 FACTOR(CLK_TOP2_TVDPLL3_D8, "tvdpll3_d8", "tvdpll3", 1, 8),
145 FACTOR(CLK_TOP2_TVDPLL3_D16, "tvdpll3_d16", "tvdpll3", 92, 1473),
146};
147
148static const char * const seninf_parents[] = {
149 "clk26m",
150 "ck_osc_d10",
151 "ck_osc_d8",
152 "ck_osc_d5",
153 "ck_osc_d4",
154 "univpll2_d6_d2",
155 "mainpll2_d9",
156 "ck_osc_d2",
157 "mainpll2_d4_d2",
158 "univpll2_d4_d2",
159 "mmpll2_d4_d2",
160 "univpll2_d7",
161 "mainpll2_d6",
162 "mmpll2_d7",
163 "univpll2_d6",
164 "univpll2_d5"
165};
166
167static const char * const img1_parents[] = {
168 "clk26m",
169 "ck_osc_d4",
170 "ck_osc_d3",
171 "mmpll2_d6_d2",
172 "ck_osc_d2",
173 "imgpll_d5_d2",
174 "mmpll2_d5_d2",
175 "univpll2_d4_d2",
176 "mmpll2_d4_d2",
177 "mmpll2_d7",
178 "univpll2_d6",
179 "mmpll2_d6",
180 "univpll2_d5",
181 "mmpll2_d5",
182 "univpll2_d4",
183 "imgpll_d4"
184};
185
186static const char * const ipe_parents[] = {
187 "clk26m",
188 "ck_osc_d4",
189 "ck_osc_d3",
190 "ck_osc_d2",
191 "univpll2_d6",
192 "mmpll2_d6",
193 "univpll2_d5",
194 "imgpll_d5",
195 "ck_mainpll_d4",
196 "mmpll2_d5",
197 "imgpll_d4"
198};
199
200static const char * const cam_parents[] = {
201 "clk26m",
202 "ck_osc_d10",
203 "ck_osc_d4",
204 "ck_osc_d3",
205 "ck_osc_d2",
206 "mmpll2_d5_d2",
207 "univpll2_d4_d2",
208 "univpll2_d7",
209 "mmpll2_d7",
210 "univpll2_d6",
211 "mmpll2_d6",
212 "univpll2_d5",
213 "mmpll2_d5",
214 "univpll2_d4",
215 "imgpll_d4",
216 "mmpll2_d4"
217};
218
219static const char * const camtm_parents[] = {
220 "clk26m",
221 "univpll2_d6_d4",
222 "ck_osc_d4",
223 "ck_osc_d3",
224 "univpll2_d6_d2"
225};
226
227static const char * const dpe_parents[] = {
228 "clk26m",
229 "mmpll2_d5_d2",
230 "univpll2_d4_d2",
231 "mmpll2_d7",
232 "univpll2_d6",
233 "mmpll2_d6",
234 "univpll2_d5",
235 "mmpll2_d5",
236 "imgpll_d4",
237 "mmpll2_d4"
238};
239
240static const char * const vdec_parents[] = {
241 "clk26m",
242 "ck_mainpll_d5_d2",
243 "mainpll2_d4_d4",
244 "mainpll2_d7_d2",
245 "mainpll2_d6_d2",
246 "mainpll2_d5_d2",
247 "mainpll2_d9",
248 "mainpll2_d4_d2",
249 "mainpll2_d7",
250 "mainpll2_d6",
251 "univpll2_d6",
252 "mainpll2_d5",
253 "mainpll2_d4",
254 "imgpll_d2"
255};
256
257static const char * const ccusys_parents[] = {
258 "clk26m",
259 "ck_osc_d4",
260 "ck_osc_d3",
261 "ck_osc_d2",
262 "mmpll2_d5_d2",
263 "univpll2_d4_d2",
264 "mmpll2_d7",
265 "univpll2_d6",
266 "mmpll2_d6",
267 "univpll2_d5",
268 "mainpll2_d4",
269 "mainpll2_d3",
270 "univpll2_d3"
271};
272
273static const char * const ccutm_parents[] = {
274 "clk26m",
275 "univpll2_d6_d4",
276 "ck_osc_d4",
277 "ck_osc_d3",
278 "univpll2_d6_d2"
279};
280
281static const char * const venc_parents[] = {
282 "clk26m",
283 "mainpll2_d5_d2",
284 "univpll2_d5_d2",
285 "mainpll2_d4_d2",
286 "mmpll2_d9",
287 "univpll2_d4_d2",
288 "mmpll2_d4_d2",
289 "mainpll2_d6",
290 "univpll2_d6",
291 "mainpll2_d5",
292 "mmpll2_d6",
293 "univpll2_d5",
294 "mainpll2_d4",
295 "univpll2_d4",
296 "univpll2_d3"
297};
298
299static const char * const dp1_parents[] = {
300 "clk26m",
301 "tvdpll2_d16",
302 "tvdpll2_d8",
303 "tvdpll2_d4",
304 "tvdpll2_d2"
305};
306
307static const char * const dp0_parents[] = {
308 "clk26m",
309 "tvdpll1_d16",
310 "tvdpll1_d8",
311 "tvdpll1_d4",
312 "ck_tvdpll1_d2"
313};
314
315static const char * const disp_parents[] = {
316 "clk26m",
317 "ck_mainpll_d5_d2",
318 "ck_mainpll_d4_d2",
319 "ck_mainpll_d6",
320 "mainpll2_d5",
321 "mmpll2_d6",
322 "mainpll2_d4",
323 "univpll2_d4",
324 "mainpll2_d3"
325};
326
327static const char * const mdp_parents[] = {
328 "clk26m",
329 "ck_mainpll_d5_d2",
330 "mainpll2_d5_d2",
331 "mmpll2_d6_d2",
332 "mainpll2_d9",
333 "mainpll2_d4_d2",
334 "mainpll2_d7",
335 "mainpll2_d6",
336 "mainpll2_d5",
337 "mmpll2_d6",
338 "mainpll2_d4",
339 "univpll2_d4",
340 "mainpll2_d3"
341};
342
343static const char * const mminfra_parents[] = {
344 "clk26m",
345 "ck_osc_d4",
346 "ck_mainpll_d7_d2",
347 "ck_mainpll_d5_d2",
348 "ck_mainpll_d9",
349 "mmpll2_d6_d2",
350 "mainpll2_d4_d2",
351 "ck_mainpll_d6",
352 "univpll2_d6",
353 "mainpll2_d5",
354 "mmpll2_d6",
355 "univpll2_d5",
356 "mainpll2_d4",
357 "univpll2_d4",
358 "mainpll2_d3",
359 "univpll2_d3"
360};
361
362static const char * const mminfra_snoc_parents[] = {
363 "clk26m",
364 "ck_osc_d4",
365 "ck_mainpll_d7_d2",
366 "ck_mainpll_d9",
367 "ck_mainpll_d7",
368 "ck_mainpll_d6",
369 "mmpll2_d4_d2",
370 "ck_mainpll_d5",
371 "ck_mainpll_d4",
372 "univpll2_d4",
373 "mmpll2_d4",
374 "mainpll2_d3",
375 "univpll2_d3",
376 "mmpll2_d3",
377 "mainpll2_d2"
378};
379
380static const char * const mmup_parents[] = {
381 "clk26m",
382 "mainpll2_d6",
383 "mainpll2_d5",
384 "ck_osc_d2",
385 "ck_osc",
386 "ck_mainpll_d4",
387 "univpll2_d4",
388 "mainpll2_d3"
389};
390
391static const char * const mminfra_ao_parents[] = {
392 "clk26m",
393 "ck_osc_d4",
394 "ck_mainpll_d3"
395};
396
397static const char * const dvo_parents[] = {
398 "clk26m",
399 "tvdpll3_d16",
400 "tvdpll3_d8",
401 "tvdpll3_d4",
402 "tvdpll3_d2"
403};
404
405static const char * const dvo_favt_parents[] = {
406 "clk26m",
407 "tvdpll3_d16",
408 "tvdpll3_d8",
409 "tvdpll3_d4",
410 "vlp_apll1",
411 "vlp_apll2",
412 "tvdpll3_d2"
413};
414
415static const struct mtk_mux top_muxes[] = {
416 /* CKSYS2_CLK_CFG_0 */
417 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF0, "seninf0", seninf_parents,
418 CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
419 MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
420 0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF0_SHIFT,
421 CKSYS2_CLK_FENC_STATUS_MON_0, 31),
422 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF1, "seninf1", seninf_parents,
423 CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
424 MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
425 8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF1_SHIFT,
426 CKSYS2_CLK_FENC_STATUS_MON_0, 30),
427 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF2, "seninf2", seninf_parents,
428 CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
429 MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
430 16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF2_SHIFT,
431 CKSYS2_CLK_FENC_STATUS_MON_0, 29),
432 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF3, "seninf3", seninf_parents,
433 CKSYS2_CLK_CFG_0, CKSYS2_CLK_CFG_0_SET, CKSYS2_CLK_CFG_0_CLR,
434 MM_HWV_CG_30_DONE, MM_HWV_CG_30_SET, MM_HWV_CG_30_CLR,
435 24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF3_SHIFT,
436 CKSYS2_CLK_FENC_STATUS_MON_0, 28),
437 /* CKSYS2_CLK_CFG_1 */
438 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF4, "seninf4", seninf_parents,
439 CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
440 MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
441 0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF4_SHIFT,
442 CKSYS2_CLK_FENC_STATUS_MON_0, 27),
443 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_SENINF5, "seninf5", seninf_parents,
444 CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
445 MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
446 8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_SENINF5_SHIFT,
447 CKSYS2_CLK_FENC_STATUS_MON_0, 26),
448 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_IMG1, "img1", img1_parents,
449 CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
450 MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
451 16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_IMG1_SHIFT,
452 CKSYS2_CLK_FENC_STATUS_MON_0, 25),
453 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_IPE, "ipe", ipe_parents,
454 CKSYS2_CLK_CFG_1, CKSYS2_CLK_CFG_1_SET, CKSYS2_CLK_CFG_1_CLR,
455 MM_HWV_CG_31_DONE, MM_HWV_CG_31_SET, MM_HWV_CG_31_CLR,
456 24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_IPE_SHIFT,
457 CKSYS2_CLK_FENC_STATUS_MON_0, 24),
458 /* CKSYS2_CLK_CFG_2 */
459 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CAM, "cam", cam_parents,
460 CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
461 MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
462 0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CAM_SHIFT,
463 CKSYS2_CLK_FENC_STATUS_MON_0, 23),
464 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CAMTM, "camtm", camtm_parents,
465 CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
466 MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
467 8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CAMTM_SHIFT,
468 CKSYS2_CLK_FENC_STATUS_MON_0, 22),
469 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_DPE, "dpe", dpe_parents,
470 CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
471 MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
472 16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DPE_SHIFT,
473 CKSYS2_CLK_FENC_STATUS_MON_0, 21),
474 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_VDEC, "vdec", vdec_parents,
475 CKSYS2_CLK_CFG_2, CKSYS2_CLK_CFG_2_SET, CKSYS2_CLK_CFG_2_CLR,
476 MM_HWV_CG_32_DONE, MM_HWV_CG_32_SET, MM_HWV_CG_32_CLR,
477 24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_VDEC_SHIFT,
478 CKSYS2_CLK_FENC_STATUS_MON_0, 20),
479 /* CKSYS2_CLK_CFG_3 */
480 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CCUSYS, "ccusys", ccusys_parents,
481 CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
482 MM_HWV_CG_33_DONE, MM_HWV_CG_33_SET, MM_HWV_CG_33_CLR,
483 0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CCUSYS_SHIFT,
484 CKSYS2_CLK_FENC_STATUS_MON_0, 19),
485 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_CCUTM, "ccutm", ccutm_parents,
486 CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
487 MM_HWV_CG_33_DONE, MM_HWV_CG_33_SET, MM_HWV_CG_33_CLR,
488 8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_CCUTM_SHIFT,
489 CKSYS2_CLK_FENC_STATUS_MON_0, 18),
490 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_VENC, "venc", venc_parents,
491 CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
492 MM_HWV_CG_33_DONE, MM_HWV_CG_33_SET, MM_HWV_CG_33_CLR,
493 16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_VENC_SHIFT,
494 CKSYS2_CLK_FENC_STATUS_MON_0, 17),
495 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DVO, "dvo", dvo_parents,
496 CKSYS2_CLK_CFG_3, CKSYS2_CLK_CFG_3_SET, CKSYS2_CLK_CFG_3_CLR,
497 24, 3, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DVO_SHIFT,
498 CKSYS2_CLK_FENC_STATUS_MON_0, 16),
499 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DVO_FAVT, "dvo_favt", dvo_favt_parents,
500 CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
501 0, 3, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DVO_FAVT_SHIFT,
502 CKSYS2_CLK_FENC_STATUS_MON_0, 15),
503 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DP1, "dp1", dp1_parents,
504 CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
505 8, 3, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DP1_SHIFT,
506 CKSYS2_CLK_FENC_STATUS_MON_0, 14),
507 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_DP0, "dp0", dp0_parents,
508 CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
509 16, 3, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DP0_SHIFT,
510 CKSYS2_CLK_FENC_STATUS_MON_0, 13),
511 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_DISP, "disp", disp_parents,
512 CKSYS2_CLK_CFG_4, CKSYS2_CLK_CFG_4_SET, CKSYS2_CLK_CFG_4_CLR,
513 MM_HWV_CG_34_DONE, MM_HWV_CG_34_SET, MM_HWV_CG_34_CLR,
514 24, 4, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_DISP_SHIFT,
515 CKSYS2_CLK_FENC_STATUS_MON_0, 12),
516 /* CKSYS2_CLK_CFG_5 */
517 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MDP, "mdp", mdp_parents,
518 CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
519 MM_HWV_CG_35_DONE, MM_HWV_CG_35_SET, MM_HWV_CG_35_CLR,
520 0, 4, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MDP_SHIFT,
521 CKSYS2_CLK_FENC_STATUS_MON_0, 11),
522 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MMINFRA, "mminfra", mminfra_parents,
523 CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
524 MM_HWV_CG_35_DONE, MM_HWV_CG_35_SET, MM_HWV_CG_35_CLR,
525 8, 4, 15, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SHIFT,
526 CKSYS2_CLK_FENC_STATUS_MON_0, 10),
527 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MMINFRA_SNOC, "mminfra_snoc", mminfra_snoc_parents,
528 CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
529 MM_HWV_CG_35_DONE, MM_HWV_CG_35_SET, MM_HWV_CG_35_CLR,
530 16, 4, 23, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_SNOC_SHIFT,
531 CKSYS2_CLK_FENC_STATUS_MON_0, 9),
532 MUX_GATE_FENC_CLR_SET_UPD(CLK_TOP2_MMUP, "mmup", mmup_parents,
533 CKSYS2_CLK_CFG_5, CKSYS2_CLK_CFG_5_SET, CKSYS2_CLK_CFG_5_CLR,
534 24, 3, 31, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMUP_SHIFT,
535 CKSYS2_CLK_FENC_STATUS_MON_0, 8),
536 /* CKSYS2_CLK_CFG_6 */
537 MUX_GATE_HWV_FENC_CLR_SET_UPD(CLK_TOP2_MMINFRA_AO, "mminfra_ao", mminfra_ao_parents,
538 CKSYS2_CLK_CFG_6, CKSYS2_CLK_CFG_6_SET, CKSYS2_CLK_CFG_6_CLR,
539 MM_HWV_CG_36_DONE, MM_HWV_CG_36_SET, MM_HWV_CG_36_CLR,
540 16, 2, 7, CKSYS2_CLK_CFG_UPDATE, TOP_MUX_MMINFRA_AO_SHIFT,
541 CKSYS2_CLK_FENC_STATUS_MON_0, 5),
542};
543
544static const struct mtk_clk_desc topck_desc = {
545 .factor_clks = top_divs,
546 .num_factor_clks = ARRAY_SIZE(top_divs),
547 .mux_clks = top_muxes,
548 .num_mux_clks = ARRAY_SIZE(top_muxes),
549};
550
551static const struct of_device_id of_match_clk_mt8196_ck[] = {
552 { .compatible = "mediatek,mt8196-topckgen-gp2", .data = &topck_desc },
553 { /* sentinel */ }
554};
555MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_ck);
556
557static struct platform_driver clk_mt8196_topck_drv = {
558 .probe = mtk_clk_simple_probe,
559 .remove = mtk_clk_simple_remove,
560 .driver = {
561 .name = "clk-mt8196-topck2",
562 .of_match_table = of_match_clk_mt8196_ck,
563 },
564};
565
566MODULE_DESCRIPTION("MediaTek MT8196 GP2 top clock generators driver");
567module_platform_driver(clk_mt8196_topck_drv);
568MODULE_LICENSE("GPL");
569

source code of linux/drivers/clk/mediatek/clk-mt8196-topckgen2.c