1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2022 MediaTek Inc. |
4 | * Copyright (c) 2023 Collabora Ltd. |
5 | */ |
6 | |
7 | #include <dt-bindings/clock/mediatek,mt8365-clk.h> |
8 | #include <linux/clk.h> |
9 | #include <linux/of.h> |
10 | #include <linux/platform_device.h> |
11 | |
12 | #include "clk-pll.h" |
13 | #include "clk-mtk.h" |
14 | |
15 | #define MT8365_PLL_FMAX (3800UL * MHZ) |
16 | #define MT8365_PLL_FMIN (1500UL * MHZ) |
17 | #define CON0_MT8365_RST_BAR BIT(23) |
18 | |
19 | #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ |
20 | _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ |
21 | _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table, \ |
22 | _rst_bar_mask, _pcw_chg_reg) { \ |
23 | .id = _id, \ |
24 | .name = _name, \ |
25 | .reg = _reg, \ |
26 | .pwr_reg = _pwr_reg, \ |
27 | .en_mask = _en_mask, \ |
28 | .flags = _flags, \ |
29 | .rst_bar_mask = _rst_bar_mask, \ |
30 | .fmax = MT8365_PLL_FMAX, \ |
31 | .fmin = MT8365_PLL_FMIN, \ |
32 | .pcwbits = _pcwbits, \ |
33 | .pcwibits = 8, \ |
34 | .pd_reg = _pd_reg, \ |
35 | .pd_shift = _pd_shift, \ |
36 | .tuner_reg = _tuner_reg, \ |
37 | .tuner_en_reg = _tuner_en_reg, \ |
38 | .tuner_en_bit = _tuner_en_bit, \ |
39 | .pcw_reg = _pcw_reg, \ |
40 | .pcw_shift = _pcw_shift, \ |
41 | .pcw_chg_reg = _pcw_chg_reg, \ |
42 | .div_table = _div_table, \ |
43 | } |
44 | |
45 | #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ |
46 | _pd_reg, _pd_shift, _tuner_reg, \ |
47 | _tuner_en_reg, _tuner_en_bit, _pcw_reg, \ |
48 | _pcw_shift, _rst_bar_mask, _pcw_chg_reg) \ |
49 | PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ |
50 | _pcwbits, _pd_reg, _pd_shift, \ |
51 | _tuner_reg, _tuner_en_reg, _tuner_en_bit, \ |
52 | _pcw_reg, _pcw_shift, NULL, _rst_bar_mask, \ |
53 | _pcw_chg_reg) \ |
54 | |
55 | static const struct mtk_pll_div_table armpll_div_table[] = { |
56 | { .div = 0, .freq = MT8365_PLL_FMAX }, |
57 | { .div = 1, .freq = 1500 * MHZ }, |
58 | { .div = 2, .freq = 750 * MHZ }, |
59 | { .div = 3, .freq = 375 * MHZ }, |
60 | { .div = 4, .freq = 182500000 }, |
61 | { } /* sentinel */ |
62 | }; |
63 | |
64 | static const struct mtk_pll_div_table mfgpll_div_table[] = { |
65 | { .div = 0, .freq = MT8365_PLL_FMAX }, |
66 | { .div = 1, .freq = 1600 * MHZ }, |
67 | { .div = 2, .freq = 800 * MHZ }, |
68 | { .div = 3, .freq = 400 * MHZ }, |
69 | { .div = 4, .freq = 200 * MHZ }, |
70 | { } /* sentinel */ |
71 | }; |
72 | |
73 | static const struct mtk_pll_div_table dsppll_div_table[] = { |
74 | { .div = 0, .freq = MT8365_PLL_FMAX }, |
75 | { .div = 1, .freq = 1600 * MHZ }, |
76 | { .div = 2, .freq = 600 * MHZ }, |
77 | { .div = 3, .freq = 400 * MHZ }, |
78 | { .div = 4, .freq = 200 * MHZ }, |
79 | { } /* sentinel */ |
80 | }; |
81 | |
82 | static const struct mtk_pll_data plls[] = { |
83 | PLL_B(CLK_APMIXED_ARMPLL, "armpll" , 0x030C, 0x0318, 0x00000001, PLL_AO, |
84 | 22, 0x0310, 24, 0, 0, 0, 0x0310, 0, armpll_div_table, 0, 0), |
85 | PLL(CLK_APMIXED_MAINPLL, "mainpll" , 0x0228, 0x0234, 0xFF000001, |
86 | HAVE_RST_BAR, 22, 0x022C, 24, 0, 0, 0, 0x022C, 0, CON0_MT8365_RST_BAR, 0), |
87 | PLL(CLK_APMIXED_UNIVPLL, "univpll2" , 0x0208, 0x0214, 0xFF000001, |
88 | HAVE_RST_BAR, 22, 0x020C, 24, 0, 0, 0, 0x020C, 0, CON0_MT8365_RST_BAR, 0), |
89 | PLL_B(CLK_APMIXED_MFGPLL, "mfgpll" , 0x0218, 0x0224, 0x00000001, 0, 22, |
90 | 0x021C, 24, 0, 0, 0, 0x021C, 0, mfgpll_div_table, 0, 0), |
91 | PLL(CLK_APMIXED_MSDCPLL, "msdcpll" , 0x0350, 0x035C, 0x00000001, 0, 22, |
92 | 0x0354, 24, 0, 0, 0, 0x0354, 0, 0, 0), |
93 | PLL(CLK_APMIXED_MMPLL, "mmpll" , 0x0330, 0x033C, 0x00000001, 0, 22, |
94 | 0x0334, 24, 0, 0, 0, 0x0334, 0, 0, 0), |
95 | PLL(CLK_APMIXED_APLL1, "apll1" , 0x031C, 0x032C, 0x00000001, 0, 32, |
96 | 0x0320, 24, 0x0040, 0x000C, 0, 0x0324, 0, 0, 0x0320), |
97 | PLL(CLK_APMIXED_APLL2, "apll2" , 0x0360, 0x0370, 0x00000001, 0, 32, |
98 | 0x0364, 24, 0x004C, 0x000C, 5, 0x0368, 0, 0, 0x0364), |
99 | PLL(CLK_APMIXED_LVDSPLL, "lvdspll" , 0x0374, 0x0380, 0x00000001, 0, 22, |
100 | 0x0378, 24, 0, 0, 0, 0x0378, 0, 0, 0), |
101 | PLL_B(CLK_APMIXED_DSPPLL, "dsppll" , 0x0390, 0x039C, 0x00000001, 0, 22, |
102 | 0x0394, 24, 0, 0, 0, 0x0394, 0, dsppll_div_table, 0, 0), |
103 | PLL(CLK_APMIXED_APUPLL, "apupll" , 0x03A0, 0x03AC, 0x00000001, 0, 22, |
104 | 0x03A4, 24, 0, 0, 0, 0x03A4, 0, 0, 0), |
105 | }; |
106 | |
107 | static int clk_mt8365_apmixed_probe(struct platform_device *pdev) |
108 | { |
109 | void __iomem *base; |
110 | struct clk_hw_onecell_data *clk_data; |
111 | struct device_node *node = pdev->dev.of_node; |
112 | struct device *dev = &pdev->dev; |
113 | struct clk_hw *hw; |
114 | int ret; |
115 | |
116 | base = devm_platform_ioremap_resource(pdev, index: 0); |
117 | if (IS_ERR(ptr: base)) |
118 | return PTR_ERR(ptr: base); |
119 | |
120 | clk_data = mtk_devm_alloc_clk_data(dev, CLK_APMIXED_NR_CLK); |
121 | if (!clk_data) |
122 | return -ENOMEM; |
123 | |
124 | hw = devm_clk_hw_register_gate(dev, "univ_en" , "univpll2" , 0, |
125 | base + 0x204, 0, 0, NULL); |
126 | if (IS_ERR(ptr: hw)) |
127 | return PTR_ERR(ptr: hw); |
128 | clk_data->hws[CLK_APMIXED_UNIV_EN] = hw; |
129 | |
130 | hw = devm_clk_hw_register_gate(dev, "usb20_en" , "univ_en" , 0, |
131 | base + 0x204, 1, 0, NULL); |
132 | if (IS_ERR(ptr: hw)) |
133 | return PTR_ERR(ptr: hw); |
134 | clk_data->hws[CLK_APMIXED_USB20_EN] = hw; |
135 | |
136 | ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); |
137 | if (ret) |
138 | return ret; |
139 | |
140 | ret = of_clk_add_hw_provider(np: node, get: of_clk_hw_onecell_get, data: clk_data); |
141 | if (ret) |
142 | goto unregister_plls; |
143 | |
144 | return 0; |
145 | |
146 | unregister_plls: |
147 | mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); |
148 | |
149 | return ret; |
150 | } |
151 | |
152 | static const struct of_device_id of_match_clk_mt8365_apmixed[] = { |
153 | { .compatible = "mediatek,mt8365-apmixedsys" }, |
154 | { /* sentinel */ } |
155 | }; |
156 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_apmixed); |
157 | |
158 | static struct platform_driver clk_mt8365_apmixed_drv = { |
159 | .probe = clk_mt8365_apmixed_probe, |
160 | .driver = { |
161 | .name = "clk-mt8365-apmixed" , |
162 | .of_match_table = of_match_clk_mt8365_apmixed, |
163 | }, |
164 | }; |
165 | builtin_platform_driver(clk_mt8365_apmixed_drv) |
166 | MODULE_LICENSE("GPL" ); |
167 | |