| 1 | // SPDX-License-Identifier: GPL-2.0 |
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| 2 | /* |
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| 3 | * Copyright (C) 2022 MediaTek Inc. |
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| 4 | */ |
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| 5 | |
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| 6 | #include <dt-bindings/clock/mediatek,mt8365-clk.h> |
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| 7 | #include <linux/clk-provider.h> |
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| 8 | #include <linux/platform_device.h> |
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| 9 | |
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| 10 | #include "clk-gate.h" |
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| 11 | #include "clk-mtk.h" |
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| 12 | |
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| 13 | static const struct mtk_gate_regs apu_cg_regs = { |
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| 14 | .set_ofs = 0x4, |
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| 15 | .clr_ofs = 0x8, |
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| 16 | .sta_ofs = 0x0, |
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| 17 | }; |
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| 18 | |
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| 19 | #define GATE_APU(_id, _name, _parent, _shift) \ |
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| 20 | GATE_MTK(_id, _name, _parent, &apu_cg_regs, _shift, \ |
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| 21 | &mtk_clk_gate_ops_setclr) |
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| 22 | |
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| 23 | static const struct mtk_gate apu_clks[] = { |
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| 24 | GATE_APU(CLK_APU_AHB, "apu_ahb" , "ifr_apu_axi" , 5), |
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| 25 | GATE_APU(CLK_APU_EDMA, "apu_edma" , "apu_sel" , 4), |
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| 26 | GATE_APU(CLK_APU_IF_CK, "apu_if_ck" , "apu_if_sel" , 3), |
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| 27 | GATE_APU(CLK_APU_JTAG, "apu_jtag" , "clk26m" , 2), |
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| 28 | GATE_APU(CLK_APU_AXI, "apu_axi" , "apu_sel" , 1), |
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| 29 | GATE_APU(CLK_APU_IPU_CK, "apu_ck" , "apu_sel" , 0), |
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| 30 | }; |
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| 31 | |
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| 32 | static const struct mtk_clk_desc apu_desc = { |
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| 33 | .clks = apu_clks, |
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| 34 | .num_clks = ARRAY_SIZE(apu_clks), |
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| 35 | }; |
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| 36 | |
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| 37 | static const struct of_device_id of_match_clk_mt8365_apu[] = { |
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| 38 | { |
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| 39 | .compatible = "mediatek,mt8365-apu" , |
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| 40 | .data = &apu_desc, |
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| 41 | }, { |
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| 42 | /* sentinel */ |
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| 43 | } |
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| 44 | }; |
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| 45 | MODULE_DEVICE_TABLE(of, of_match_clk_mt8365_apu); |
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| 46 | |
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| 47 | static struct platform_driver clk_mt8365_apu_drv = { |
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| 48 | .probe = mtk_clk_simple_probe, |
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| 49 | .remove_new = mtk_clk_simple_remove, |
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| 50 | .driver = { |
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| 51 | .name = "clk-mt8365-apu" , |
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| 52 | .of_match_table = of_match_clk_mt8365_apu, |
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| 53 | }, |
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| 54 | }; |
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| 55 | module_platform_driver(clk_mt8365_apu_drv); |
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| 56 | MODULE_LICENSE("GPL" ); |
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| 57 | |
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