1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 * Copyright (C) 2023 Collabora Ltd.
5 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6 */
7
8#include <dt-bindings/clock/mediatek,mt8365-clk.h>
9#include <linux/clk.h>
10#include <linux/clk-provider.h>
11#include <linux/delay.h>
12#include <linux/mfd/syscon.h>
13#include <linux/mod_devicetable.h>
14#include <linux/platform_device.h>
15#include <linux/slab.h>
16
17#include "clk-gate.h"
18#include "clk-mtk.h"
19#include "clk-mux.h"
20
21static DEFINE_SPINLOCK(mt8365_clk_lock);
22
23static const struct mtk_fixed_clk top_fixed_clks[] = {
24 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
25 FIXED_CLK(CLK_TOP_I2S0_BCK, "i2s0_bck", NULL, 26000000),
26 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSICK, "dsi0_lntc_dsick", "clk26m",
27 75000000),
28 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", "clk26m", 75000000),
29 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx_dig_cts", "clk26m",
30 52500000),
31};
32
33static const struct mtk_fixed_factor top_divs[] = {
34 FACTOR(CLK_TOP_SYS_26M_D2, "sys_26m_d2", "clk26m", 1, 2),
35 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
36 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
37 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
38 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
39 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "mainpll", 1, 32),
40 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
41 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "mainpll", 1, 6),
42 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
43 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
44 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
45 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
46 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
47 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
48 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
49 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
50 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ_en", 1, 2),
51 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
52 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
53 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
54 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
55 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
56 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
57 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
58 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll", 1, 96),
59 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
60 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
61 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
62 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
63 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
64 FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
65 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
66 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
67 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
68 FACTOR(CLK_TOP_LVDSPLL_D16, "lvdspll_d16", "lvdspll", 1, 16),
69 FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "usb20_en", 1, 13),
70 FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4),
71 FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8),
72 FACTOR(CLK_TOP_USB20_192M_D16, "usb20_192m_d16", "usb20_192m_ck",
73 1, 16),
74 FACTOR(CLK_TOP_USB20_192M_D32, "usb20_192m_d32", "usb20_192m_ck",
75 1, 32),
76 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
77 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
78 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
79 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8),
80 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
81 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
82 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4),
83 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8),
84 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
85 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
86 FACTOR(CLK_TOP_DSPPLL, "dsppll_ck", "dsppll", 1, 1),
87 FACTOR(CLK_TOP_DSPPLL_D2, "dsppll_d2", "dsppll", 1, 2),
88 FACTOR(CLK_TOP_DSPPLL_D4, "dsppll_d4", "dsppll", 1, 4),
89 FACTOR(CLK_TOP_DSPPLL_D8, "dsppll_d8", "dsppll", 1, 8),
90 FACTOR(CLK_TOP_APUPLL, "apupll_ck", "apupll", 1, 1),
91 FACTOR(CLK_TOP_CLK26M_D52, "clk26m_d52", "clk26m", 1, 52),
92};
93
94static const char * const axi_parents[] = {
95 "clk26m",
96 "syspll_d7",
97 "syspll1_d4",
98 "syspll3_d2"
99};
100
101static const char * const mem_parents[] = {
102 "clk26m",
103 "mmpll_ck",
104 "syspll_d3",
105 "syspll1_d2"
106};
107
108static const char * const mm_parents[] = {
109 "clk26m",
110 "mmpll_ck",
111 "syspll1_d2",
112 "syspll_d5",
113 "syspll1_d4",
114 "univpll_d5",
115 "univpll1_d2",
116 "mmpll_d2"
117};
118
119static const char * const scp_parents[] = {
120 "clk26m",
121 "syspll4_d2",
122 "univpll2_d2",
123 "syspll1_d2",
124 "univpll1_d2",
125 "syspll_d3",
126 "univpll_d3"
127};
128
129static const char * const mfg_parents[] = {
130 "clk26m",
131 "mfgpll_ck",
132 "syspll_d3",
133 "univpll_d3"
134};
135
136static const char * const atb_parents[] = {
137 "clk26m",
138 "syspll1_d4",
139 "syspll1_d2"
140};
141
142static const char * const camtg_parents[] = {
143 "clk26m",
144 "usb20_192m_d8",
145 "univpll2_d8",
146 "usb20_192m_d4",
147 "univpll2_d32",
148 "usb20_192m_d16",
149 "usb20_192m_d32"
150};
151
152static const char * const uart_parents[] = {
153 "clk26m",
154 "univpll2_d8"
155};
156
157static const char * const spi_parents[] = {
158 "clk26m",
159 "univpll2_d2",
160 "univpll2_d4",
161 "univpll2_d8"
162};
163
164static const char * const msdc50_0_hc_parents[] = {
165 "clk26m",
166 "syspll1_d2",
167 "univpll1_d4",
168 "syspll2_d2"
169};
170
171static const char * const msdc50_0_parents[] = {
172 "clk26m",
173 "msdcpll_ck",
174 "univpll1_d2",
175 "syspll1_d2",
176 "univpll_d5",
177 "syspll2_d2",
178 "univpll1_d4",
179 "syspll4_d2"
180};
181
182static const char * const msdc50_2_parents[] = {
183 "clk26m",
184 "msdcpll_ck",
185 "univpll_d3",
186 "univpll1_d2",
187 "syspll1_d2",
188 "univpll2_d2",
189 "syspll2_d2",
190 "univpll1_d4"
191};
192
193static const char * const msdc30_1_parents[] = {
194 "clk26m",
195 "msdcpll_d2",
196 "univpll2_d2",
197 "syspll2_d2",
198 "univpll1_d4",
199 "syspll1_d4",
200 "syspll2_d4",
201 "univpll2_d8"
202};
203
204static const char * const audio_parents[] = {
205 "clk26m",
206 "syspll3_d4",
207 "syspll4_d4",
208 "syspll1_d16"
209};
210
211static const char * const aud_intbus_parents[] = {
212 "clk26m",
213 "syspll1_d4",
214 "syspll4_d2"
215};
216
217static const char * const aud_1_parents[] = {
218 "clk26m",
219 "apll1_ck"
220};
221
222static const char * const aud_2_parents[] = {
223 "clk26m",
224 "apll2_ck"
225};
226
227static const char * const aud_engen1_parents[] = {
228 "clk26m",
229 "apll1_d2",
230 "apll1_d4",
231 "apll1_d8"
232};
233
234static const char * const aud_engen2_parents[] = {
235 "clk26m",
236 "apll2_d2",
237 "apll2_d4",
238 "apll2_d8"
239};
240
241static const char * const aud_spdif_parents[] = {
242 "clk26m",
243 "univpll_d2"
244};
245
246static const char * const disp_pwm_parents[] = {
247 "clk26m",
248 "univpll2_d4"
249};
250
251static const char * const dxcc_parents[] = {
252 "clk26m",
253 "syspll1_d2",
254 "syspll1_d4",
255 "syspll1_d8"
256};
257
258static const char * const ssusb_sys_parents[] = {
259 "clk26m",
260 "univpll3_d4",
261 "univpll2_d4",
262 "univpll3_d2"
263};
264
265static const char * const spm_parents[] = {
266 "clk26m",
267 "syspll1_d8"
268};
269
270static const char * const i2c_parents[] = {
271 "clk26m",
272 "univpll3_d4",
273 "univpll3_d2",
274 "syspll1_d8",
275 "syspll2_d8"
276};
277
278static const char * const pwm_parents[] = {
279 "clk26m",
280 "univpll3_d4",
281 "syspll1_d8"
282};
283
284static const char * const senif_parents[] = {
285 "clk26m",
286 "univpll1_d4",
287 "univpll1_d2",
288 "univpll2_d2"
289};
290
291static const char * const aes_fde_parents[] = {
292 "clk26m",
293 "msdcpll_ck",
294 "univpll_d3",
295 "univpll2_d2",
296 "univpll1_d2",
297 "syspll1_d2"
298};
299
300static const char * const dpi0_parents[] = {
301 "clk26m",
302 "lvdspll_d2",
303 "lvdspll_d4",
304 "lvdspll_d8",
305 "lvdspll_d16"
306};
307
308static const char * const dsp_parents[] = {
309 "clk26m",
310 "sys_26m_d2",
311 "dsppll_ck",
312 "dsppll_d2",
313 "dsppll_d4",
314 "dsppll_d8"
315};
316
317static const char * const nfi2x_parents[] = {
318 "clk26m",
319 "syspll2_d2",
320 "syspll_d7",
321 "syspll_d3",
322 "syspll2_d4",
323 "msdcpll_d2",
324 "univpll1_d2",
325 "univpll_d5"
326};
327
328static const char * const nfiecc_parents[] = {
329 "clk26m",
330 "syspll4_d2",
331 "univpll2_d4",
332 "syspll_d7",
333 "univpll1_d2",
334 "syspll1_d2",
335 "univpll2_d2",
336 "syspll_d5"
337};
338
339static const char * const ecc_parents[] = {
340 "clk26m",
341 "univpll2_d2",
342 "univpll1_d2",
343 "univpll_d3",
344 "syspll_d2"
345};
346
347static const char * const eth_parents[] = {
348 "clk26m",
349 "univpll2_d8",
350 "syspll4_d4",
351 "syspll1_d8",
352 "syspll4_d2"
353};
354
355static const char * const gcpu_parents[] = {
356 "clk26m",
357 "univpll_d3",
358 "univpll2_d2",
359 "syspll_d3",
360 "syspll2_d2"
361};
362
363static const char * const gcpu_cpm_parents[] = {
364 "clk26m",
365 "univpll2_d2",
366 "syspll2_d2"
367};
368
369static const char * const apu_parents[] = {
370 "clk26m",
371 "univpll_d2",
372 "apupll_ck",
373 "mmpll_ck",
374 "syspll_d3",
375 "univpll1_d2",
376 "syspll1_d2",
377 "syspll1_d4"
378};
379
380static const char * const mbist_diag_parents[] = {
381 "clk26m",
382 "syspll4_d4",
383 "univpll2_d8"
384};
385
386static const char * const apll_i2s_parents[] = {
387 "aud_1_sel",
388 "aud_2_sel"
389};
390
391static struct mtk_composite top_misc_muxes[] = {
392 /* CLK_CFG_11 */
393 MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents,
394 0x0ec, 0, 2, 7),
395 /* Audio MUX */
396 MUX(CLK_TOP_APLL_I2S0_SEL, "apll_i2s0_sel", apll_i2s_parents, 0x0320, 11, 1),
397 MUX(CLK_TOP_APLL_I2S1_SEL, "apll_i2s1_sel", apll_i2s_parents, 0x0320, 12, 1),
398 MUX(CLK_TOP_APLL_I2S2_SEL, "apll_i2s2_sel", apll_i2s_parents, 0x0320, 13, 1),
399 MUX(CLK_TOP_APLL_I2S3_SEL, "apll_i2s3_sel", apll_i2s_parents, 0x0320, 14, 1),
400 MUX(CLK_TOP_APLL_TDMOUT_SEL, "apll_tdmout_sel", apll_i2s_parents, 0x0320, 15, 1),
401 MUX(CLK_TOP_APLL_TDMIN_SEL, "apll_tdmin_sel", apll_i2s_parents, 0x0320, 16, 1),
402 MUX(CLK_TOP_APLL_SPDIF_SEL, "apll_spdif_sel", apll_i2s_parents, 0x0320, 17, 1),
403};
404
405#define CLK_CFG_UPDATE 0x004
406#define CLK_CFG_UPDATE1 0x008
407
408static const struct mtk_mux top_muxes[] = {
409 /* CLK_CFG_0 */
410 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
411 0x040, 0x044, 0x048, 0, 2, 7, CLK_CFG_UPDATE,
412 0, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
413 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,
414 0x044, 0x048, 8, 2, 15, CLK_CFG_UPDATE, 1),
415 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
416 0x048, 16, 3, 23, CLK_CFG_UPDATE, 2),
417 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040,
418 0x044, 0x048, 24, 3, 31, CLK_CFG_UPDATE, 3),
419 /* CLK_CFG_1 */
420 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050,
421 0x054, 0x058, 0, 2, 7, CLK_CFG_UPDATE, 4),
422 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x050,
423 0x054, 0x058, 8, 2, 15, CLK_CFG_UPDATE, 5),
424 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
425 0x050, 0x054, 0x058, 16, 3, 23, CLK_CFG_UPDATE, 6),
426 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
427 0x050, 0x054, 0x058, 24, 3, 31, CLK_CFG_UPDATE, 7),
428 /* CLK_CFG_2 */
429 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
430 0x064, 0x068, 0, 1, 7, CLK_CFG_UPDATE, 8),
431 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060,
432 0x064, 0x068, 8, 2, 15, CLK_CFG_UPDATE, 9),
433 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, "msdc50_0_hc_sel",
434 msdc50_0_hc_parents, 0x060, 0x064, 0x068, 16, 2,
435 23, CLK_CFG_UPDATE, 10, 0),
436 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, "msdc2_2_hc_sel",
437 msdc50_0_hc_parents, 0x060, 0x064, 0x068, 24, 2,
438 31, CLK_CFG_UPDATE, 11, 0),
439 /* CLK_CFG_3 */
440 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
441 msdc50_0_parents, 0x070, 0x074, 0x078, 0, 3, 7,
442 CLK_CFG_UPDATE, 12, 0),
443 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, "msdc50_2_sel",
444 msdc50_2_parents, 0x070, 0x074, 0x078, 8, 3, 15,
445 CLK_CFG_UPDATE, 13, 0),
446 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
447 msdc30_1_parents, 0x070, 0x074, 0x078, 16, 3, 23,
448 CLK_CFG_UPDATE, 14, 0),
449 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
450 0x070, 0x074, 0x078, 24, 2, 31, CLK_CFG_UPDATE,
451 15),
452 /* CLK_CFG_4 */
453 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
454 aud_intbus_parents, 0x080, 0x084, 0x088, 0, 2, 7,
455 CLK_CFG_UPDATE, 16),
456 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
457 0x080, 0x084, 0x088, 8, 1, 15, CLK_CFG_UPDATE, 17),
458 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents,
459 0x080, 0x084, 0x088, 16, 1, 23, CLK_CFG_UPDATE,
460 18),
461 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
462 aud_engen1_parents, 0x080, 0x084, 0x088, 24, 2, 31,
463 CLK_CFG_UPDATE, 19),
464 /* CLK_CFG_5 */
465 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
466 aud_engen2_parents, 0x090, 0x094, 0x098, 0, 2, 7,
467 CLK_CFG_UPDATE, 20),
468 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SPDIF_SEL, "aud_spdif_sel",
469 aud_spdif_parents, 0x090, 0x094, 0x098, 8, 1, 15,
470 CLK_CFG_UPDATE, 21),
471 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
472 disp_pwm_parents, 0x090, 0x094, 0x098, 16, 2, 23,
473 CLK_CFG_UPDATE, 22),
474 /* CLK_CFG_6 */
475 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
476 0x0a0, 0x0a4, 0x0a8, 0, 2, 7, CLK_CFG_UPDATE,
477 24, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
478 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_SYS_SEL, "ssusb_sys_sel",
479 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 8, 2, 15,
480 CLK_CFG_UPDATE, 25),
481 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL, "ssusb_xhci_sel",
482 ssusb_sys_parents, 0x0a0, 0x0a4, 0x0a8, 16, 2, 23,
483 CLK_CFG_UPDATE, 26),
484 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, "spm_sel", spm_parents,
485 0x0a0, 0x0a4, 0x0a8, 24, 1, 31, CLK_CFG_UPDATE,
486 27, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
487 /* CLK_CFG_7 */
488 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x0b0,
489 0x0b4, 0x0b8, 0, 3, 7, CLK_CFG_UPDATE, 28),
490 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0b0,
491 0x0b4, 0x0b8, 8, 2, 15, CLK_CFG_UPDATE, 29),
492 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENIF_SEL, "senif_sel", senif_parents,
493 0x0b0, 0x0b4, 0x0b8, 16, 2, 23, CLK_CFG_UPDATE,
494 30),
495 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel",
496 aes_fde_parents, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31,
497 CLK_CFG_UPDATE, 31),
498 /* CLK_CFG_8 */
499 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", senif_parents,
500 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, CLK_CFG_UPDATE1, 0),
501 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0c0,
502 0x0c4, 0x0c8, 8, 3, 15, CLK_CFG_UPDATE1, 1),
503 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi0_parents, 0x0c0,
504 0x0c4, 0x0c8, 16, 3, 23, CLK_CFG_UPDATE1, 2),
505 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x0c0,
506 0x0c4, 0x0c8, 24, 3, 31, CLK_CFG_UPDATE1, 3),
507 /* CLK_CFG_9 */
508 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
509 0x0d0, 0x0d4, 0x0d8, 0, 3, 7, CLK_CFG_UPDATE1, 4),
510 MUX_GATE_CLR_SET_UPD(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
511 0x0d0, 0x0d4, 0x0d8, 8, 3, 15, CLK_CFG_UPDATE1, 5),
512 MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel", ecc_parents, 0x0d0,
513 0x0d4, 0x0d8, 16, 3, 23, CLK_CFG_UPDATE1, 6),
514 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SEL, "eth_sel", eth_parents, 0x0d0,
515 0x0d4, 0x0d8, 24, 3, 31, CLK_CFG_UPDATE1, 7),
516 /* CLK_CFG_10 */
517 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0e0,
518 0x0e4, 0x0e8, 0, 3, 7, CLK_CFG_UPDATE1, 8),
519 MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_CPM_SEL, "gcpu_cpm_sel",
520 gcpu_cpm_parents, 0x0e0, 0x0e4, 0x0e8, 8, 2, 15,
521 CLK_CFG_UPDATE1, 9),
522 MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_SEL, "apu_sel", apu_parents, 0x0e0,
523 0x0e4, 0x0e8, 16, 3, 23, CLK_CFG_UPDATE1, 10),
524 MUX_GATE_CLR_SET_UPD(CLK_TOP_APU_IF_SEL, "apu_if_sel", apu_parents,
525 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, CLK_CFG_UPDATE1,
526 11),
527};
528
529static const char * const mcu_bus_parents[] = {
530 "clk26m",
531 "armpll",
532 "mainpll",
533 "univpll_d2"
534};
535
536static struct mtk_composite mcu_muxes[] = {
537 /* bus_pll_divider_cfg */
538 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
539 9, 2, -1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
540};
541
542#define DIV_ADJ_F(_id, _name, _parent, _reg, _shift, _width, _flags) { \
543 .id = _id, \
544 .name = _name, \
545 .parent_name = _parent, \
546 .div_reg = _reg, \
547 .div_shift = _shift, \
548 .div_width = _width, \
549 .clk_divider_flags = _flags, \
550}
551
552static const struct mtk_clk_divider top_adj_divs[] = {
553 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "apll_i2s0_sel",
554 0x324, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
555 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "apll_i2s1_sel",
556 0x324, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
557 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "apll_i2s2_sel",
558 0x324, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
559 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "apll_i2s3_sel",
560 0x324, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
561 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "apll_tdmout_sel",
562 0x328, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
563 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll_tdmout_sel",
564 0x328, 8, 8, CLK_DIVIDER_ROUND_CLOSEST),
565 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "apll_tdmin_sel",
566 0x328, 16, 8, CLK_DIVIDER_ROUND_CLOSEST),
567 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll_tdmin_sel",
568 0x328, 24, 8, CLK_DIVIDER_ROUND_CLOSEST),
569 DIV_ADJ_F(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "apll_spdif_sel",
570 0x32c, 0, 8, CLK_DIVIDER_ROUND_CLOSEST),
571};
572
573static const struct mtk_gate_regs top0_cg_regs = {
574 .set_ofs = 0,
575 .clr_ofs = 0,
576 .sta_ofs = 0,
577};
578
579static const struct mtk_gate_regs top1_cg_regs = {
580 .set_ofs = 0x104,
581 .clr_ofs = 0x104,
582 .sta_ofs = 0x104,
583};
584
585static const struct mtk_gate_regs top2_cg_regs = {
586 .set_ofs = 0x320,
587 .clr_ofs = 0x320,
588 .sta_ofs = 0x320,
589};
590
591#define GATE_TOP0(_id, _name, _parent, _shift) \
592 GATE_MTK(_id, _name, _parent, &top0_cg_regs, \
593 _shift, &mtk_clk_gate_ops_no_setclr)
594
595#define GATE_TOP1(_id, _name, _parent, _shift) \
596 GATE_MTK(_id, _name, _parent, &top1_cg_regs, \
597 _shift, &mtk_clk_gate_ops_no_setclr_inv)
598
599#define GATE_TOP2(_id, _name, _parent, _shift) \
600 GATE_MTK(_id, _name, _parent, &top2_cg_regs, \
601 _shift, &mtk_clk_gate_ops_no_setclr_inv)
602
603static const struct mtk_gate top_clk_gates[] = {
604 GATE_TOP0(CLK_TOP_CONN_32K, "conn_32k", "clk32k", 10),
605 GATE_TOP0(CLK_TOP_CONN_26M, "conn_26m", "clk26m", 11),
606 GATE_TOP0(CLK_TOP_DSP_32K, "dsp_32k", "clk32k", 16),
607 GATE_TOP0(CLK_TOP_DSP_26M, "dsp_26m", "clk26m", 17),
608 GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_192m_d4", 8),
609 GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "usb20_192m_d4", 9),
610 GATE_TOP1(CLK_TOP_LVDSTX_CLKDIG_EN, "lvdstx_dig_en", "lvdstx_dig_cts", 20),
611 GATE_TOP1(CLK_TOP_VPLL_DPIX_EN, "vpll_dpix_en", "vpll_dpix", 21),
612 GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, "ssusb_top_ck_en", NULL, 22),
613 GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, "ssusb_phy_ck_en", NULL, 23),
614 GATE_TOP2(CLK_TOP_AUD_I2S0_M, "aud_i2s0_m_ck", "apll12_ck_div0", 0),
615 GATE_TOP2(CLK_TOP_AUD_I2S1_M, "aud_i2s1_m_ck", "apll12_ck_div1", 1),
616 GATE_TOP2(CLK_TOP_AUD_I2S2_M, "aud_i2s2_m_ck", "apll12_ck_div2", 2),
617 GATE_TOP2(CLK_TOP_AUD_I2S3_M, "aud_i2s3_m_ck", "apll12_ck_div3", 3),
618 GATE_TOP2(CLK_TOP_AUD_TDMOUT_M, "aud_tdmout_m_ck", "apll12_ck_div4", 4),
619 GATE_TOP2(CLK_TOP_AUD_TDMOUT_B, "aud_tdmout_b_ck", "apll12_ck_div4b", 5),
620 GATE_TOP2(CLK_TOP_AUD_TDMIN_M, "aud_tdmin_m_ck", "apll12_ck_div5", 6),
621 GATE_TOP2(CLK_TOP_AUD_TDMIN_B, "aud_tdmin_b_ck", "apll12_ck_div5b", 7),
622 GATE_TOP2(CLK_TOP_AUD_SPDIF_M, "aud_spdif_m_ck", "apll12_ck_div6", 8),
623};
624
625static const struct mtk_gate_regs ifr2_cg_regs = {
626 .set_ofs = 0x80,
627 .clr_ofs = 0x84,
628 .sta_ofs = 0x90,
629};
630
631static const struct mtk_gate_regs ifr3_cg_regs = {
632 .set_ofs = 0x88,
633 .clr_ofs = 0x8c,
634 .sta_ofs = 0x94,
635};
636
637static const struct mtk_gate_regs ifr4_cg_regs = {
638 .set_ofs = 0xa4,
639 .clr_ofs = 0xa8,
640 .sta_ofs = 0xac,
641};
642
643static const struct mtk_gate_regs ifr5_cg_regs = {
644 .set_ofs = 0xc0,
645 .clr_ofs = 0xc4,
646 .sta_ofs = 0xc8,
647};
648
649static const struct mtk_gate_regs ifr6_cg_regs = {
650 .set_ofs = 0xd0,
651 .clr_ofs = 0xd4,
652 .sta_ofs = 0xd8,
653};
654
655#define GATE_IFRX(_id, _name, _parent, _shift, _regs) \
656 GATE_MTK(_id, _name, _parent, _regs, _shift, \
657 &mtk_clk_gate_ops_setclr)
658
659#define GATE_IFR2(_id, _name, _parent, _shift) \
660 GATE_IFRX(_id, _name, _parent, _shift, &ifr2_cg_regs)
661
662#define GATE_IFR3(_id, _name, _parent, _shift) \
663 GATE_IFRX(_id, _name, _parent, _shift, &ifr3_cg_regs)
664
665#define GATE_IFR4(_id, _name, _parent, _shift) \
666 GATE_IFRX(_id, _name, _parent, _shift, &ifr4_cg_regs)
667
668#define GATE_IFR5(_id, _name, _parent, _shift) \
669 GATE_IFRX(_id, _name, _parent, _shift, &ifr5_cg_regs)
670
671#define GATE_IFR6(_id, _name, _parent, _shift) \
672 GATE_IFRX(_id, _name, _parent, _shift, &ifr6_cg_regs)
673
674static const struct mtk_gate ifr_clks[] = {
675 /* IFR2 */
676 GATE_IFR2(CLK_IFR_PMIC_TMR, "ifr_pmic_tmr", "clk26m", 0),
677 GATE_IFR2(CLK_IFR_PMIC_AP, "ifr_pmic_ap", "clk26m", 1),
678 GATE_IFR2(CLK_IFR_PMIC_MD, "ifr_pmic_md", "clk26m", 2),
679 GATE_IFR2(CLK_IFR_PMIC_CONN, "ifr_pmic_conn", "clk26m", 3),
680 GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_sel", 8),
681 GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_sel", 9),
682 GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_sel", 10),
683 GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_sel", 15),
684 GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "pwm_sel", 16),
685 GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "pwm_sel", 17),
686 GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "pwm_sel", 18),
687 GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "pwm_sel", 19),
688 GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "pwm_sel", 20),
689 GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "pwm_sel", 21),
690 GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "uart_sel", 22),
691 GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "uart_sel", 23),
692 GATE_IFR2(CLK_IFR_UART2, "ifr_uart2", "uart_sel", 24),
693 GATE_IFR2(CLK_IFR_DSP_UART, "ifr_dsp_uart", "uart_sel", 26),
694 GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "clk26m", 27),
695 GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_cq_dma_fpc", "axi_sel", 28),
696 GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_sel", 31),
697 /* IFR3 */
698 GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_sel", 1),
699 GATE_IFR3(CLK_IFR_MSDC0_HCLK, "ifr_msdc0", "msdc50_0_hc_sel", 2),
700 GATE_IFR3(CLK_IFR_MSDC2_HCLK, "ifr_msdc2", "msdc2_2_hc_sel", 3),
701 GATE_IFR3(CLK_IFR_MSDC1_HCLK, "ifr_msdc1", "axi_sel", 4),
702 GATE_IFR3(CLK_IFR_DVFSRC, "ifr_dvfsrc", "clk26m", 7),
703 GATE_IFR3(CLK_IFR_GCPU, "ifr_gcpu", "axi_sel", 8),
704 GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_sel", 9),
705 GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "clk26m", 10),
706 GATE_IFR3(CLK_IFR_CPUM, "ifr_cpum", "clk26m", 11),
707 GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "clk26m", 14),
708 GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_sel", 18),
709 GATE_IFR3(CLK_IFR_DEBUGSYS, "ifr_debugsys", "axi_sel", 24),
710 GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_sel", 25),
711 /* IFR4 */
712 GATE_IFR4(CLK_IFR_PWM_FBCLK6, "ifr_pwm_fbclk6", "pwm_sel", 0),
713 GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "disp_pwm_sel", 2),
714 GATE_IFR4(CLK_IFR_AUD_26M_BK, "ifr_aud_26m_bk", "clk26m", 4),
715 GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_sel", 27),
716 /* IFR5 */
717 GATE_IFR5(CLK_IFR_MSDC0_SF, "ifr_msdc0_sf", "msdc50_0_sel", 0),
718 GATE_IFR5(CLK_IFR_MSDC1_SF, "ifr_msdc1_sf", "msdc50_0_sel", 1),
719 GATE_IFR5(CLK_IFR_MSDC2_SF, "ifr_msdc2_sf", "msdc50_0_sel", 2),
720 GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_sel", 7),
721 GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_sel", 8),
722 GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_src", "msdc50_0_sel", 9),
723 GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_src", "msdc30_1_sel", 10),
724 GATE_IFR5(CLK_IFR_MSDC2_SRC, "ifr_msdc2_src", "msdc50_2_sel", 11),
725 GATE_IFR5(CLK_IFR_PWRAP_TMR, "ifr_pwrap_tmr", "clk26m", 12),
726 GATE_IFR5(CLK_IFR_PWRAP_SPI, "ifr_pwrap_spi", "clk26m", 13),
727 GATE_IFR5(CLK_IFR_PWRAP_SYS, "ifr_pwrap_sys", "clk26m", 14),
728 GATE_MTK_FLAGS(CLK_IFR_MCU_PM_BK, "ifr_mcu_pm_bk", NULL, &ifr5_cg_regs,
729 17, &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED),
730 GATE_IFR5(CLK_IFR_IRRX_26M, "ifr_irrx_26m", "clk26m", 22),
731 GATE_IFR5(CLK_IFR_IRRX_32K, "ifr_irrx_32k", "clk32k", 23),
732 GATE_IFR5(CLK_IFR_I2C0_AXI, "ifr_i2c0_axi", "i2c_sel", 24),
733 GATE_IFR5(CLK_IFR_I2C1_AXI, "ifr_i2c1_axi", "i2c_sel", 25),
734 GATE_IFR5(CLK_IFR_I2C2_AXI, "ifr_i2c2_axi", "i2c_sel", 26),
735 GATE_IFR5(CLK_IFR_I2C3_AXI, "ifr_i2c3_axi", "i2c_sel", 27),
736 GATE_IFR5(CLK_IFR_NIC_AXI, "ifr_nic_axi", "axi_sel", 28),
737 GATE_IFR5(CLK_IFR_NIC_SLV_AXI, "ifr_nic_slv_axi", "axi_sel", 29),
738 GATE_IFR5(CLK_IFR_APU_AXI, "ifr_apu_axi", "axi_sel", 30),
739 /* IFR6 */
740 GATE_IFR6(CLK_IFR_NFIECC, "ifr_nfiecc", "nfiecc_sel", 0),
741 GATE_IFR6(CLK_IFR_NFI1X_BK, "ifr_nfi1x_bk", "nfi2x_sel", 1),
742 GATE_IFR6(CLK_IFR_NFIECC_BK, "ifr_nfiecc_bk", "nfi2x_sel", 2),
743 GATE_IFR6(CLK_IFR_NFI_BK, "ifr_nfi_bk", "axi_sel", 3),
744 GATE_IFR6(CLK_IFR_MSDC2_AP_BK, "ifr_msdc2_ap_bk", "axi_sel", 4),
745 GATE_IFR6(CLK_IFR_MSDC2_MD_BK, "ifr_msdc2_md_bk", "axi_sel", 5),
746 GATE_IFR6(CLK_IFR_MSDC2_BK, "ifr_msdc2_bk", "axi_sel", 6),
747 GATE_IFR6(CLK_IFR_SUSB_133_BK, "ifr_susb_133_bk", "axi_sel", 7),
748 GATE_IFR6(CLK_IFR_SUSB_66_BK, "ifr_susb_66_bk", "axi_sel", 8),
749 GATE_IFR6(CLK_IFR_SSUSB_SYS, "ifr_ssusb_sys", "ssusb_sys_sel", 9),
750 GATE_IFR6(CLK_IFR_SSUSB_REF, "ifr_ssusb_ref", "ssusb_sys_sel", 10),
751 GATE_IFR6(CLK_IFR_SSUSB_XHCI, "ifr_ssusb_xhci", "ssusb_xhci_sel", 11),
752};
753
754static const struct mtk_gate_regs peri_cg_regs = {
755 .set_ofs = 0x20c,
756 .clr_ofs = 0x20c,
757 .sta_ofs = 0x20c,
758};
759
760static const struct mtk_gate peri_clks[] = {
761 GATE_MTK(CLK_PERIAXI, "periaxi", "axi_sel", &peri_cg_regs, 31,
762 &mtk_clk_gate_ops_no_setclr),
763};
764
765static const struct mtk_clk_desc topck_desc = {
766 .clks = top_clk_gates,
767 .num_clks = ARRAY_SIZE(top_clk_gates),
768 .fixed_clks = top_fixed_clks,
769 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
770 .factor_clks = top_divs,
771 .num_factor_clks = ARRAY_SIZE(top_divs),
772 .mux_clks = top_muxes,
773 .num_mux_clks = ARRAY_SIZE(top_muxes),
774 .composite_clks = top_misc_muxes,
775 .num_composite_clks = ARRAY_SIZE(top_misc_muxes),
776 .divider_clks = top_adj_divs,
777 .num_divider_clks = ARRAY_SIZE(top_adj_divs),
778 .clk_lock = &mt8365_clk_lock,
779};
780
781static const struct mtk_clk_desc infra_desc = {
782 .clks = ifr_clks,
783 .num_clks = ARRAY_SIZE(ifr_clks),
784};
785
786static const struct mtk_clk_desc peri_desc = {
787 .clks = peri_clks,
788 .num_clks = ARRAY_SIZE(peri_clks),
789};
790
791static const struct mtk_clk_desc mcu_desc = {
792 .composite_clks = mcu_muxes,
793 .num_composite_clks = ARRAY_SIZE(mcu_muxes),
794 .clk_lock = &mt8365_clk_lock,
795};
796
797static const struct of_device_id of_match_clk_mt8365[] = {
798 { .compatible = "mediatek,mt8365-topckgen", .data = &topck_desc },
799 { .compatible = "mediatek,mt8365-infracfg", .data = &infra_desc },
800 { .compatible = "mediatek,mt8365-pericfg", .data = &peri_desc },
801 { .compatible = "mediatek,mt8365-mcucfg", .data = &mcu_desc },
802 { /* sentinel */ }
803};
804MODULE_DEVICE_TABLE(of, of_match_clk_mt8365);
805
806static struct platform_driver clk_mt8365_drv = {
807 .driver = {
808 .name = "clk-mt8365",
809 .of_match_table = of_match_clk_mt8365,
810 },
811 .probe = mtk_clk_simple_probe,
812 .remove = mtk_clk_simple_remove,
813};
814module_platform_driver(clk_mt8365_drv);
815
816MODULE_DESCRIPTION("MediaTek MT8365 main clocks driver");
817MODULE_LICENSE("GPL");
818

source code of linux/drivers/clk/mediatek/clk-mt8365.c