1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: James Liao <jamesjj.liao@mediatek.com>
5 * Fabien Parent <fparent@baylibre.com>
6 * Copyright (c) 2023 Collabora Ltd.
7 */
8
9#include <linux/delay.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/slab.h>
13#include <linux/mfd/syscon.h>
14#include <linux/platform_device.h>
15
16#include "clk-gate.h"
17#include "clk-mtk.h"
18
19#include <dt-bindings/clock/mt8516-clk.h>
20
21static DEFINE_SPINLOCK(mt8516_clk_lock);
22
23static const struct mtk_fixed_clk fixed_clks[] __initconst = {
24 FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
25 FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
26 FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
27};
28
29static const struct mtk_fixed_factor top_divs[] __initconst = {
30 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
31 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
32 FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
33 FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
34 FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
35 FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
36 FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
37 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
38 FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
39 FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
40 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
41 FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
42 FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
43 FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
44 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
45 FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
46 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
47 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
48 FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
49 FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
50 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
51 FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
52 FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
53 FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
54 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
55 FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
56 FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
57 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
58 FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
59 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
60 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
61 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
62 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
63 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
64 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
65 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
66 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
67 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
68 FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
69 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
70 FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
71 FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
72 FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
73};
74
75static const char * const uart0_parents[] __initconst = {
76 "clk26m_ck",
77 "univpll_d24"
78};
79
80static const char * const ahb_infra_parents[] __initconst = {
81 "clk_null",
82 "clk26m_ck",
83 "mainpll_d11",
84 "clk_null",
85 "mainpll_d12",
86 "clk_null",
87 "clk_null",
88 "clk_null",
89 "clk_null",
90 "clk_null",
91 "clk_null",
92 "clk_null",
93 "mainpll_d10"
94};
95
96static const char * const msdc0_parents[] __initconst = {
97 "clk26m_ck",
98 "univpll_d6",
99 "mainpll_d8",
100 "univpll_d8",
101 "mainpll_d16",
102 "mmpll_200m",
103 "mainpll_d12",
104 "mmpll_d2"
105};
106
107static const char * const uart1_parents[] __initconst = {
108 "clk26m_ck",
109 "univpll_d24"
110};
111
112static const char * const msdc1_parents[] __initconst = {
113 "clk26m_ck",
114 "univpll_d6",
115 "mainpll_d8",
116 "univpll_d8",
117 "mainpll_d16",
118 "mmpll_200m",
119 "mainpll_d12",
120 "mmpll_d2"
121};
122
123static const char * const pmicspi_parents[] __initconst = {
124 "univpll_d20",
125 "usb_phy48m_ck",
126 "univpll_d16",
127 "clk26m_ck"
128};
129
130static const char * const qaxi_aud26m_parents[] __initconst = {
131 "clk26m_ck",
132 "ahb_infra_sel"
133};
134
135static const char * const aud_intbus_parents[] __initconst = {
136 "clk_null",
137 "clk26m_ck",
138 "mainpll_d22",
139 "clk_null",
140 "mainpll_d11"
141};
142
143static const char * const nfi2x_pad_parents[] __initconst = {
144 "clk_null",
145 "clk_null",
146 "clk_null",
147 "clk_null",
148 "clk_null",
149 "clk_null",
150 "clk_null",
151 "clk_null",
152 "clk26m_ck",
153 "clk_null",
154 "clk_null",
155 "clk_null",
156 "clk_null",
157 "clk_null",
158 "clk_null",
159 "clk_null",
160 "clk_null",
161 "mainpll_d12",
162 "mainpll_d8",
163 "clk_null",
164 "mainpll_d6",
165 "clk_null",
166 "clk_null",
167 "clk_null",
168 "clk_null",
169 "clk_null",
170 "clk_null",
171 "clk_null",
172 "clk_null",
173 "clk_null",
174 "clk_null",
175 "clk_null",
176 "mainpll_d4",
177 "clk_null",
178 "clk_null",
179 "clk_null",
180 "clk_null",
181 "clk_null",
182 "clk_null",
183 "clk_null",
184 "clk_null",
185 "clk_null",
186 "clk_null",
187 "clk_null",
188 "clk_null",
189 "clk_null",
190 "clk_null",
191 "clk_null",
192 "clk_null",
193 "clk_null",
194 "clk_null",
195 "clk_null",
196 "clk_null",
197 "clk_null",
198 "clk_null",
199 "clk_null",
200 "clk_null",
201 "clk_null",
202 "clk_null",
203 "clk_null",
204 "clk_null",
205 "clk_null",
206 "clk_null",
207 "clk_null",
208 "clk_null",
209 "clk_null",
210 "clk_null",
211 "clk_null",
212 "clk_null",
213 "clk_null",
214 "clk_null",
215 "clk_null",
216 "clk_null",
217 "clk_null",
218 "clk_null",
219 "clk_null",
220 "clk_null",
221 "clk_null",
222 "clk_null",
223 "clk_null",
224 "clk_null",
225 "mainpll_d10",
226 "mainpll_d7",
227 "clk_null",
228 "mainpll_d5"
229};
230
231static const char * const nfi1x_pad_parents[] __initconst = {
232 "ahb_infra_sel",
233 "nfi1x_ck"
234};
235
236static const char * const usb_78m_parents[] __initconst = {
237 "clk_null",
238 "clk26m_ck",
239 "univpll_d16",
240 "clk_null",
241 "mainpll_d20"
242};
243
244static const char * const spinor_parents[] __initconst = {
245 "clk26m_d2",
246 "clk26m_ck",
247 "mainpll_d40",
248 "univpll_d24",
249 "univpll_d20",
250 "mainpll_d20",
251 "mainpll_d16",
252 "univpll_d12"
253};
254
255static const char * const msdc2_parents[] __initconst = {
256 "clk26m_ck",
257 "univpll_d6",
258 "mainpll_d8",
259 "univpll_d8",
260 "mainpll_d16",
261 "mmpll_200m",
262 "mainpll_d12",
263 "mmpll_d2"
264};
265
266static const char * const eth_parents[] __initconst = {
267 "clk26m_ck",
268 "mainpll_d40",
269 "univpll_d24",
270 "univpll_d20",
271 "mainpll_d20"
272};
273
274static const char * const aud1_parents[] __initconst = {
275 "clk26m_ck",
276 "apll1_ck"
277};
278
279static const char * const aud2_parents[] __initconst = {
280 "clk26m_ck",
281 "apll2_ck"
282};
283
284static const char * const aud_engen1_parents[] __initconst = {
285 "clk26m_ck",
286 "rg_apll1_d2_en",
287 "rg_apll1_d4_en",
288 "rg_apll1_d8_en"
289};
290
291static const char * const aud_engen2_parents[] __initconst = {
292 "clk26m_ck",
293 "rg_apll2_d2_en",
294 "rg_apll2_d4_en",
295 "rg_apll2_d8_en"
296};
297
298static const char * const i2c_parents[] __initconst = {
299 "clk26m_ck",
300 "univpll_d20",
301 "univpll_d16",
302 "univpll_d12"
303};
304
305static const char * const aud_i2s0_m_parents[] __initconst = {
306 "rg_aud1",
307 "rg_aud2"
308};
309
310static const char * const pwm_parents[] __initconst = {
311 "clk26m_ck",
312 "univpll_d12"
313};
314
315static const char * const spi_parents[] __initconst = {
316 "clk26m_ck",
317 "univpll_d12",
318 "univpll_d8",
319 "univpll_d6"
320};
321
322static const char * const aud_spdifin_parents[] __initconst = {
323 "clk26m_ck",
324 "univpll_d2"
325};
326
327static const char * const uart2_parents[] __initconst = {
328 "clk26m_ck",
329 "univpll_d24"
330};
331
332static const char * const bsi_parents[] __initconst = {
333 "clk26m_ck",
334 "mainpll_d10",
335 "mainpll_d12",
336 "mainpll_d20"
337};
338
339static const char * const dbg_atclk_parents[] __initconst = {
340 "clk_null",
341 "clk26m_ck",
342 "mainpll_d5",
343 "clk_null",
344 "univpll_d5"
345};
346
347static const char * const csw_nfiecc_parents[] __initconst = {
348 "clk_null",
349 "mainpll_d7",
350 "mainpll_d6",
351 "clk_null",
352 "mainpll_d5"
353};
354
355static const char * const nfiecc_parents[] __initconst = {
356 "clk_null",
357 "nfi2x_pad_sel",
358 "mainpll_d4",
359 "clk_null",
360 "csw_nfiecc_sel"
361};
362
363static struct mtk_composite top_muxes[] __initdata = {
364 /* CLK_MUX_SEL0 */
365 MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
366 0x000, 0, 1),
367 MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
368 0x000, 4, 4),
369 MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
370 0x000, 11, 3),
371 MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
372 0x000, 19, 1),
373 MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
374 0x000, 20, 3),
375 MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
376 0x000, 24, 2),
377 MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
378 0x000, 26, 1),
379 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
380 0x000, 27, 3),
381 /* CLK_MUX_SEL1 */
382 MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
383 0x004, 0, 7),
384 MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
385 0x004, 7, 1),
386 MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
387 0x004, 20, 3),
388 /* CLK_MUX_SEL8 */
389 MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
390 0x040, 0, 3),
391 MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
392 0x040, 3, 3),
393 MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
394 0x040, 6, 3),
395 MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
396 0x040, 22, 1),
397 MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
398 0x040, 23, 1),
399 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
400 0x040, 24, 2),
401 MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
402 0x040, 26, 2),
403 MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
404 0x040, 28, 2),
405 /* CLK_SEL_9 */
406 MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
407 0x044, 12, 1),
408 MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
409 0x044, 13, 1),
410 MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
411 0x044, 14, 1),
412 MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
413 0x044, 15, 1),
414 MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
415 0x044, 16, 1),
416 MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
417 0x044, 17, 1),
418 MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
419 0x044, 18, 1),
420 /* CLK_MUX_SEL13 */
421 MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
422 0x07c, 0, 1),
423 MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
424 0x07c, 1, 2),
425 MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
426 0x07c, 3, 1),
427 MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
428 0x07c, 4, 1),
429 MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
430 0x07c, 5, 2),
431 MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
432 0x07c, 7, 3),
433 MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
434 0x07c, 10, 3),
435 MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
436 0x07c, 13, 3),
437};
438
439static const char * const ifr_mux1_parents[] __initconst = {
440 "clk26m_ck",
441 "armpll",
442 "univpll",
443 "mainpll_d2"
444};
445
446static const char * const ifr_eth_25m_parents[] __initconst = {
447 "eth_d2_ck",
448 "rg_eth"
449};
450
451static const char * const ifr_i2c0_parents[] __initconst = {
452 "ahb_infra_d2",
453 "rg_i2c"
454};
455
456static const struct mtk_composite ifr_muxes[] __initconst = {
457 MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
458 2, 2),
459 MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
460 0, 1),
461 MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
462 1, 1),
463 MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
464 2, 1),
465 MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
466 3, 1),
467};
468
469#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
470 .id = _id, \
471 .name = _name, \
472 .parent_name = _parent, \
473 .div_reg = _reg, \
474 .div_shift = _shift, \
475 .div_width = _width, \
476}
477
478static const struct mtk_clk_divider top_adj_divs[] = {
479 DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
480 0x0048, 0, 8),
481 DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
482 0x0048, 8, 8),
483 DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
484 0x0048, 16, 8),
485 DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
486 0x0048, 24, 8),
487 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
488 0x004c, 0, 8),
489 DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
490 0x004c, 8, 8),
491 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
492 0x004c, 16, 8),
493 DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
494 0x004c, 24, 8),
495 DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
496 0x0078, 0, 8),
497};
498
499static const struct mtk_gate_regs top1_cg_regs = {
500 .set_ofs = 0x54,
501 .clr_ofs = 0x84,
502 .sta_ofs = 0x24,
503};
504
505static const struct mtk_gate_regs top2_cg_regs = {
506 .set_ofs = 0x6c,
507 .clr_ofs = 0x9c,
508 .sta_ofs = 0x3c,
509};
510
511static const struct mtk_gate_regs top3_cg_regs = {
512 .set_ofs = 0xa0,
513 .clr_ofs = 0xb0,
514 .sta_ofs = 0x70,
515};
516
517static const struct mtk_gate_regs top4_cg_regs = {
518 .set_ofs = 0xa4,
519 .clr_ofs = 0xb4,
520 .sta_ofs = 0x74,
521};
522
523static const struct mtk_gate_regs top5_cg_regs = {
524 .set_ofs = 0x44,
525 .clr_ofs = 0x44,
526 .sta_ofs = 0x44,
527};
528
529#define GATE_TOP1(_id, _name, _parent, _shift) \
530 GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
531
532#define GATE_TOP2(_id, _name, _parent, _shift) \
533 GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
534
535#define GATE_TOP2_I(_id, _name, _parent, _shift) \
536 GATE_MTK(_id, _name, _parent, &top2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
537
538#define GATE_TOP3(_id, _name, _parent, _shift) \
539 GATE_MTK(_id, _name, _parent, &top3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
540
541#define GATE_TOP4_I(_id, _name, _parent, _shift) \
542 GATE_MTK(_id, _name, _parent, &top4_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
543
544#define GATE_TOP5(_id, _name, _parent, _shift) \
545 GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
546
547static const struct mtk_gate top_clks[] __initconst = {
548 /* TOP1 */
549 GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
550 GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
551 GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
552 GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
553 GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
554 GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
555 GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
556 GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
557 GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
558 GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
559 GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
560 GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
561 GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
562 GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
563 GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
564 GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
565 GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
566 GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
567 GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
568 GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
569 GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
570 GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
571 GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
572 GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
573 GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
574 GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
575 GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
576 GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
577 GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
578 GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
579 /* TOP2 */
580 GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
581 GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
582 GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
583 GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
584 GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
585 GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
586 GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
587 GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
588 GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
589 GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
590 GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
591 GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
592 GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
593 GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
594 GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
595 15),
596 GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
597 GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
598 GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
599 GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
600 GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
601 GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
602 GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
603 GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
604 GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
605 GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
606 GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
607 GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
608 /* TOP3 */
609 GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
610 GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
611 GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
612 GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
613 GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
614 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
615 GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
616 GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
617 GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
618 GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
619 14),
620 GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
621 GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
622 GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
623 GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
624 /* TOP4 */
625 GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
626 GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
627 GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
628 GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
629 GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
630 GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
631 /* TOP5 */
632 GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
633 GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
634 GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
635 GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
636 GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
637 GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
638 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
639 GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
640 GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
641};
642
643static const struct mtk_clk_desc topck_desc = {
644 .clks = top_clks,
645 .num_clks = ARRAY_SIZE(top_clks),
646 .fixed_clks = fixed_clks,
647 .num_fixed_clks = ARRAY_SIZE(fixed_clks),
648 .factor_clks = top_divs,
649 .num_factor_clks = ARRAY_SIZE(top_divs),
650 .composite_clks = top_muxes,
651 .num_composite_clks = ARRAY_SIZE(top_muxes),
652 .divider_clks = top_adj_divs,
653 .num_divider_clks = ARRAY_SIZE(top_adj_divs),
654 .clk_lock = &mt8516_clk_lock,
655};
656
657static const struct mtk_clk_desc infra_desc = {
658 .composite_clks = ifr_muxes,
659 .num_composite_clks = ARRAY_SIZE(ifr_muxes),
660 .clk_lock = &mt8516_clk_lock,
661};
662
663static const struct of_device_id of_match_clk_mt8516[] = {
664 { .compatible = "mediatek,mt8516-topckgen", .data = &topck_desc },
665 { .compatible = "mediatek,mt8516-infracfg", .data = &infra_desc },
666 { /* sentinel */ }
667};
668MODULE_DEVICE_TABLE(of, of_match_clk_mt8516);
669
670static struct platform_driver clk_mt8516_drv = {
671 .probe = mtk_clk_simple_probe,
672 .remove_new = mtk_clk_simple_remove,
673 .driver = {
674 .name = "clk-mt8516",
675 .of_match_table = of_match_clk_mt8516,
676 },
677};
678module_platform_driver(clk_mt8516_drv);
679
680MODULE_DESCRIPTION("MediaTek MT8516 clocks driver");
681MODULE_LICENSE("GPL");
682

source code of linux/drivers/clk/mediatek/clk-mt8516.c