1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4	*/
5
6	#include <linux/clk-provider.h>
7	#include <linux/mod_devicetable.h>
8	#include <linux/module.h>
9	#include <linux/platform_device.h>
10	#include <linux/pm_runtime.h>
11	#include <linux/regmap.h>
12
13	#include <dt-bindings/clock/qcom,sm8550-camcc.h>
14
15	#include "clk-alpha-pll.h"
16	#include "clk-branch.h"
17	#include "clk-rcg.h"
18	#include "clk-regmap.h"
19	#include "common.h"
20	#include "gdsc.h"
21	#include "reset.h"
22
23	enum {
24	DT_IFACE,
25	DT_BI_TCXO,
26	DT_BI_TCXO_AO,
27	DT_SLEEP_CLK,
28	};
29
30	enum {
31	P_BI_TCXO,
32	P_BI_TCXO_AO,
33	P_CAM_CC_PLL0_OUT_EVEN,
34	P_CAM_CC_PLL0_OUT_MAIN,
35	P_CAM_CC_PLL0_OUT_ODD,
36	P_CAM_CC_PLL1_OUT_EVEN,
37	P_CAM_CC_PLL2_OUT_EVEN,
38	P_CAM_CC_PLL2_OUT_MAIN,
39	P_CAM_CC_PLL3_OUT_EVEN,
40	P_CAM_CC_PLL4_OUT_EVEN,
41	P_CAM_CC_PLL5_OUT_EVEN,
42	P_CAM_CC_PLL6_OUT_EVEN,
43	P_CAM_CC_PLL7_OUT_EVEN,
44	P_CAM_CC_PLL8_OUT_EVEN,
45	P_CAM_CC_PLL9_OUT_EVEN,
46	P_CAM_CC_PLL9_OUT_ODD,
47	P_CAM_CC_PLL10_OUT_EVEN,
48	P_CAM_CC_PLL11_OUT_EVEN,
49	P_CAM_CC_PLL12_OUT_EVEN,
50	P_SLEEP_CLK,
51	};
52
53	static const struct pll_vco lucid_ole_vco[] = {
54	{ 249600000, 2300000000, 0 },
55	};
56
57	static const struct pll_vco rivian_ole_vco[] = {
58	{ 777000000, 1285000000, 0 },
59	};
60
61	static const struct alpha_pll_config cam_cc_pll0_config = {
62	.l = 0x3e,
63	.alpha = 0x8000,
64	.config_ctl_val = 0x20485699,
65	.config_ctl_hi_val = 0x00182261,
66	.config_ctl_hi1_val = 0x82aa299c,
67	.test_ctl_val = 0x00000000,
68	.test_ctl_hi_val = 0x00000003,
69	.test_ctl_hi1_val = 0x00009000,
70	.test_ctl_hi2_val = 0x00000034,
71	.user_ctl_val = 0x00008400,
72	.user_ctl_hi_val = 0x00000005,
73	};
74
75	static struct clk_alpha_pll cam_cc_pll0 = {
76	.offset = 0x0,
77	.vco_table = lucid_ole_vco,
78	.num_vco = ARRAY_SIZE(lucid_ole_vco),
79	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
80	.clkr = {
81	.hw.init = &(const struct clk_init_data) {
82	.name = "cam_cc_pll0",
83	.parent_data = &(const struct clk_parent_data) {
84	.index = DT_BI_TCXO,
85	},
86	.num_parents = 1,
87	.ops = &clk_alpha_pll_lucid_evo_ops,
88	},
89	},
90	};
91
92	static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
93	{ 0x1, 2 },
94	{ }
95	};
96
97	static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
98	.offset = 0x0,
99	.post_div_shift = 10,
100	.post_div_table = post_div_table_cam_cc_pll0_out_even,
101	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
102	.width = 4,
103	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
104	.clkr.hw.init = &(const struct clk_init_data) {
105	.name = "cam_cc_pll0_out_even",
106	.parent_hws = (const struct clk_hw*[]) {
107	&cam_cc_pll0.clkr.hw,
108	},
109	.num_parents = 1,
110	.flags = CLK_SET_RATE_PARENT,
111	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
112	},
113	};
114
115	static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
116	{ 0x2, 3 },
117	{ }
118	};
119
120	static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
121	.offset = 0x0,
122	.post_div_shift = 14,
123	.post_div_table = post_div_table_cam_cc_pll0_out_odd,
124	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
125	.width = 4,
126	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
127	.clkr.hw.init = &(const struct clk_init_data) {
128	.name = "cam_cc_pll0_out_odd",
129	.parent_hws = (const struct clk_hw*[]) {
130	&cam_cc_pll0.clkr.hw,
131	},
132	.num_parents = 1,
133	.flags = CLK_SET_RATE_PARENT,
134	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
135	},
136	};
137
138	static const struct alpha_pll_config cam_cc_pll1_config = {
139	.l = 0x2f,
140	.alpha = 0x6555,
141	.config_ctl_val = 0x20485699,
142	.config_ctl_hi_val = 0x00182261,
143	.config_ctl_hi1_val = 0x82aa299c,
144	.test_ctl_val = 0x00000000,
145	.test_ctl_hi_val = 0x00000003,
146	.test_ctl_hi1_val = 0x00009000,
147	.test_ctl_hi2_val = 0x00000034,
148	.user_ctl_val = 0x00000400,
149	.user_ctl_hi_val = 0x00000005,
150	};
151
152	static struct clk_alpha_pll cam_cc_pll1 = {
153	.offset = 0x1000,
154	.vco_table = lucid_ole_vco,
155	.num_vco = ARRAY_SIZE(lucid_ole_vco),
156	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
157	.clkr = {
158	.hw.init = &(const struct clk_init_data) {
159	.name = "cam_cc_pll1",
160	.parent_data = &(const struct clk_parent_data) {
161	.index = DT_BI_TCXO,
162	},
163	.num_parents = 1,
164	.ops = &clk_alpha_pll_lucid_evo_ops,
165	},
166	},
167	};
168
169	static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
170	{ 0x1, 2 },
171	{ }
172	};
173
174	static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
175	.offset = 0x1000,
176	.post_div_shift = 10,
177	.post_div_table = post_div_table_cam_cc_pll1_out_even,
178	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
179	.width = 4,
180	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
181	.clkr.hw.init = &(const struct clk_init_data) {
182	.name = "cam_cc_pll1_out_even",
183	.parent_hws = (const struct clk_hw*[]) {
184	&cam_cc_pll1.clkr.hw,
185	},
186	.num_parents = 1,
187	.flags = CLK_SET_RATE_PARENT,
188	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
189	},
190	};
191
192	static const struct alpha_pll_config cam_cc_pll2_config = {
193	.l = 0x32,
194	.alpha = 0x0,
195	.config_ctl_val = 0x10000030,
196	.config_ctl_hi_val = 0x80890263,
197	.config_ctl_hi1_val = 0x00000217,
198	.user_ctl_val = 0x00000000,
199	.user_ctl_hi_val = 0x00100000,
200	};
201
202	static struct clk_alpha_pll cam_cc_pll2 = {
203	.offset = 0x2000,
204	.vco_table = rivian_ole_vco,
205	.num_vco = ARRAY_SIZE(rivian_ole_vco),
206	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
207	.clkr = {
208	.hw.init = &(const struct clk_init_data) {
209	.name = "cam_cc_pll2",
210	.parent_data = &(const struct clk_parent_data) {
211	.index = DT_BI_TCXO,
212	},
213	.num_parents = 1,
214	.ops = &clk_alpha_pll_rivian_evo_ops,
215	},
216	},
217	};
218
219	static const struct alpha_pll_config cam_cc_pll3_config = {
220	.l = 0x30,
221	.alpha = 0x8aaa,
222	.config_ctl_val = 0x20485699,
223	.config_ctl_hi_val = 0x00182261,
224	.config_ctl_hi1_val = 0x82aa299c,
225	.test_ctl_val = 0x00000000,
226	.test_ctl_hi_val = 0x00000003,
227	.test_ctl_hi1_val = 0x00009000,
228	.test_ctl_hi2_val = 0x00000034,
229	.user_ctl_val = 0x00000400,
230	.user_ctl_hi_val = 0x00000005,
231	};
232
233	static struct clk_alpha_pll cam_cc_pll3 = {
234	.offset = 0x3000,
235	.vco_table = lucid_ole_vco,
236	.num_vco = ARRAY_SIZE(lucid_ole_vco),
237	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
238	.clkr = {
239	.hw.init = &(const struct clk_init_data) {
240	.name = "cam_cc_pll3",
241	.parent_data = &(const struct clk_parent_data) {
242	.index = DT_BI_TCXO,
243	},
244	.num_parents = 1,
245	.ops = &clk_alpha_pll_lucid_evo_ops,
246	},
247	},
248	};
249
250	static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
251	{ 0x1, 2 },
252	{ }
253	};
254
255	static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
256	.offset = 0x3000,
257	.post_div_shift = 10,
258	.post_div_table = post_div_table_cam_cc_pll3_out_even,
259	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
260	.width = 4,
261	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
262	.clkr.hw.init = &(const struct clk_init_data) {
263	.name = "cam_cc_pll3_out_even",
264	.parent_hws = (const struct clk_hw*[]) {
265	&cam_cc_pll3.clkr.hw,
266	},
267	.num_parents = 1,
268	.flags = CLK_SET_RATE_PARENT,
269	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
270	},
271	};
272
273	static const struct alpha_pll_config cam_cc_pll4_config = {
274	.l = 0x30,
275	.alpha = 0x8aaa,
276	.config_ctl_val = 0x20485699,
277	.config_ctl_hi_val = 0x00182261,
278	.config_ctl_hi1_val = 0x82aa299c,
279	.test_ctl_val = 0x00000000,
280	.test_ctl_hi_val = 0x00000003,
281	.test_ctl_hi1_val = 0x00009000,
282	.test_ctl_hi2_val = 0x00000034,
283	.user_ctl_val = 0x00000400,
284	.user_ctl_hi_val = 0x00000005,
285	};
286
287	static struct clk_alpha_pll cam_cc_pll4 = {
288	.offset = 0x4000,
289	.vco_table = lucid_ole_vco,
290	.num_vco = ARRAY_SIZE(lucid_ole_vco),
291	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
292	.clkr = {
293	.hw.init = &(const struct clk_init_data) {
294	.name = "cam_cc_pll4",
295	.parent_data = &(const struct clk_parent_data) {
296	.index = DT_BI_TCXO,
297	},
298	.num_parents = 1,
299	.ops = &clk_alpha_pll_lucid_evo_ops,
300	},
301	},
302	};
303
304	static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
305	{ 0x1, 2 },
306	{ }
307	};
308
309	static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
310	.offset = 0x4000,
311	.post_div_shift = 10,
312	.post_div_table = post_div_table_cam_cc_pll4_out_even,
313	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
314	.width = 4,
315	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
316	.clkr.hw.init = &(const struct clk_init_data) {
317	.name = "cam_cc_pll4_out_even",
318	.parent_hws = (const struct clk_hw*[]) {
319	&cam_cc_pll4.clkr.hw,
320	},
321	.num_parents = 1,
322	.flags = CLK_SET_RATE_PARENT,
323	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
324	},
325	};
326
327	static const struct alpha_pll_config cam_cc_pll5_config = {
328	.l = 0x30,
329	.alpha = 0x8aaa,
330	.config_ctl_val = 0x20485699,
331	.config_ctl_hi_val = 0x00182261,
332	.config_ctl_hi1_val = 0x82aa299c,
333	.test_ctl_val = 0x00000000,
334	.test_ctl_hi_val = 0x00000003,
335	.test_ctl_hi1_val = 0x00009000,
336	.test_ctl_hi2_val = 0x00000034,
337	.user_ctl_val = 0x00000400,
338	.user_ctl_hi_val = 0x00000005,
339	};
340
341	static struct clk_alpha_pll cam_cc_pll5 = {
342	.offset = 0x5000,
343	.vco_table = lucid_ole_vco,
344	.num_vco = ARRAY_SIZE(lucid_ole_vco),
345	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
346	.clkr = {
347	.hw.init = &(const struct clk_init_data) {
348	.name = "cam_cc_pll5",
349	.parent_data = &(const struct clk_parent_data) {
350	.index = DT_BI_TCXO,
351	},
352	.num_parents = 1,
353	.ops = &clk_alpha_pll_lucid_evo_ops,
354	},
355	},
356	};
357
358	static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
359	{ 0x1, 2 },
360	{ }
361	};
362
363	static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
364	.offset = 0x5000,
365	.post_div_shift = 10,
366	.post_div_table = post_div_table_cam_cc_pll5_out_even,
367	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
368	.width = 4,
369	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
370	.clkr.hw.init = &(const struct clk_init_data) {
371	.name = "cam_cc_pll5_out_even",
372	.parent_hws = (const struct clk_hw*[]) {
373	&cam_cc_pll5.clkr.hw,
374	},
375	.num_parents = 1,
376	.flags = CLK_SET_RATE_PARENT,
377	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
378	},
379	};
380
381	static const struct alpha_pll_config cam_cc_pll6_config = {
382	.l = 0x30,
383	.alpha = 0x8aaa,
384	.config_ctl_val = 0x20485699,
385	.config_ctl_hi_val = 0x00182261,
386	.config_ctl_hi1_val = 0x82aa299c,
387	.test_ctl_val = 0x00000000,
388	.test_ctl_hi_val = 0x00000003,
389	.test_ctl_hi1_val = 0x00009000,
390	.test_ctl_hi2_val = 0x00000034,
391	.user_ctl_val = 0x00000400,
392	.user_ctl_hi_val = 0x00000005,
393	};
394
395	static struct clk_alpha_pll cam_cc_pll6 = {
396	.offset = 0x6000,
397	.vco_table = lucid_ole_vco,
398	.num_vco = ARRAY_SIZE(lucid_ole_vco),
399	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
400	.clkr = {
401	.hw.init = &(const struct clk_init_data) {
402	.name = "cam_cc_pll6",
403	.parent_data = &(const struct clk_parent_data) {
404	.index = DT_BI_TCXO,
405	},
406	.num_parents = 1,
407	.ops = &clk_alpha_pll_lucid_evo_ops,
408	},
409	},
410	};
411
412	static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
413	{ 0x1, 2 },
414	{ }
415	};
416
417	static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
418	.offset = 0x6000,
419	.post_div_shift = 10,
420	.post_div_table = post_div_table_cam_cc_pll6_out_even,
421	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
422	.width = 4,
423	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
424	.clkr.hw.init = &(const struct clk_init_data) {
425	.name = "cam_cc_pll6_out_even",
426	.parent_hws = (const struct clk_hw*[]) {
427	&cam_cc_pll6.clkr.hw,
428	},
429	.num_parents = 1,
430	.flags = CLK_SET_RATE_PARENT,
431	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
432	},
433	};
434
435	static const struct alpha_pll_config cam_cc_pll7_config = {
436	.l = 0x30,
437	.alpha = 0x8aaa,
438	.config_ctl_val = 0x20485699,
439	.config_ctl_hi_val = 0x00182261,
440	.config_ctl_hi1_val = 0x82aa299c,
441	.test_ctl_val = 0x00000000,
442	.test_ctl_hi_val = 0x00000003,
443	.test_ctl_hi1_val = 0x00009000,
444	.test_ctl_hi2_val = 0x00000034,
445	.user_ctl_val = 0x00000400,
446	.user_ctl_hi_val = 0x00000005,
447	};
448
449	static struct clk_alpha_pll cam_cc_pll7 = {
450	.offset = 0x7000,
451	.vco_table = lucid_ole_vco,
452	.num_vco = ARRAY_SIZE(lucid_ole_vco),
453	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
454	.clkr = {
455	.hw.init = &(const struct clk_init_data) {
456	.name = "cam_cc_pll7",
457	.parent_data = &(const struct clk_parent_data) {
458	.index = DT_BI_TCXO,
459	},
460	.num_parents = 1,
461	.ops = &clk_alpha_pll_lucid_evo_ops,
462	},
463	},
464	};
465
466	static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
467	{ 0x1, 2 },
468	{ }
469	};
470
471	static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
472	.offset = 0x7000,
473	.post_div_shift = 10,
474	.post_div_table = post_div_table_cam_cc_pll7_out_even,
475	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
476	.width = 4,
477	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
478	.clkr.hw.init = &(const struct clk_init_data) {
479	.name = "cam_cc_pll7_out_even",
480	.parent_hws = (const struct clk_hw*[]) {
481	&cam_cc_pll7.clkr.hw,
482	},
483	.num_parents = 1,
484	.flags = CLK_SET_RATE_PARENT,
485	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
486	},
487	};
488
489	static const struct alpha_pll_config cam_cc_pll8_config = {
490	.l = 0x14,
491	.alpha = 0xd555,
492	.config_ctl_val = 0x20485699,
493	.config_ctl_hi_val = 0x00182261,
494	.config_ctl_hi1_val = 0x82aa299c,
495	.test_ctl_val = 0x00000000,
496	.test_ctl_hi_val = 0x00000003,
497	.test_ctl_hi1_val = 0x00009000,
498	.test_ctl_hi2_val = 0x00000034,
499	.user_ctl_val = 0x00000400,
500	.user_ctl_hi_val = 0x00000005,
501	};
502
503	static struct clk_alpha_pll cam_cc_pll8 = {
504	.offset = 0x8000,
505	.vco_table = lucid_ole_vco,
506	.num_vco = ARRAY_SIZE(lucid_ole_vco),
507	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
508	.clkr = {
509	.hw.init = &(const struct clk_init_data) {
510	.name = "cam_cc_pll8",
511	.parent_data = &(const struct clk_parent_data) {
512	.index = DT_BI_TCXO,
513	},
514	.num_parents = 1,
515	.ops = &clk_alpha_pll_lucid_evo_ops,
516	},
517	},
518	};
519
520	static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
521	{ 0x1, 2 },
522	{ }
523	};
524
525	static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
526	.offset = 0x8000,
527	.post_div_shift = 10,
528	.post_div_table = post_div_table_cam_cc_pll8_out_even,
529	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
530	.width = 4,
531	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
532	.clkr.hw.init = &(const struct clk_init_data) {
533	.name = "cam_cc_pll8_out_even",
534	.parent_hws = (const struct clk_hw*[]) {
535	&cam_cc_pll8.clkr.hw,
536	},
537	.num_parents = 1,
538	.flags = CLK_SET_RATE_PARENT,
539	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
540	},
541	};
542
543	static const struct alpha_pll_config cam_cc_pll9_config = {
544	.l = 0x32,
545	.alpha = 0x0,
546	.config_ctl_val = 0x20485699,
547	.config_ctl_hi_val = 0x00182261,
548	.config_ctl_hi1_val = 0x82aa299c,
549	.test_ctl_val = 0x00000000,
550	.test_ctl_hi_val = 0x00000003,
551	.test_ctl_hi1_val = 0x00009000,
552	.test_ctl_hi2_val = 0x00000034,
553	.user_ctl_val = 0x00000400,
554	.user_ctl_hi_val = 0x00000005,
555	};
556
557	static struct clk_alpha_pll cam_cc_pll9 = {
558	.offset = 0x9000,
559	.vco_table = lucid_ole_vco,
560	.num_vco = ARRAY_SIZE(lucid_ole_vco),
561	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
562	.clkr = {
563	.hw.init = &(const struct clk_init_data) {
564	.name = "cam_cc_pll9",
565	.parent_data = &(const struct clk_parent_data) {
566	.index = DT_BI_TCXO,
567	},
568	.num_parents = 1,
569	.ops = &clk_alpha_pll_lucid_evo_ops,
570	},
571	},
572	};
573
574	static const struct clk_div_table post_div_table_cam_cc_pll9_out_even[] = {
575	{ 0x1, 2 },
576	{ }
577	};
578
579	static struct clk_alpha_pll_postdiv cam_cc_pll9_out_even = {
580	.offset = 0x9000,
581	.post_div_shift = 10,
582	.post_div_table = post_div_table_cam_cc_pll9_out_even,
583	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll9_out_even),
584	.width = 4,
585	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
586	.clkr.hw.init = &(const struct clk_init_data) {
587	.name = "cam_cc_pll9_out_even",
588	.parent_hws = (const struct clk_hw*[]) {
589	&cam_cc_pll9.clkr.hw,
590	},
591	.num_parents = 1,
592	.flags = CLK_SET_RATE_PARENT,
593	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
594	},
595	};
596
597	static const struct alpha_pll_config cam_cc_pll10_config = {
598	.l = 0x30,
599	.alpha = 0x8aaa,
600	.config_ctl_val = 0x20485699,
601	.config_ctl_hi_val = 0x00182261,
602	.config_ctl_hi1_val = 0x82aa299c,
603	.test_ctl_val = 0x00000000,
604	.test_ctl_hi_val = 0x00000003,
605	.test_ctl_hi1_val = 0x00009000,
606	.test_ctl_hi2_val = 0x00000034,
607	.user_ctl_val = 0x00000400,
608	.user_ctl_hi_val = 0x00000005,
609	};
610
611	static struct clk_alpha_pll cam_cc_pll10 = {
612	.offset = 0xa000,
613	.vco_table = lucid_ole_vco,
614	.num_vco = ARRAY_SIZE(lucid_ole_vco),
615	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
616	.clkr = {
617	.hw.init = &(const struct clk_init_data) {
618	.name = "cam_cc_pll10",
619	.parent_data = &(const struct clk_parent_data) {
620	.index = DT_BI_TCXO,
621	},
622	.num_parents = 1,
623	.ops = &clk_alpha_pll_lucid_evo_ops,
624	},
625	},
626	};
627
628	static const struct clk_div_table post_div_table_cam_cc_pll10_out_even[] = {
629	{ 0x1, 2 },
630	{ }
631	};
632
633	static struct clk_alpha_pll_postdiv cam_cc_pll10_out_even = {
634	.offset = 0xa000,
635	.post_div_shift = 10,
636	.post_div_table = post_div_table_cam_cc_pll10_out_even,
637	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll10_out_even),
638	.width = 4,
639	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
640	.clkr.hw.init = &(const struct clk_init_data) {
641	.name = "cam_cc_pll10_out_even",
642	.parent_hws = (const struct clk_hw*[]) {
643	&cam_cc_pll10.clkr.hw,
644	},
645	.num_parents = 1,
646	.flags = CLK_SET_RATE_PARENT,
647	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
648	},
649	};
650
651	static const struct alpha_pll_config cam_cc_pll11_config = {
652	.l = 0x30,
653	.alpha = 0x8aaa,
654	.config_ctl_val = 0x20485699,
655	.config_ctl_hi_val = 0x00182261,
656	.config_ctl_hi1_val = 0x82aa299c,
657	.test_ctl_val = 0x00000000,
658	.test_ctl_hi_val = 0x00000003,
659	.test_ctl_hi1_val = 0x00009000,
660	.test_ctl_hi2_val = 0x00000034,
661	.user_ctl_val = 0x00000400,
662	.user_ctl_hi_val = 0x00000005,
663	};
664
665	static struct clk_alpha_pll cam_cc_pll11 = {
666	.offset = 0xb000,
667	.vco_table = lucid_ole_vco,
668	.num_vco = ARRAY_SIZE(lucid_ole_vco),
669	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
670	.clkr = {
671	.hw.init = &(const struct clk_init_data) {
672	.name = "cam_cc_pll11",
673	.parent_data = &(const struct clk_parent_data) {
674	.index = DT_BI_TCXO,
675	},
676	.num_parents = 1,
677	.ops = &clk_alpha_pll_lucid_evo_ops,
678	},
679	},
680	};
681
682	static const struct clk_div_table post_div_table_cam_cc_pll11_out_even[] = {
683	{ 0x1, 2 },
684	{ }
685	};
686
687	static struct clk_alpha_pll_postdiv cam_cc_pll11_out_even = {
688	.offset = 0xb000,
689	.post_div_shift = 10,
690	.post_div_table = post_div_table_cam_cc_pll11_out_even,
691	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll11_out_even),
692	.width = 4,
693	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
694	.clkr.hw.init = &(const struct clk_init_data) {
695	.name = "cam_cc_pll11_out_even",
696	.parent_hws = (const struct clk_hw*[]) {
697	&cam_cc_pll11.clkr.hw,
698	},
699	.num_parents = 1,
700	.flags = CLK_SET_RATE_PARENT,
701	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
702	},
703	};
704
705	static const struct alpha_pll_config cam_cc_pll12_config = {
706	.l = 0x30,
707	.alpha = 0x8aaa,
708	.config_ctl_val = 0x20485699,
709	.config_ctl_hi_val = 0x00182261,
710	.config_ctl_hi1_val = 0x82aa299c,
711	.test_ctl_val = 0x00000000,
712	.test_ctl_hi_val = 0x00000003,
713	.test_ctl_hi1_val = 0x00009000,
714	.test_ctl_hi2_val = 0x00000034,
715	.user_ctl_val = 0x00000400,
716	.user_ctl_hi_val = 0x00000005,
717	};
718
719	static struct clk_alpha_pll cam_cc_pll12 = {
720	.offset = 0xc000,
721	.vco_table = lucid_ole_vco,
722	.num_vco = ARRAY_SIZE(lucid_ole_vco),
723	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
724	.clkr = {
725	.hw.init = &(const struct clk_init_data) {
726	.name = "cam_cc_pll12",
727	.parent_data = &(const struct clk_parent_data) {
728	.index = DT_BI_TCXO,
729	},
730	.num_parents = 1,
731	.ops = &clk_alpha_pll_lucid_evo_ops,
732	},
733	},
734	};
735
736	static const struct clk_div_table post_div_table_cam_cc_pll12_out_even[] = {
737	{ 0x1, 2 },
738	{ }
739	};
740
741	static struct clk_alpha_pll_postdiv cam_cc_pll12_out_even = {
742	.offset = 0xc000,
743	.post_div_shift = 10,
744	.post_div_table = post_div_table_cam_cc_pll12_out_even,
745	.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll12_out_even),
746	.width = 4,
747	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
748	.clkr.hw.init = &(const struct clk_init_data) {
749	.name = "cam_cc_pll12_out_even",
750	.parent_hws = (const struct clk_hw*[]) {
751	&cam_cc_pll12.clkr.hw,
752	},
753	.num_parents = 1,
754	.flags = CLK_SET_RATE_PARENT,
755	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
756	},
757	};
758
759	static const struct parent_map cam_cc_parent_map_0[] = {
760	{ P_BI_TCXO, 0 },
761	{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
762	{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
763	{ P_CAM_CC_PLL0_OUT_ODD, 3 },
764	{ P_CAM_CC_PLL9_OUT_ODD, 4 },
765	{ P_CAM_CC_PLL9_OUT_EVEN, 5 },
766	};
767
768	static const struct clk_parent_data cam_cc_parent_data_0[] = {
769	{ .index = DT_BI_TCXO },
770	{ .hw = &cam_cc_pll0.clkr.hw },
771	{ .hw = &cam_cc_pll0_out_even.clkr.hw },
772	{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
773	{ .hw = &cam_cc_pll9.clkr.hw },
774	{ .hw = &cam_cc_pll9_out_even.clkr.hw },
775	};
776
777	static const struct parent_map cam_cc_parent_map_1[] = {
778	{ P_BI_TCXO, 0 },
779	{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
780	{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
781	};
782
783	static const struct clk_parent_data cam_cc_parent_data_1[] = {
784	{ .index = DT_BI_TCXO },
785	{ .hw = &cam_cc_pll2.clkr.hw },
786	{ .hw = &cam_cc_pll2.clkr.hw },
787	};
788
789	static const struct parent_map cam_cc_parent_map_2[] = {
790	{ P_BI_TCXO, 0 },
791	{ P_CAM_CC_PLL8_OUT_EVEN, 6 },
792	};
793
794	static const struct clk_parent_data cam_cc_parent_data_2[] = {
795	{ .index = DT_BI_TCXO },
796	{ .hw = &cam_cc_pll8_out_even.clkr.hw },
797	};
798
799	static const struct parent_map cam_cc_parent_map_3[] = {
800	{ P_BI_TCXO, 0 },
801	{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
802	};
803
804	static const struct clk_parent_data cam_cc_parent_data_3[] = {
805	{ .index = DT_BI_TCXO },
806	{ .hw = &cam_cc_pll3_out_even.clkr.hw },
807	};
808
809	static const struct parent_map cam_cc_parent_map_4[] = {
810	{ P_BI_TCXO, 0 },
811	{ P_CAM_CC_PLL10_OUT_EVEN, 6 },
812	};
813
814	static const struct clk_parent_data cam_cc_parent_data_4[] = {
815	{ .index = DT_BI_TCXO },
816	{ .hw = &cam_cc_pll10_out_even.clkr.hw },
817	};
818
819	static const struct parent_map cam_cc_parent_map_5[] = {
820	{ P_BI_TCXO, 0 },
821	{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
822	};
823
824	static const struct clk_parent_data cam_cc_parent_data_5[] = {
825	{ .index = DT_BI_TCXO },
826	{ .hw = &cam_cc_pll4_out_even.clkr.hw },
827	};
828
829	static const struct parent_map cam_cc_parent_map_6[] = {
830	{ P_BI_TCXO, 0 },
831	{ P_CAM_CC_PLL11_OUT_EVEN, 6 },
832	};
833
834	static const struct clk_parent_data cam_cc_parent_data_6[] = {
835	{ .index = DT_BI_TCXO },
836	{ .hw = &cam_cc_pll11_out_even.clkr.hw },
837	};
838
839	static const struct parent_map cam_cc_parent_map_7[] = {
840	{ P_BI_TCXO, 0 },
841	{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
842	};
843
844	static const struct clk_parent_data cam_cc_parent_data_7[] = {
845	{ .index = DT_BI_TCXO },
846	{ .hw = &cam_cc_pll5_out_even.clkr.hw },
847	};
848
849	static const struct parent_map cam_cc_parent_map_8[] = {
850	{ P_BI_TCXO, 0 },
851	{ P_CAM_CC_PLL12_OUT_EVEN, 6 },
852	};
853
854	static const struct clk_parent_data cam_cc_parent_data_8[] = {
855	{ .index = DT_BI_TCXO },
856	{ .hw = &cam_cc_pll12_out_even.clkr.hw },
857	};
858
859	static const struct parent_map cam_cc_parent_map_9[] = {
860	{ P_BI_TCXO, 0 },
861	{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
862	};
863
864	static const struct clk_parent_data cam_cc_parent_data_9[] = {
865	{ .index = DT_BI_TCXO },
866	{ .hw = &cam_cc_pll1_out_even.clkr.hw },
867	};
868
869	static const struct parent_map cam_cc_parent_map_10[] = {
870	{ P_BI_TCXO, 0 },
871	{ P_CAM_CC_PLL6_OUT_EVEN, 6 },
872	};
873
874	static const struct clk_parent_data cam_cc_parent_data_10[] = {
875	{ .index = DT_BI_TCXO },
876	{ .hw = &cam_cc_pll6_out_even.clkr.hw },
877	};
878
879	static const struct parent_map cam_cc_parent_map_11[] = {
880	{ P_BI_TCXO, 0 },
881	{ P_CAM_CC_PLL7_OUT_EVEN, 6 },
882	};
883
884	static const struct clk_parent_data cam_cc_parent_data_11[] = {
885	{ .index = DT_BI_TCXO },
886	{ .hw = &cam_cc_pll7_out_even.clkr.hw },
887	};
888
889	static const struct parent_map cam_cc_parent_map_12[] = {
890	{ P_SLEEP_CLK, 0 },
891	};
892
893	static const struct clk_parent_data cam_cc_parent_data_12[] = {
894	{ .index = DT_SLEEP_CLK },
895	};
896
897	static const struct parent_map cam_cc_parent_map_13_ao[] = {
898	{ P_BI_TCXO_AO, 0 },
899	};
900
901	static const struct clk_parent_data cam_cc_parent_data_13_ao[] = {
902	{ .index = DT_BI_TCXO_AO },
903	};
904
905	static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
906	F(19200000, P_BI_TCXO, 1, 0, 0),
907	F(200000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
908	F(400000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
909	F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
910	F(785000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
911	{ }
912	};
913
914	static struct clk_rcg2 cam_cc_bps_clk_src = {
915	.cmd_rcgr = 0x10278,
916	.mnd_width = 0,
917	.hid_width = 5,
918	.parent_map = cam_cc_parent_map_2,
919	.freq_tbl = ftbl_cam_cc_bps_clk_src,
920	.clkr.hw.init = &(const struct clk_init_data) {
921	.name = "cam_cc_bps_clk_src",
922	.parent_data = cam_cc_parent_data_2,
923	.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
924	.flags = CLK_SET_RATE_PARENT,
925	.ops = &clk_rcg2_shared_ops,
926	},
927	};
928
929	static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
930	F(19200000, P_BI_TCXO, 1, 0, 0),
931	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
932	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
933	{ }
934	};
935
936	static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
937	.cmd_rcgr = 0x13de0,
938	.mnd_width = 0,
939	.hid_width = 5,
940	.parent_map = cam_cc_parent_map_0,
941	.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
942	.clkr.hw.init = &(const struct clk_init_data) {
943	.name = "cam_cc_camnoc_axi_clk_src",
944	.parent_data = cam_cc_parent_data_0,
945	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
946	.flags = CLK_SET_RATE_PARENT,
947	.ops = &clk_rcg2_shared_ops,
948	},
949	};
950
951	static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
952	F(19200000, P_BI_TCXO, 1, 0, 0),
953	F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
954	{ }
955	};
956
957	static struct clk_rcg2 cam_cc_cci_0_clk_src = {
958	.cmd_rcgr = 0x13900,
959	.mnd_width = 8,
960	.hid_width = 5,
961	.parent_map = cam_cc_parent_map_0,
962	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
963	.clkr.hw.init = &(const struct clk_init_data) {
964	.name = "cam_cc_cci_0_clk_src",
965	.parent_data = cam_cc_parent_data_0,
966	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
967	.flags = CLK_SET_RATE_PARENT,
968	.ops = &clk_rcg2_shared_ops,
969	},
970	};
971
972	static struct clk_rcg2 cam_cc_cci_1_clk_src = {
973	.cmd_rcgr = 0x13a30,
974	.mnd_width = 8,
975	.hid_width = 5,
976	.parent_map = cam_cc_parent_map_0,
977	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
978	.clkr.hw.init = &(const struct clk_init_data) {
979	.name = "cam_cc_cci_1_clk_src",
980	.parent_data = cam_cc_parent_data_0,
981	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
982	.flags = CLK_SET_RATE_PARENT,
983	.ops = &clk_rcg2_shared_ops,
984	},
985	};
986
987	static struct clk_rcg2 cam_cc_cci_2_clk_src = {
988	.cmd_rcgr = 0x13b60,
989	.mnd_width = 8,
990	.hid_width = 5,
991	.parent_map = cam_cc_parent_map_0,
992	.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
993	.clkr.hw.init = &(const struct clk_init_data) {
994	.name = "cam_cc_cci_2_clk_src",
995	.parent_data = cam_cc_parent_data_0,
996	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
997	.flags = CLK_SET_RATE_PARENT,
998	.ops = &clk_rcg2_shared_ops,
999	},
1000	};
1001
1002	static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
1003	F(19200000, P_BI_TCXO, 1, 0, 0),
1004	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1005	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
1006	{ }
1007	};
1008
1009	static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
1010	.cmd_rcgr = 0x11290,
1011	.mnd_width = 0,
1012	.hid_width = 5,
1013	.parent_map = cam_cc_parent_map_0,
1014	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
1015	.clkr.hw.init = &(const struct clk_init_data) {
1016	.name = "cam_cc_cphy_rx_clk_src",
1017	.parent_data = cam_cc_parent_data_0,
1018	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1019	.flags = CLK_SET_RATE_PARENT,
1020	.ops = &clk_rcg2_shared_ops,
1021	},
1022	};
1023
1024	static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = {
1025	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
1026	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1027	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
1028	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
1029	{ }
1030	};
1031
1032	static struct clk_rcg2 cam_cc_cre_clk_src = {
1033	.cmd_rcgr = 0x1353c,
1034	.mnd_width = 0,
1035	.hid_width = 5,
1036	.parent_map = cam_cc_parent_map_0,
1037	.freq_tbl = ftbl_cam_cc_cre_clk_src,
1038	.clkr.hw.init = &(const struct clk_init_data) {
1039	.name = "cam_cc_cre_clk_src",
1040	.parent_data = cam_cc_parent_data_0,
1041	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1042	.flags = CLK_SET_RATE_PARENT,
1043	.ops = &clk_rcg2_shared_ops,
1044	},
1045	};
1046
1047	static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
1048	F(19200000, P_BI_TCXO, 1, 0, 0),
1049	F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
1050	{ }
1051	};
1052
1053	static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
1054	.cmd_rcgr = 0x15980,
1055	.mnd_width = 0,
1056	.hid_width = 5,
1057	.parent_map = cam_cc_parent_map_0,
1058	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1059	.clkr.hw.init = &(const struct clk_init_data) {
1060	.name = "cam_cc_csi0phytimer_clk_src",
1061	.parent_data = cam_cc_parent_data_0,
1062	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1063	.flags = CLK_SET_RATE_PARENT,
1064	.ops = &clk_rcg2_shared_ops,
1065	},
1066	};
1067
1068	static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
1069	.cmd_rcgr = 0x15ab8,
1070	.mnd_width = 0,
1071	.hid_width = 5,
1072	.parent_map = cam_cc_parent_map_0,
1073	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1074	.clkr.hw.init = &(const struct clk_init_data) {
1075	.name = "cam_cc_csi1phytimer_clk_src",
1076	.parent_data = cam_cc_parent_data_0,
1077	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1078	.flags = CLK_SET_RATE_PARENT,
1079	.ops = &clk_rcg2_shared_ops,
1080	},
1081	};
1082
1083	static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
1084	.cmd_rcgr = 0x15bec,
1085	.mnd_width = 0,
1086	.hid_width = 5,
1087	.parent_map = cam_cc_parent_map_0,
1088	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1089	.clkr.hw.init = &(const struct clk_init_data) {
1090	.name = "cam_cc_csi2phytimer_clk_src",
1091	.parent_data = cam_cc_parent_data_0,
1092	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1093	.flags = CLK_SET_RATE_PARENT,
1094	.ops = &clk_rcg2_shared_ops,
1095	},
1096	};
1097
1098	static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
1099	.cmd_rcgr = 0x15d20,
1100	.mnd_width = 0,
1101	.hid_width = 5,
1102	.parent_map = cam_cc_parent_map_0,
1103	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1104	.clkr.hw.init = &(const struct clk_init_data) {
1105	.name = "cam_cc_csi3phytimer_clk_src",
1106	.parent_data = cam_cc_parent_data_0,
1107	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1108	.flags = CLK_SET_RATE_PARENT,
1109	.ops = &clk_rcg2_shared_ops,
1110	},
1111	};
1112
1113	static const struct freq_tbl ftbl_cam_cc_csi4phytimer_clk_src[] = {
1114	F(19200000, P_BI_TCXO, 1, 0, 0),
1115	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1116	{ }
1117	};
1118
1119	static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
1120	.cmd_rcgr = 0x15e54,
1121	.mnd_width = 0,
1122	.hid_width = 5,
1123	.parent_map = cam_cc_parent_map_0,
1124	.freq_tbl = ftbl_cam_cc_csi4phytimer_clk_src,
1125	.clkr.hw.init = &(const struct clk_init_data) {
1126	.name = "cam_cc_csi4phytimer_clk_src",
1127	.parent_data = cam_cc_parent_data_0,
1128	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1129	.flags = CLK_SET_RATE_PARENT,
1130	.ops = &clk_rcg2_shared_ops,
1131	},
1132	};
1133
1134	static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
1135	.cmd_rcgr = 0x15f88,
1136	.mnd_width = 0,
1137	.hid_width = 5,
1138	.parent_map = cam_cc_parent_map_0,
1139	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1140	.clkr.hw.init = &(const struct clk_init_data) {
1141	.name = "cam_cc_csi5phytimer_clk_src",
1142	.parent_data = cam_cc_parent_data_0,
1143	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1144	.flags = CLK_SET_RATE_PARENT,
1145	.ops = &clk_rcg2_shared_ops,
1146	},
1147	};
1148
1149	static struct clk_rcg2 cam_cc_csi6phytimer_clk_src = {
1150	.cmd_rcgr = 0x160bc,
1151	.mnd_width = 0,
1152	.hid_width = 5,
1153	.parent_map = cam_cc_parent_map_0,
1154	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1155	.clkr.hw.init = &(const struct clk_init_data) {
1156	.name = "cam_cc_csi6phytimer_clk_src",
1157	.parent_data = cam_cc_parent_data_0,
1158	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1159	.flags = CLK_SET_RATE_PARENT,
1160	.ops = &clk_rcg2_shared_ops,
1161	},
1162	};
1163
1164	static struct clk_rcg2 cam_cc_csi7phytimer_clk_src = {
1165	.cmd_rcgr = 0x161f0,
1166	.mnd_width = 0,
1167	.hid_width = 5,
1168	.parent_map = cam_cc_parent_map_0,
1169	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
1170	.clkr.hw.init = &(const struct clk_init_data) {
1171	.name = "cam_cc_csi7phytimer_clk_src",
1172	.parent_data = cam_cc_parent_data_0,
1173	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1174	.flags = CLK_SET_RATE_PARENT,
1175	.ops = &clk_rcg2_shared_ops,
1176	},
1177	};
1178
1179	static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
1180	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1181	F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
1182	{ }
1183	};
1184
1185	static struct clk_rcg2 cam_cc_csid_clk_src = {
1186	.cmd_rcgr = 0x13ca8,
1187	.mnd_width = 0,
1188	.hid_width = 5,
1189	.parent_map = cam_cc_parent_map_0,
1190	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1191	.clkr.hw.init = &(const struct clk_init_data) {
1192	.name = "cam_cc_csid_clk_src",
1193	.parent_data = cam_cc_parent_data_0,
1194	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1195	.flags = CLK_SET_RATE_PARENT,
1196	.ops = &clk_rcg2_shared_ops,
1197	},
1198	};
1199
1200	static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
1201	F(19200000, P_BI_TCXO, 1, 0, 0),
1202	F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
1203	F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1204	{ }
1205	};
1206
1207	static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
1208	.cmd_rcgr = 0x10018,
1209	.mnd_width = 0,
1210	.hid_width = 5,
1211	.parent_map = cam_cc_parent_map_0,
1212	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
1213	.clkr.hw.init = &(const struct clk_init_data) {
1214	.name = "cam_cc_fast_ahb_clk_src",
1215	.parent_data = cam_cc_parent_data_0,
1216	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1217	.flags = CLK_SET_RATE_PARENT,
1218	.ops = &clk_rcg2_shared_ops,
1219	},
1220	};
1221
1222	static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
1223	F(19200000, P_BI_TCXO, 1, 0, 0),
1224	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1225	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
1226	F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
1227	{ }
1228	};
1229
1230	static struct clk_rcg2 cam_cc_icp_clk_src = {
1231	.cmd_rcgr = 0x137c4,
1232	.mnd_width = 0,
1233	.hid_width = 5,
1234	.parent_map = cam_cc_parent_map_0,
1235	.freq_tbl = ftbl_cam_cc_icp_clk_src,
1236	.clkr.hw.init = &(const struct clk_init_data) {
1237	.name = "cam_cc_icp_clk_src",
1238	.parent_data = cam_cc_parent_data_0,
1239	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1240	.flags = CLK_SET_RATE_PARENT,
1241	.ops = &clk_rcg2_shared_ops,
1242	},
1243	};
1244
1245	static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
1246	F(19200000, P_BI_TCXO, 1, 0, 0),
1247	F(466000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1248	F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1249	F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1250	F(785000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
1251	{ }
1252	};
1253
1254	static struct clk_rcg2 cam_cc_ife_0_clk_src = {
1255	.cmd_rcgr = 0x11018,
1256	.mnd_width = 0,
1257	.hid_width = 5,
1258	.parent_map = cam_cc_parent_map_3,
1259	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
1260	.clkr.hw.init = &(const struct clk_init_data) {
1261	.name = "cam_cc_ife_0_clk_src",
1262	.parent_data = cam_cc_parent_data_3,
1263	.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
1264	.flags = CLK_SET_RATE_PARENT,
1265	.ops = &clk_rcg2_shared_ops,
1266	},
1267	};
1268
1269	static const struct freq_tbl ftbl_cam_cc_ife_0_dsp_clk_src[] = {
1270	F(466000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1271	F(594000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1272	F(675000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1273	F(785000000, P_CAM_CC_PLL10_OUT_EVEN, 1, 0, 0),
1274	{ }
1275	};
1276
1277	static struct clk_rcg2 cam_cc_ife_0_dsp_clk_src = {
1278	.cmd_rcgr = 0x11154,
1279	.mnd_width = 0,
1280	.hid_width = 5,
1281	.parent_map = cam_cc_parent_map_4,
1282	.freq_tbl = ftbl_cam_cc_ife_0_dsp_clk_src,
1283	.clkr.hw.init = &(const struct clk_init_data) {
1284	.name = "cam_cc_ife_0_dsp_clk_src",
1285	.parent_data = cam_cc_parent_data_4,
1286	.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
1287	.flags = CLK_SET_RATE_PARENT,
1288	.ops = &clk_rcg2_shared_ops,
1289	},
1290	};
1291
1292	static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
1293	F(19200000, P_BI_TCXO, 1, 0, 0),
1294	F(466000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1295	F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1296	F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1297	F(785000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
1298	{ }
1299	};
1300
1301	static struct clk_rcg2 cam_cc_ife_1_clk_src = {
1302	.cmd_rcgr = 0x12018,
1303	.mnd_width = 0,
1304	.hid_width = 5,
1305	.parent_map = cam_cc_parent_map_5,
1306	.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
1307	.clkr.hw.init = &(const struct clk_init_data) {
1308	.name = "cam_cc_ife_1_clk_src",
1309	.parent_data = cam_cc_parent_data_5,
1310	.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
1311	.flags = CLK_SET_RATE_PARENT,
1312	.ops = &clk_rcg2_shared_ops,
1313	},
1314	};
1315
1316	static const struct freq_tbl ftbl_cam_cc_ife_1_dsp_clk_src[] = {
1317	F(466000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
1318	F(594000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
1319	F(675000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
1320	F(785000000, P_CAM_CC_PLL11_OUT_EVEN, 1, 0, 0),
1321	{ }
1322	};
1323
1324	static struct clk_rcg2 cam_cc_ife_1_dsp_clk_src = {
1325	.cmd_rcgr = 0x12154,
1326	.mnd_width = 0,
1327	.hid_width = 5,
1328	.parent_map = cam_cc_parent_map_6,
1329	.freq_tbl = ftbl_cam_cc_ife_1_dsp_clk_src,
1330	.clkr.hw.init = &(const struct clk_init_data) {
1331	.name = "cam_cc_ife_1_dsp_clk_src",
1332	.parent_data = cam_cc_parent_data_6,
1333	.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
1334	.flags = CLK_SET_RATE_PARENT,
1335	.ops = &clk_rcg2_shared_ops,
1336	},
1337	};
1338
1339	static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
1340	F(466000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1341	F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1342	F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1343	F(785000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
1344	{ }
1345	};
1346
1347	static struct clk_rcg2 cam_cc_ife_2_clk_src = {
1348	.cmd_rcgr = 0x122a8,
1349	.mnd_width = 0,
1350	.hid_width = 5,
1351	.parent_map = cam_cc_parent_map_7,
1352	.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
1353	.clkr.hw.init = &(const struct clk_init_data) {
1354	.name = "cam_cc_ife_2_clk_src",
1355	.parent_data = cam_cc_parent_data_7,
1356	.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
1357	.flags = CLK_SET_RATE_PARENT,
1358	.ops = &clk_rcg2_shared_ops,
1359	},
1360	};
1361
1362	static const struct freq_tbl ftbl_cam_cc_ife_2_dsp_clk_src[] = {
1363	F(466000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
1364	F(594000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
1365	F(675000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
1366	F(785000000, P_CAM_CC_PLL12_OUT_EVEN, 1, 0, 0),
1367	{ }
1368	};
1369
1370	static struct clk_rcg2 cam_cc_ife_2_dsp_clk_src = {
1371	.cmd_rcgr = 0x123e4,
1372	.mnd_width = 0,
1373	.hid_width = 5,
1374	.parent_map = cam_cc_parent_map_8,
1375	.freq_tbl = ftbl_cam_cc_ife_2_dsp_clk_src,
1376	.clkr.hw.init = &(const struct clk_init_data) {
1377	.name = "cam_cc_ife_2_dsp_clk_src",
1378	.parent_data = cam_cc_parent_data_8,
1379	.num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
1380	.flags = CLK_SET_RATE_PARENT,
1381	.ops = &clk_rcg2_shared_ops,
1382	},
1383	};
1384
1385	static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
1386	.cmd_rcgr = 0x13000,
1387	.mnd_width = 0,
1388	.hid_width = 5,
1389	.parent_map = cam_cc_parent_map_0,
1390	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1391	.clkr.hw.init = &(const struct clk_init_data) {
1392	.name = "cam_cc_ife_lite_clk_src",
1393	.parent_data = cam_cc_parent_data_0,
1394	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1395	.flags = CLK_SET_RATE_PARENT,
1396	.ops = &clk_rcg2_shared_ops,
1397	},
1398	};
1399
1400	static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
1401	.cmd_rcgr = 0x1313c,
1402	.mnd_width = 0,
1403	.hid_width = 5,
1404	.parent_map = cam_cc_parent_map_0,
1405	.freq_tbl = ftbl_cam_cc_csid_clk_src,
1406	.clkr.hw.init = &(const struct clk_init_data) {
1407	.name = "cam_cc_ife_lite_csid_clk_src",
1408	.parent_data = cam_cc_parent_data_0,
1409	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1410	.flags = CLK_SET_RATE_PARENT,
1411	.ops = &clk_rcg2_shared_ops,
1412	},
1413	};
1414
1415	static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
1416	F(455000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1417	F(575000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1418	F(675000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1419	F(825000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1420	{ }
1421	};
1422
1423	static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
1424	.cmd_rcgr = 0x103cc,
1425	.mnd_width = 0,
1426	.hid_width = 5,
1427	.parent_map = cam_cc_parent_map_9,
1428	.freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
1429	.clkr.hw.init = &(const struct clk_init_data) {
1430	.name = "cam_cc_ipe_nps_clk_src",
1431	.parent_data = cam_cc_parent_data_9,
1432	.num_parents = ARRAY_SIZE(cam_cc_parent_data_9),
1433	.flags = CLK_SET_RATE_PARENT,
1434	.ops = &clk_rcg2_shared_ops,
1435	},
1436	};
1437
1438	static const struct freq_tbl ftbl_cam_cc_jpeg_clk_src[] = {
1439	F(19200000, P_BI_TCXO, 1, 0, 0),
1440	F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
1441	F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
1442	F(480000000, P_CAM_CC_PLL9_OUT_EVEN, 1, 0, 0),
1443	F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
1444	{ }
1445	};
1446
1447	static struct clk_rcg2 cam_cc_jpeg_clk_src = {
1448	.cmd_rcgr = 0x13674,
1449	.mnd_width = 0,
1450	.hid_width = 5,
1451	.parent_map = cam_cc_parent_map_0,
1452	.freq_tbl = ftbl_cam_cc_jpeg_clk_src,
1453	.clkr.hw.init = &(const struct clk_init_data) {
1454	.name = "cam_cc_jpeg_clk_src",
1455	.parent_data = cam_cc_parent_data_0,
1456	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1457	.flags = CLK_SET_RATE_PARENT,
1458	.ops = &clk_rcg2_shared_ops,
1459	},
1460	};
1461
1462	static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
1463	F(19200000, P_BI_TCXO, 1, 0, 0),
1464	F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
1465	F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
1466	{ }
1467	};
1468
1469	static struct clk_rcg2 cam_cc_mclk0_clk_src = {
1470	.cmd_rcgr = 0x15000,
1471	.mnd_width = 8,
1472	.hid_width = 5,
1473	.parent_map = cam_cc_parent_map_1,
1474	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1475	.clkr.hw.init = &(const struct clk_init_data) {
1476	.name = "cam_cc_mclk0_clk_src",
1477	.parent_data = cam_cc_parent_data_1,
1478	.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1479	.flags = CLK_SET_RATE_PARENT,
1480	.ops = &clk_rcg2_shared_ops,
1481	},
1482	};
1483
1484	static struct clk_rcg2 cam_cc_mclk1_clk_src = {
1485	.cmd_rcgr = 0x15130,
1486	.mnd_width = 8,
1487	.hid_width = 5,
1488	.parent_map = cam_cc_parent_map_1,
1489	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1490	.clkr.hw.init = &(const struct clk_init_data) {
1491	.name = "cam_cc_mclk1_clk_src",
1492	.parent_data = cam_cc_parent_data_1,
1493	.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1494	.flags = CLK_SET_RATE_PARENT,
1495	.ops = &clk_rcg2_shared_ops,
1496	},
1497	};
1498
1499	static struct clk_rcg2 cam_cc_mclk2_clk_src = {
1500	.cmd_rcgr = 0x15260,
1501	.mnd_width = 8,
1502	.hid_width = 5,
1503	.parent_map = cam_cc_parent_map_1,
1504	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1505	.clkr.hw.init = &(const struct clk_init_data) {
1506	.name = "cam_cc_mclk2_clk_src",
1507	.parent_data = cam_cc_parent_data_1,
1508	.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1509	.flags = CLK_SET_RATE_PARENT,
1510	.ops = &clk_rcg2_shared_ops,
1511	},
1512	};
1513
1514	static struct clk_rcg2 cam_cc_mclk3_clk_src = {
1515	.cmd_rcgr = 0x15390,
1516	.mnd_width = 8,
1517	.hid_width = 5,
1518	.parent_map = cam_cc_parent_map_1,
1519	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1520	.clkr.hw.init = &(const struct clk_init_data) {
1521	.name = "cam_cc_mclk3_clk_src",
1522	.parent_data = cam_cc_parent_data_1,
1523	.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1524	.flags = CLK_SET_RATE_PARENT,
1525	.ops = &clk_rcg2_shared_ops,
1526	},
1527	};
1528
1529	static struct clk_rcg2 cam_cc_mclk4_clk_src = {
1530	.cmd_rcgr = 0x154c0,
1531	.mnd_width = 8,
1532	.hid_width = 5,
1533	.parent_map = cam_cc_parent_map_1,
1534	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1535	.clkr.hw.init = &(const struct clk_init_data) {
1536	.name = "cam_cc_mclk4_clk_src",
1537	.parent_data = cam_cc_parent_data_1,
1538	.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1539	.flags = CLK_SET_RATE_PARENT,
1540	.ops = &clk_rcg2_shared_ops,
1541	},
1542	};
1543
1544	static struct clk_rcg2 cam_cc_mclk5_clk_src = {
1545	.cmd_rcgr = 0x155f0,
1546	.mnd_width = 8,
1547	.hid_width = 5,
1548	.parent_map = cam_cc_parent_map_1,
1549	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1550	.clkr.hw.init = &(const struct clk_init_data) {
1551	.name = "cam_cc_mclk5_clk_src",
1552	.parent_data = cam_cc_parent_data_1,
1553	.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1554	.flags = CLK_SET_RATE_PARENT,
1555	.ops = &clk_rcg2_shared_ops,
1556	},
1557	};
1558
1559	static struct clk_rcg2 cam_cc_mclk6_clk_src = {
1560	.cmd_rcgr = 0x15720,
1561	.mnd_width = 8,
1562	.hid_width = 5,
1563	.parent_map = cam_cc_parent_map_1,
1564	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1565	.clkr.hw.init = &(const struct clk_init_data) {
1566	.name = "cam_cc_mclk6_clk_src",
1567	.parent_data = cam_cc_parent_data_1,
1568	.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1569	.flags = CLK_SET_RATE_PARENT,
1570	.ops = &clk_rcg2_shared_ops,
1571	},
1572	};
1573
1574	static struct clk_rcg2 cam_cc_mclk7_clk_src = {
1575	.cmd_rcgr = 0x15850,
1576	.mnd_width = 8,
1577	.hid_width = 5,
1578	.parent_map = cam_cc_parent_map_1,
1579	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1580	.clkr.hw.init = &(const struct clk_init_data) {
1581	.name = "cam_cc_mclk7_clk_src",
1582	.parent_data = cam_cc_parent_data_1,
1583	.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1584	.flags = CLK_SET_RATE_PARENT,
1585	.ops = &clk_rcg2_shared_ops,
1586	},
1587	};
1588
1589	static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
1590	F(19200000, P_BI_TCXO, 1, 0, 0),
1591	F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
1592	F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
1593	F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
1594	{ }
1595	};
1596
1597	static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
1598	.cmd_rcgr = 0x13f24,
1599	.mnd_width = 0,
1600	.hid_width = 5,
1601	.parent_map = cam_cc_parent_map_0,
1602	.freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
1603	.clkr.hw.init = &(const struct clk_init_data) {
1604	.name = "cam_cc_qdss_debug_clk_src",
1605	.parent_data = cam_cc_parent_data_0,
1606	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1607	.flags = CLK_SET_RATE_PARENT,
1608	.ops = &clk_rcg2_shared_ops,
1609	},
1610	};
1611
1612	static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
1613	F(466000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1614	F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1615	F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1616	F(785000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1617	{ }
1618	};
1619
1620	static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
1621	.cmd_rcgr = 0x13294,
1622	.mnd_width = 0,
1623	.hid_width = 5,
1624	.parent_map = cam_cc_parent_map_10,
1625	.freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
1626	.clkr.hw.init = &(const struct clk_init_data) {
1627	.name = "cam_cc_sfe_0_clk_src",
1628	.parent_data = cam_cc_parent_data_10,
1629	.num_parents = ARRAY_SIZE(cam_cc_parent_data_10),
1630	.flags = CLK_SET_RATE_PARENT,
1631	.ops = &clk_rcg2_shared_ops,
1632	},
1633	};
1634
1635	static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
1636	F(466000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1637	F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1638	F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1639	F(785000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1640	{ }
1641	};
1642
1643	static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
1644	.cmd_rcgr = 0x133f4,
1645	.mnd_width = 0,
1646	.hid_width = 5,
1647	.parent_map = cam_cc_parent_map_11,
1648	.freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
1649	.clkr.hw.init = &(const struct clk_init_data) {
1650	.name = "cam_cc_sfe_1_clk_src",
1651	.parent_data = cam_cc_parent_data_11,
1652	.num_parents = ARRAY_SIZE(cam_cc_parent_data_11),
1653	.flags = CLK_SET_RATE_PARENT,
1654	.ops = &clk_rcg2_shared_ops,
1655	},
1656	};
1657
1658	static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
1659	F(32000, P_SLEEP_CLK, 1, 0, 0),
1660	{ }
1661	};
1662
1663	static struct clk_rcg2 cam_cc_sleep_clk_src = {
1664	.cmd_rcgr = 0x141a0,
1665	.mnd_width = 0,
1666	.hid_width = 5,
1667	.parent_map = cam_cc_parent_map_12,
1668	.freq_tbl = ftbl_cam_cc_sleep_clk_src,
1669	.clkr.hw.init = &(const struct clk_init_data) {
1670	.name = "cam_cc_sleep_clk_src",
1671	.parent_data = cam_cc_parent_data_12,
1672	.num_parents = ARRAY_SIZE(cam_cc_parent_data_12),
1673	.flags = CLK_SET_RATE_PARENT,
1674	.ops = &clk_rcg2_shared_ops,
1675	},
1676	};
1677
1678	static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
1679	F(19200000, P_BI_TCXO, 1, 0, 0),
1680	F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
1681	{ }
1682	};
1683
1684	static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
1685	.cmd_rcgr = 0x10148,
1686	.mnd_width = 8,
1687	.hid_width = 5,
1688	.parent_map = cam_cc_parent_map_0,
1689	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
1690	.clkr.hw.init = &(const struct clk_init_data) {
1691	.name = "cam_cc_slow_ahb_clk_src",
1692	.parent_data = cam_cc_parent_data_0,
1693	.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1694	.flags = CLK_SET_RATE_PARENT,
1695	.ops = &clk_rcg2_shared_ops,
1696	},
1697	};
1698
1699	static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1700	F(19200000, P_BI_TCXO_AO, 1, 0, 0),
1701	{ }
1702	};
1703
1704	static struct clk_rcg2 cam_cc_xo_clk_src = {
1705	.cmd_rcgr = 0x14070,
1706	.mnd_width = 0,
1707	.hid_width = 5,
1708	.parent_map = cam_cc_parent_map_13_ao,
1709	.freq_tbl = ftbl_cam_cc_xo_clk_src,
1710	.clkr.hw.init = &(const struct clk_init_data) {
1711	.name = "cam_cc_xo_clk_src",
1712	.parent_data = cam_cc_parent_data_13_ao,
1713	.num_parents = ARRAY_SIZE(cam_cc_parent_data_13_ao),
1714	.flags = CLK_SET_RATE_PARENT,
1715	.ops = &clk_rcg2_shared_ops,
1716	},
1717	};
1718
1719	static struct clk_branch cam_cc_bps_ahb_clk = {
1720	.halt_reg = 0x10274,
1721	.halt_check = BRANCH_HALT,
1722	.clkr = {
1723	.enable_reg = 0x10274,
1724	.enable_mask = BIT(0),
1725	.hw.init = &(const struct clk_init_data) {
1726	.name = "cam_cc_bps_ahb_clk",
1727	.parent_hws = (const struct clk_hw*[]) {
1728	&cam_cc_slow_ahb_clk_src.clkr.hw,
1729	},
1730	.num_parents = 1,
1731	.flags = CLK_SET_RATE_PARENT,
1732	.ops = &clk_branch2_ops,
1733	},
1734	},
1735	};
1736
1737	static struct clk_branch cam_cc_bps_clk = {
1738	.halt_reg = 0x103a4,
1739	.halt_check = BRANCH_HALT,
1740	.clkr = {
1741	.enable_reg = 0x103a4,
1742	.enable_mask = BIT(0),
1743	.hw.init = &(const struct clk_init_data) {
1744	.name = "cam_cc_bps_clk",
1745	.parent_hws = (const struct clk_hw*[]) {
1746	&cam_cc_bps_clk_src.clkr.hw,
1747	},
1748	.num_parents = 1,
1749	.flags = CLK_SET_RATE_PARENT,
1750	.ops = &clk_branch2_ops,
1751	},
1752	},
1753	};
1754
1755	static struct clk_branch cam_cc_bps_fast_ahb_clk = {
1756	.halt_reg = 0x10144,
1757	.halt_check = BRANCH_HALT,
1758	.clkr = {
1759	.enable_reg = 0x10144,
1760	.enable_mask = BIT(0),
1761	.hw.init = &(const struct clk_init_data) {
1762	.name = "cam_cc_bps_fast_ahb_clk",
1763	.parent_hws = (const struct clk_hw*[]) {
1764	&cam_cc_fast_ahb_clk_src.clkr.hw,
1765	},
1766	.num_parents = 1,
1767	.flags = CLK_SET_RATE_PARENT,
1768	.ops = &clk_branch2_ops,
1769	},
1770	},
1771	};
1772
1773	static struct clk_branch cam_cc_camnoc_axi_clk = {
1774	.halt_reg = 0x13f0c,
1775	.halt_check = BRANCH_HALT,
1776	.clkr = {
1777	.enable_reg = 0x13f0c,
1778	.enable_mask = BIT(0),
1779	.hw.init = &(const struct clk_init_data) {
1780	.name = "cam_cc_camnoc_axi_clk",
1781	.parent_hws = (const struct clk_hw*[]) {
1782	&cam_cc_camnoc_axi_clk_src.clkr.hw,
1783	},
1784	.num_parents = 1,
1785	.flags = CLK_SET_RATE_PARENT,
1786	.ops = &clk_branch2_ops,
1787	},
1788	},
1789	};
1790
1791	static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1792	.halt_reg = 0x13f18,
1793	.halt_check = BRANCH_HALT,
1794	.clkr = {
1795	.enable_reg = 0x13f18,
1796	.enable_mask = BIT(0),
1797	.hw.init = &(const struct clk_init_data) {
1798	.name = "cam_cc_camnoc_dcd_xo_clk",
1799	.parent_hws = (const struct clk_hw*[]) {
1800	&cam_cc_xo_clk_src.clkr.hw,
1801	},
1802	.num_parents = 1,
1803	.flags = CLK_SET_RATE_PARENT,
1804	.ops = &clk_branch2_ops,
1805	},
1806	},
1807	};
1808
1809	static struct clk_branch cam_cc_camnoc_xo_clk = {
1810	.halt_reg = 0x13f1c,
1811	.halt_check = BRANCH_HALT,
1812	.clkr = {
1813	.enable_reg = 0x13f1c,
1814	.enable_mask = BIT(0),
1815	.hw.init = &(const struct clk_init_data) {
1816	.name = "cam_cc_camnoc_xo_clk",
1817	.parent_hws = (const struct clk_hw*[]) {
1818	&cam_cc_xo_clk_src.clkr.hw,
1819	},
1820	.num_parents = 1,
1821	.flags = CLK_SET_RATE_PARENT,
1822	.ops = &clk_branch2_ops,
1823	},
1824	},
1825	};
1826
1827	static struct clk_branch cam_cc_cci_0_clk = {
1828	.halt_reg = 0x13a2c,
1829	.halt_check = BRANCH_HALT,
1830	.clkr = {
1831	.enable_reg = 0x13a2c,
1832	.enable_mask = BIT(0),
1833	.hw.init = &(const struct clk_init_data) {
1834	.name = "cam_cc_cci_0_clk",
1835	.parent_hws = (const struct clk_hw*[]) {
1836	&cam_cc_cci_0_clk_src.clkr.hw,
1837	},
1838	.num_parents = 1,
1839	.flags = CLK_SET_RATE_PARENT,
1840	.ops = &clk_branch2_ops,
1841	},
1842	},
1843	};
1844
1845	static struct clk_branch cam_cc_cci_1_clk = {
1846	.halt_reg = 0x13b5c,
1847	.halt_check = BRANCH_HALT,
1848	.clkr = {
1849	.enable_reg = 0x13b5c,
1850	.enable_mask = BIT(0),
1851	.hw.init = &(const struct clk_init_data) {
1852	.name = "cam_cc_cci_1_clk",
1853	.parent_hws = (const struct clk_hw*[]) {
1854	&cam_cc_cci_1_clk_src.clkr.hw,
1855	},
1856	.num_parents = 1,
1857	.flags = CLK_SET_RATE_PARENT,
1858	.ops = &clk_branch2_ops,
1859	},
1860	},
1861	};
1862
1863	static struct clk_branch cam_cc_cci_2_clk = {
1864	.halt_reg = 0x13c8c,
1865	.halt_check = BRANCH_HALT,
1866	.clkr = {
1867	.enable_reg = 0x13c8c,
1868	.enable_mask = BIT(0),
1869	.hw.init = &(const struct clk_init_data) {
1870	.name = "cam_cc_cci_2_clk",
1871	.parent_hws = (const struct clk_hw*[]) {
1872	&cam_cc_cci_2_clk_src.clkr.hw,
1873	},
1874	.num_parents = 1,
1875	.flags = CLK_SET_RATE_PARENT,
1876	.ops = &clk_branch2_ops,
1877	},
1878	},
1879	};
1880
1881	static struct clk_branch cam_cc_core_ahb_clk = {
1882	.halt_reg = 0x1406c,
1883	.halt_check = BRANCH_HALT_DELAY,
1884	.clkr = {
1885	.enable_reg = 0x1406c,
1886	.enable_mask = BIT(0),
1887	.hw.init = &(const struct clk_init_data) {
1888	.name = "cam_cc_core_ahb_clk",
1889	.parent_hws = (const struct clk_hw*[]) {
1890	&cam_cc_slow_ahb_clk_src.clkr.hw,
1891	},
1892	.num_parents = 1,
1893	.flags = CLK_SET_RATE_PARENT,
1894	.ops = &clk_branch2_ops,
1895	},
1896	},
1897	};
1898
1899	static struct clk_branch cam_cc_cpas_ahb_clk = {
1900	.halt_reg = 0x13c90,
1901	.halt_check = BRANCH_HALT,
1902	.clkr = {
1903	.enable_reg = 0x13c90,
1904	.enable_mask = BIT(0),
1905	.hw.init = &(const struct clk_init_data) {
1906	.name = "cam_cc_cpas_ahb_clk",
1907	.parent_hws = (const struct clk_hw*[]) {
1908	&cam_cc_slow_ahb_clk_src.clkr.hw,
1909	},
1910	.num_parents = 1,
1911	.flags = CLK_SET_RATE_PARENT,
1912	.ops = &clk_branch2_ops,
1913	},
1914	},
1915	};
1916
1917	static struct clk_branch cam_cc_cpas_bps_clk = {
1918	.halt_reg = 0x103b0,
1919	.halt_check = BRANCH_HALT,
1920	.clkr = {
1921	.enable_reg = 0x103b0,
1922	.enable_mask = BIT(0),
1923	.hw.init = &(const struct clk_init_data) {
1924	.name = "cam_cc_cpas_bps_clk",
1925	.parent_hws = (const struct clk_hw*[]) {
1926	&cam_cc_bps_clk_src.clkr.hw,
1927	},
1928	.num_parents = 1,
1929	.flags = CLK_SET_RATE_PARENT,
1930	.ops = &clk_branch2_ops,
1931	},
1932	},
1933	};
1934
1935	static struct clk_branch cam_cc_cpas_cre_clk = {
1936	.halt_reg = 0x1366c,
1937	.halt_check = BRANCH_HALT,
1938	.clkr = {
1939	.enable_reg = 0x1366c,
1940	.enable_mask = BIT(0),
1941	.hw.init = &(const struct clk_init_data) {
1942	.name = "cam_cc_cpas_cre_clk",
1943	.parent_hws = (const struct clk_hw*[]) {
1944	&cam_cc_cre_clk_src.clkr.hw,
1945	},
1946	.num_parents = 1,
1947	.flags = CLK_SET_RATE_PARENT,
1948	.ops = &clk_branch2_ops,
1949	},
1950	},
1951	};
1952
1953	static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
1954	.halt_reg = 0x13c9c,
1955	.halt_check = BRANCH_HALT,
1956	.clkr = {
1957	.enable_reg = 0x13c9c,
1958	.enable_mask = BIT(0),
1959	.hw.init = &(const struct clk_init_data) {
1960	.name = "cam_cc_cpas_fast_ahb_clk",
1961	.parent_hws = (const struct clk_hw*[]) {
1962	&cam_cc_fast_ahb_clk_src.clkr.hw,
1963	},
1964	.num_parents = 1,
1965	.flags = CLK_SET_RATE_PARENT,
1966	.ops = &clk_branch2_ops,
1967	},
1968	},
1969	};
1970
1971	static struct clk_branch cam_cc_cpas_ife_0_clk = {
1972	.halt_reg = 0x11150,
1973	.halt_check = BRANCH_HALT,
1974	.clkr = {
1975	.enable_reg = 0x11150,
1976	.enable_mask = BIT(0),
1977	.hw.init = &(const struct clk_init_data) {
1978	.name = "cam_cc_cpas_ife_0_clk",
1979	.parent_hws = (const struct clk_hw*[]) {
1980	&cam_cc_ife_0_clk_src.clkr.hw,
1981	},
1982	.num_parents = 1,
1983	.flags = CLK_SET_RATE_PARENT,
1984	.ops = &clk_branch2_ops,
1985	},
1986	},
1987	};
1988
1989	static struct clk_branch cam_cc_cpas_ife_1_clk = {
1990	.halt_reg = 0x12150,
1991	.halt_check = BRANCH_HALT,
1992	.clkr = {
1993	.enable_reg = 0x12150,
1994	.enable_mask = BIT(0),
1995	.hw.init = &(const struct clk_init_data) {
1996	.name = "cam_cc_cpas_ife_1_clk",
1997	.parent_hws = (const struct clk_hw*[]) {
1998	&cam_cc_ife_1_clk_src.clkr.hw,
1999	},
2000	.num_parents = 1,
2001	.flags = CLK_SET_RATE_PARENT,
2002	.ops = &clk_branch2_ops,
2003	},
2004	},
2005	};
2006
2007	static struct clk_branch cam_cc_cpas_ife_2_clk = {
2008	.halt_reg = 0x123e0,
2009	.halt_check = BRANCH_HALT,
2010	.clkr = {
2011	.enable_reg = 0x123e0,
2012	.enable_mask = BIT(0),
2013	.hw.init = &(const struct clk_init_data) {
2014	.name = "cam_cc_cpas_ife_2_clk",
2015	.parent_hws = (const struct clk_hw*[]) {
2016	&cam_cc_ife_2_clk_src.clkr.hw,
2017	},
2018	.num_parents = 1,
2019	.flags = CLK_SET_RATE_PARENT,
2020	.ops = &clk_branch2_ops,
2021	},
2022	},
2023	};
2024
2025	static struct clk_branch cam_cc_cpas_ife_lite_clk = {
2026	.halt_reg = 0x13138,
2027	.halt_check = BRANCH_HALT,
2028	.clkr = {
2029	.enable_reg = 0x13138,
2030	.enable_mask = BIT(0),
2031	.hw.init = &(const struct clk_init_data) {
2032	.name = "cam_cc_cpas_ife_lite_clk",
2033	.parent_hws = (const struct clk_hw*[]) {
2034	&cam_cc_ife_lite_clk_src.clkr.hw,
2035	},
2036	.num_parents = 1,
2037	.flags = CLK_SET_RATE_PARENT,
2038	.ops = &clk_branch2_ops,
2039	},
2040	},
2041	};
2042
2043	static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
2044	.halt_reg = 0x10504,
2045	.halt_check = BRANCH_HALT,
2046	.clkr = {
2047	.enable_reg = 0x10504,
2048	.enable_mask = BIT(0),
2049	.hw.init = &(const struct clk_init_data) {
2050	.name = "cam_cc_cpas_ipe_nps_clk",
2051	.parent_hws = (const struct clk_hw*[]) {
2052	&cam_cc_ipe_nps_clk_src.clkr.hw,
2053	},
2054	.num_parents = 1,
2055	.flags = CLK_SET_RATE_PARENT,
2056	.ops = &clk_branch2_ops,
2057	},
2058	},
2059	};
2060
2061	static struct clk_branch cam_cc_cpas_sbi_clk = {
2062	.halt_reg = 0x1054c,
2063	.halt_check = BRANCH_HALT,
2064	.clkr = {
2065	.enable_reg = 0x1054c,
2066	.enable_mask = BIT(0),
2067	.hw.init = &(const struct clk_init_data) {
2068	.name = "cam_cc_cpas_sbi_clk",
2069	.parent_hws = (const struct clk_hw*[]) {
2070	&cam_cc_ife_0_clk_src.clkr.hw,
2071	},
2072	.num_parents = 1,
2073	.flags = CLK_SET_RATE_PARENT,
2074	.ops = &clk_branch2_ops,
2075	},
2076	},
2077	};
2078
2079	static struct clk_branch cam_cc_cpas_sfe_0_clk = {
2080	.halt_reg = 0x133cc,
2081	.halt_check = BRANCH_HALT,
2082	.clkr = {
2083	.enable_reg = 0x133cc,
2084	.enable_mask = BIT(0),
2085	.hw.init = &(const struct clk_init_data) {
2086	.name = "cam_cc_cpas_sfe_0_clk",
2087	.parent_hws = (const struct clk_hw*[]) {
2088	&cam_cc_sfe_0_clk_src.clkr.hw,
2089	},
2090	.num_parents = 1,
2091	.flags = CLK_SET_RATE_PARENT,
2092	.ops = &clk_branch2_ops,
2093	},
2094	},
2095	};
2096
2097	static struct clk_branch cam_cc_cpas_sfe_1_clk = {
2098	.halt_reg = 0x1352c,
2099	.halt_check = BRANCH_HALT,
2100	.clkr = {
2101	.enable_reg = 0x1352c,
2102	.enable_mask = BIT(0),
2103	.hw.init = &(const struct clk_init_data) {
2104	.name = "cam_cc_cpas_sfe_1_clk",
2105	.parent_hws = (const struct clk_hw*[]) {
2106	&cam_cc_sfe_1_clk_src.clkr.hw,
2107	},
2108	.num_parents = 1,
2109	.flags = CLK_SET_RATE_PARENT,
2110	.ops = &clk_branch2_ops,
2111	},
2112	},
2113	};
2114
2115	static struct clk_branch cam_cc_cre_ahb_clk = {
2116	.halt_reg = 0x13670,
2117	.halt_check = BRANCH_HALT,
2118	.clkr = {
2119	.enable_reg = 0x13670,
2120	.enable_mask = BIT(0),
2121	.hw.init = &(const struct clk_init_data) {
2122	.name = "cam_cc_cre_ahb_clk",
2123	.parent_hws = (const struct clk_hw*[]) {
2124	&cam_cc_slow_ahb_clk_src.clkr.hw,
2125	},
2126	.num_parents = 1,
2127	.flags = CLK_SET_RATE_PARENT,
2128	.ops = &clk_branch2_ops,
2129	},
2130	},
2131	};
2132
2133	static struct clk_branch cam_cc_cre_clk = {
2134	.halt_reg = 0x13668,
2135	.halt_check = BRANCH_HALT,
2136	.clkr = {
2137	.enable_reg = 0x13668,
2138	.enable_mask = BIT(0),
2139	.hw.init = &(const struct clk_init_data) {
2140	.name = "cam_cc_cre_clk",
2141	.parent_hws = (const struct clk_hw*[]) {
2142	&cam_cc_cre_clk_src.clkr.hw,
2143	},
2144	.num_parents = 1,
2145	.flags = CLK_SET_RATE_PARENT,
2146	.ops = &clk_branch2_ops,
2147	},
2148	},
2149	};
2150
2151	static struct clk_branch cam_cc_csi0phytimer_clk = {
2152	.halt_reg = 0x15aac,
2153	.halt_check = BRANCH_HALT,
2154	.clkr = {
2155	.enable_reg = 0x15aac,
2156	.enable_mask = BIT(0),
2157	.hw.init = &(const struct clk_init_data) {
2158	.name = "cam_cc_csi0phytimer_clk",
2159	.parent_hws = (const struct clk_hw*[]) {
2160	&cam_cc_csi0phytimer_clk_src.clkr.hw,
2161	},
2162	.num_parents = 1,
2163	.flags = CLK_SET_RATE_PARENT,
2164	.ops = &clk_branch2_ops,
2165	},
2166	},
2167	};
2168
2169	static struct clk_branch cam_cc_csi1phytimer_clk = {
2170	.halt_reg = 0x15be4,
2171	.halt_check = BRANCH_HALT,
2172	.clkr = {
2173	.enable_reg = 0x15be4,
2174	.enable_mask = BIT(0),
2175	.hw.init = &(const struct clk_init_data) {
2176	.name = "cam_cc_csi1phytimer_clk",
2177	.parent_hws = (const struct clk_hw*[]) {
2178	&cam_cc_csi1phytimer_clk_src.clkr.hw,
2179	},
2180	.num_parents = 1,
2181	.flags = CLK_SET_RATE_PARENT,
2182	.ops = &clk_branch2_ops,
2183	},
2184	},
2185	};
2186
2187	static struct clk_branch cam_cc_csi2phytimer_clk = {
2188	.halt_reg = 0x15d18,
2189	.halt_check = BRANCH_HALT,
2190	.clkr = {
2191	.enable_reg = 0x15d18,
2192	.enable_mask = BIT(0),
2193	.hw.init = &(const struct clk_init_data) {
2194	.name = "cam_cc_csi2phytimer_clk",
2195	.parent_hws = (const struct clk_hw*[]) {
2196	&cam_cc_csi2phytimer_clk_src.clkr.hw,
2197	},
2198	.num_parents = 1,
2199	.flags = CLK_SET_RATE_PARENT,
2200	.ops = &clk_branch2_ops,
2201	},
2202	},
2203	};
2204
2205	static struct clk_branch cam_cc_csi3phytimer_clk = {
2206	.halt_reg = 0x15e4c,
2207	.halt_check = BRANCH_HALT,
2208	.clkr = {
2209	.enable_reg = 0x15e4c,
2210	.enable_mask = BIT(0),
2211	.hw.init = &(const struct clk_init_data) {
2212	.name = "cam_cc_csi3phytimer_clk",
2213	.parent_hws = (const struct clk_hw*[]) {
2214	&cam_cc_csi3phytimer_clk_src.clkr.hw,
2215	},
2216	.num_parents = 1,
2217	.flags = CLK_SET_RATE_PARENT,
2218	.ops = &clk_branch2_ops,
2219	},
2220	},
2221	};
2222
2223	static struct clk_branch cam_cc_csi4phytimer_clk = {
2224	.halt_reg = 0x15f80,
2225	.halt_check = BRANCH_HALT,
2226	.clkr = {
2227	.enable_reg = 0x15f80,
2228	.enable_mask = BIT(0),
2229	.hw.init = &(const struct clk_init_data) {
2230	.name = "cam_cc_csi4phytimer_clk",
2231	.parent_hws = (const struct clk_hw*[]) {
2232	&cam_cc_csi4phytimer_clk_src.clkr.hw,
2233	},
2234	.num_parents = 1,
2235	.flags = CLK_SET_RATE_PARENT,
2236	.ops = &clk_branch2_ops,
2237	},
2238	},
2239	};
2240
2241	static struct clk_branch cam_cc_csi5phytimer_clk = {
2242	.halt_reg = 0x160b4,
2243	.halt_check = BRANCH_HALT,
2244	.clkr = {
2245	.enable_reg = 0x160b4,
2246	.enable_mask = BIT(0),
2247	.hw.init = &(const struct clk_init_data) {
2248	.name = "cam_cc_csi5phytimer_clk",
2249	.parent_hws = (const struct clk_hw*[]) {
2250	&cam_cc_csi5phytimer_clk_src.clkr.hw,
2251	},
2252	.num_parents = 1,
2253	.flags = CLK_SET_RATE_PARENT,
2254	.ops = &clk_branch2_ops,
2255	},
2256	},
2257	};
2258
2259	static struct clk_branch cam_cc_csi6phytimer_clk = {
2260	.halt_reg = 0x161e8,
2261	.halt_check = BRANCH_HALT,
2262	.clkr = {
2263	.enable_reg = 0x161e8,
2264	.enable_mask = BIT(0),
2265	.hw.init = &(const struct clk_init_data) {
2266	.name = "cam_cc_csi6phytimer_clk",
2267	.parent_hws = (const struct clk_hw*[]) {
2268	&cam_cc_csi6phytimer_clk_src.clkr.hw,
2269	},
2270	.num_parents = 1,
2271	.flags = CLK_SET_RATE_PARENT,
2272	.ops = &clk_branch2_ops,
2273	},
2274	},
2275	};
2276
2277	static struct clk_branch cam_cc_csi7phytimer_clk = {
2278	.halt_reg = 0x1631c,
2279	.halt_check = BRANCH_HALT,
2280	.clkr = {
2281	.enable_reg = 0x1631c,
2282	.enable_mask = BIT(0),
2283	.hw.init = &(const struct clk_init_data) {
2284	.name = "cam_cc_csi7phytimer_clk",
2285	.parent_hws = (const struct clk_hw*[]) {
2286	&cam_cc_csi7phytimer_clk_src.clkr.hw,
2287	},
2288	.num_parents = 1,
2289	.flags = CLK_SET_RATE_PARENT,
2290	.ops = &clk_branch2_ops,
2291	},
2292	},
2293	};
2294
2295	static struct clk_branch cam_cc_csid_clk = {
2296	.halt_reg = 0x13dd4,
2297	.halt_check = BRANCH_HALT,
2298	.clkr = {
2299	.enable_reg = 0x13dd4,
2300	.enable_mask = BIT(0),
2301	.hw.init = &(const struct clk_init_data) {
2302	.name = "cam_cc_csid_clk",
2303	.parent_hws = (const struct clk_hw*[]) {
2304	&cam_cc_csid_clk_src.clkr.hw,
2305	},
2306	.num_parents = 1,
2307	.flags = CLK_SET_RATE_PARENT,
2308	.ops = &clk_branch2_ops,
2309	},
2310	},
2311	};
2312
2313	static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
2314	.halt_reg = 0x15ab4,
2315	.halt_check = BRANCH_HALT,
2316	.clkr = {
2317	.enable_reg = 0x15ab4,
2318	.enable_mask = BIT(0),
2319	.hw.init = &(const struct clk_init_data) {
2320	.name = "cam_cc_csid_csiphy_rx_clk",
2321	.parent_hws = (const struct clk_hw*[]) {
2322	&cam_cc_cphy_rx_clk_src.clkr.hw,
2323	},
2324	.num_parents = 1,
2325	.flags = CLK_SET_RATE_PARENT,
2326	.ops = &clk_branch2_ops,
2327	},
2328	},
2329	};
2330
2331	static struct clk_branch cam_cc_csiphy0_clk = {
2332	.halt_reg = 0x15ab0,
2333	.halt_check = BRANCH_HALT,
2334	.clkr = {
2335	.enable_reg = 0x15ab0,
2336	.enable_mask = BIT(0),
2337	.hw.init = &(const struct clk_init_data) {
2338	.name = "cam_cc_csiphy0_clk",
2339	.parent_hws = (const struct clk_hw*[]) {
2340	&cam_cc_cphy_rx_clk_src.clkr.hw,
2341	},
2342	.num_parents = 1,
2343	.flags = CLK_SET_RATE_PARENT,
2344	.ops = &clk_branch2_ops,
2345	},
2346	},
2347	};
2348
2349	static struct clk_branch cam_cc_csiphy1_clk = {
2350	.halt_reg = 0x15be8,
2351	.halt_check = BRANCH_HALT,
2352	.clkr = {
2353	.enable_reg = 0x15be8,
2354	.enable_mask = BIT(0),
2355	.hw.init = &(const struct clk_init_data) {
2356	.name = "cam_cc_csiphy1_clk",
2357	.parent_hws = (const struct clk_hw*[]) {
2358	&cam_cc_cphy_rx_clk_src.clkr.hw,
2359	},
2360	.num_parents = 1,
2361	.flags = CLK_SET_RATE_PARENT,
2362	.ops = &clk_branch2_ops,
2363	},
2364	},
2365	};
2366
2367	static struct clk_branch cam_cc_csiphy2_clk = {
2368	.halt_reg = 0x15d1c,
2369	.halt_check = BRANCH_HALT,
2370	.clkr = {
2371	.enable_reg = 0x15d1c,
2372	.enable_mask = BIT(0),
2373	.hw.init = &(const struct clk_init_data) {
2374	.name = "cam_cc_csiphy2_clk",
2375	.parent_hws = (const struct clk_hw*[]) {
2376	&cam_cc_cphy_rx_clk_src.clkr.hw,
2377	},
2378	.num_parents = 1,
2379	.flags = CLK_SET_RATE_PARENT,
2380	.ops = &clk_branch2_ops,
2381	},
2382	},
2383	};
2384
2385	static struct clk_branch cam_cc_csiphy3_clk = {
2386	.halt_reg = 0x15e50,
2387	.halt_check = BRANCH_HALT,
2388	.clkr = {
2389	.enable_reg = 0x15e50,
2390	.enable_mask = BIT(0),
2391	.hw.init = &(const struct clk_init_data) {
2392	.name = "cam_cc_csiphy3_clk",
2393	.parent_hws = (const struct clk_hw*[]) {
2394	&cam_cc_cphy_rx_clk_src.clkr.hw,
2395	},
2396	.num_parents = 1,
2397	.flags = CLK_SET_RATE_PARENT,
2398	.ops = &clk_branch2_ops,
2399	},
2400	},
2401	};
2402
2403	static struct clk_branch cam_cc_csiphy4_clk = {
2404	.halt_reg = 0x15f84,
2405	.halt_check = BRANCH_HALT,
2406	.clkr = {
2407	.enable_reg = 0x15f84,
2408	.enable_mask = BIT(0),
2409	.hw.init = &(const struct clk_init_data) {
2410	.name = "cam_cc_csiphy4_clk",
2411	.parent_hws = (const struct clk_hw*[]) {
2412	&cam_cc_cphy_rx_clk_src.clkr.hw,
2413	},
2414	.num_parents = 1,
2415	.flags = CLK_SET_RATE_PARENT,
2416	.ops = &clk_branch2_ops,
2417	},
2418	},
2419	};
2420
2421	static struct clk_branch cam_cc_csiphy5_clk = {
2422	.halt_reg = 0x160b8,
2423	.halt_check = BRANCH_HALT,
2424	.clkr = {
2425	.enable_reg = 0x160b8,
2426	.enable_mask = BIT(0),
2427	.hw.init = &(const struct clk_init_data) {
2428	.name = "cam_cc_csiphy5_clk",
2429	.parent_hws = (const struct clk_hw*[]) {
2430	&cam_cc_cphy_rx_clk_src.clkr.hw,
2431	},
2432	.num_parents = 1,
2433	.flags = CLK_SET_RATE_PARENT,
2434	.ops = &clk_branch2_ops,
2435	},
2436	},
2437	};
2438
2439	static struct clk_branch cam_cc_csiphy6_clk = {
2440	.halt_reg = 0x161ec,
2441	.halt_check = BRANCH_HALT,
2442	.clkr = {
2443	.enable_reg = 0x161ec,
2444	.enable_mask = BIT(0),
2445	.hw.init = &(const struct clk_init_data) {
2446	.name = "cam_cc_csiphy6_clk",
2447	.parent_hws = (const struct clk_hw*[]) {
2448	&cam_cc_cphy_rx_clk_src.clkr.hw,
2449	},
2450	.num_parents = 1,
2451	.flags = CLK_SET_RATE_PARENT,
2452	.ops = &clk_branch2_ops,
2453	},
2454	},
2455	};
2456
2457	static struct clk_branch cam_cc_csiphy7_clk = {
2458	.halt_reg = 0x16320,
2459	.halt_check = BRANCH_HALT,
2460	.clkr = {
2461	.enable_reg = 0x16320,
2462	.enable_mask = BIT(0),
2463	.hw.init = &(const struct clk_init_data) {
2464	.name = "cam_cc_csiphy7_clk",
2465	.parent_hws = (const struct clk_hw*[]) {
2466	&cam_cc_cphy_rx_clk_src.clkr.hw,
2467	},
2468	.num_parents = 1,
2469	.flags = CLK_SET_RATE_PARENT,
2470	.ops = &clk_branch2_ops,
2471	},
2472	},
2473	};
2474
2475	static struct clk_branch cam_cc_drv_ahb_clk = {
2476	.halt_reg = 0x142d8,
2477	.halt_check = BRANCH_HALT,
2478	.clkr = {
2479	.enable_reg = 0x142d8,
2480	.enable_mask = BIT(0),
2481	.hw.init = &(const struct clk_init_data) {
2482	.name = "cam_cc_drv_ahb_clk",
2483	.parent_hws = (const struct clk_hw*[]) {
2484	&cam_cc_slow_ahb_clk_src.clkr.hw,
2485	},
2486	.num_parents = 1,
2487	.flags = CLK_SET_RATE_PARENT,
2488	.ops = &clk_branch2_ops,
2489	},
2490	},
2491	};
2492
2493	static struct clk_branch cam_cc_drv_xo_clk = {
2494	.halt_reg = 0x142d4,
2495	.halt_check = BRANCH_HALT,
2496	.clkr = {
2497	.enable_reg = 0x142d4,
2498	.enable_mask = BIT(0),
2499	.hw.init = &(const struct clk_init_data) {
2500	.name = "cam_cc_drv_xo_clk",
2501	.parent_hws = (const struct clk_hw*[]) {
2502	&cam_cc_xo_clk_src.clkr.hw,
2503	},
2504	.num_parents = 1,
2505	.flags = CLK_SET_RATE_PARENT,
2506	.ops = &clk_branch2_ops,
2507	},
2508	},
2509	};
2510
2511	static struct clk_branch cam_cc_icp_ahb_clk = {
2512	.halt_reg = 0x138fc,
2513	.halt_check = BRANCH_HALT,
2514	.clkr = {
2515	.enable_reg = 0x138fc,
2516	.enable_mask = BIT(0),
2517	.hw.init = &(const struct clk_init_data) {
2518	.name = "cam_cc_icp_ahb_clk",
2519	.parent_hws = (const struct clk_hw*[]) {
2520	&cam_cc_slow_ahb_clk_src.clkr.hw,
2521	},
2522	.num_parents = 1,
2523	.flags = CLK_SET_RATE_PARENT,
2524	.ops = &clk_branch2_ops,
2525	},
2526	},
2527	};
2528
2529	static struct clk_branch cam_cc_icp_clk = {
2530	.halt_reg = 0x138f0,
2531	.halt_check = BRANCH_HALT,
2532	.clkr = {
2533	.enable_reg = 0x138f0,
2534	.enable_mask = BIT(0),
2535	.hw.init = &(const struct clk_init_data) {
2536	.name = "cam_cc_icp_clk",
2537	.parent_hws = (const struct clk_hw*[]) {
2538	&cam_cc_icp_clk_src.clkr.hw,
2539	},
2540	.num_parents = 1,
2541	.flags = CLK_SET_RATE_PARENT,
2542	.ops = &clk_branch2_ops,
2543	},
2544	},
2545	};
2546
2547	static struct clk_branch cam_cc_ife_0_clk = {
2548	.halt_reg = 0x11144,
2549	.halt_check = BRANCH_HALT,
2550	.clkr = {
2551	.enable_reg = 0x11144,
2552	.enable_mask = BIT(0),
2553	.hw.init = &(const struct clk_init_data) {
2554	.name = "cam_cc_ife_0_clk",
2555	.parent_hws = (const struct clk_hw*[]) {
2556	&cam_cc_ife_0_clk_src.clkr.hw,
2557	},
2558	.num_parents = 1,
2559	.flags = CLK_SET_RATE_PARENT,
2560	.ops = &clk_branch2_ops,
2561	},
2562	},
2563	};
2564
2565	static struct clk_branch cam_cc_ife_0_dsp_clk = {
2566	.halt_reg = 0x11280,
2567	.halt_check = BRANCH_HALT,
2568	.clkr = {
2569	.enable_reg = 0x11280,
2570	.enable_mask = BIT(0),
2571	.hw.init = &(const struct clk_init_data) {
2572	.name = "cam_cc_ife_0_dsp_clk",
2573	.parent_hws = (const struct clk_hw*[]) {
2574	&cam_cc_ife_0_dsp_clk_src.clkr.hw,
2575	},
2576	.num_parents = 1,
2577	.flags = CLK_SET_RATE_PARENT,
2578	.ops = &clk_branch2_ops,
2579	},
2580	},
2581	};
2582
2583	static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
2584	.halt_reg = 0x1128c,
2585	.halt_check = BRANCH_HALT,
2586	.clkr = {
2587	.enable_reg = 0x1128c,
2588	.enable_mask = BIT(0),
2589	.hw.init = &(const struct clk_init_data) {
2590	.name = "cam_cc_ife_0_fast_ahb_clk",
2591	.parent_hws = (const struct clk_hw*[]) {
2592	&cam_cc_fast_ahb_clk_src.clkr.hw,
2593	},
2594	.num_parents = 1,
2595	.flags = CLK_SET_RATE_PARENT,
2596	.ops = &clk_branch2_ops,
2597	},
2598	},
2599	};
2600
2601	static struct clk_branch cam_cc_ife_1_clk = {
2602	.halt_reg = 0x12144,
2603	.halt_check = BRANCH_HALT,
2604	.clkr = {
2605	.enable_reg = 0x12144,
2606	.enable_mask = BIT(0),
2607	.hw.init = &(const struct clk_init_data) {
2608	.name = "cam_cc_ife_1_clk",
2609	.parent_hws = (const struct clk_hw*[]) {
2610	&cam_cc_ife_1_clk_src.clkr.hw,
2611	},
2612	.num_parents = 1,
2613	.flags = CLK_SET_RATE_PARENT,
2614	.ops = &clk_branch2_ops,
2615	},
2616	},
2617	};
2618
2619	static struct clk_branch cam_cc_ife_1_dsp_clk = {
2620	.halt_reg = 0x12280,
2621	.halt_check = BRANCH_HALT,
2622	.clkr = {
2623	.enable_reg = 0x12280,
2624	.enable_mask = BIT(0),
2625	.hw.init = &(const struct clk_init_data) {
2626	.name = "cam_cc_ife_1_dsp_clk",
2627	.parent_hws = (const struct clk_hw*[]) {
2628	&cam_cc_ife_1_dsp_clk_src.clkr.hw,
2629	},
2630	.num_parents = 1,
2631	.flags = CLK_SET_RATE_PARENT,
2632	.ops = &clk_branch2_ops,
2633	},
2634	},
2635	};
2636
2637	static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
2638	.halt_reg = 0x1228c,
2639	.halt_check = BRANCH_HALT,
2640	.clkr = {
2641	.enable_reg = 0x1228c,
2642	.enable_mask = BIT(0),
2643	.hw.init = &(const struct clk_init_data) {
2644	.name = "cam_cc_ife_1_fast_ahb_clk",
2645	.parent_hws = (const struct clk_hw*[]) {
2646	&cam_cc_fast_ahb_clk_src.clkr.hw,
2647	},
2648	.num_parents = 1,
2649	.flags = CLK_SET_RATE_PARENT,
2650	.ops = &clk_branch2_ops,
2651	},
2652	},
2653	};
2654
2655	static struct clk_branch cam_cc_ife_2_clk = {
2656	.halt_reg = 0x123d4,
2657	.halt_check = BRANCH_HALT,
2658	.clkr = {
2659	.enable_reg = 0x123d4,
2660	.enable_mask = BIT(0),
2661	.hw.init = &(const struct clk_init_data) {
2662	.name = "cam_cc_ife_2_clk",
2663	.parent_hws = (const struct clk_hw*[]) {
2664	&cam_cc_ife_2_clk_src.clkr.hw,
2665	},
2666	.num_parents = 1,
2667	.flags = CLK_SET_RATE_PARENT,
2668	.ops = &clk_branch2_ops,
2669	},
2670	},
2671	};
2672
2673	static struct clk_branch cam_cc_ife_2_dsp_clk = {
2674	.halt_reg = 0x12510,
2675	.halt_check = BRANCH_HALT,
2676	.clkr = {
2677	.enable_reg = 0x12510,
2678	.enable_mask = BIT(0),
2679	.hw.init = &(const struct clk_init_data) {
2680	.name = "cam_cc_ife_2_dsp_clk",
2681	.parent_hws = (const struct clk_hw*[]) {
2682	&cam_cc_ife_2_dsp_clk_src.clkr.hw,
2683	},
2684	.num_parents = 1,
2685	.flags = CLK_SET_RATE_PARENT,
2686	.ops = &clk_branch2_ops,
2687	},
2688	},
2689	};
2690
2691	static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
2692	.halt_reg = 0x1251c,
2693	.halt_check = BRANCH_HALT,
2694	.clkr = {
2695	.enable_reg = 0x1251c,
2696	.enable_mask = BIT(0),
2697	.hw.init = &(const struct clk_init_data) {
2698	.name = "cam_cc_ife_2_fast_ahb_clk",
2699	.parent_hws = (const struct clk_hw*[]) {
2700	&cam_cc_fast_ahb_clk_src.clkr.hw,
2701	},
2702	.num_parents = 1,
2703	.flags = CLK_SET_RATE_PARENT,
2704	.ops = &clk_branch2_ops,
2705	},
2706	},
2707	};
2708
2709	static struct clk_branch cam_cc_ife_lite_ahb_clk = {
2710	.halt_reg = 0x13278,
2711	.halt_check = BRANCH_HALT,
2712	.clkr = {
2713	.enable_reg = 0x13278,
2714	.enable_mask = BIT(0),
2715	.hw.init = &(const struct clk_init_data) {
2716	.name = "cam_cc_ife_lite_ahb_clk",
2717	.parent_hws = (const struct clk_hw*[]) {
2718	&cam_cc_slow_ahb_clk_src.clkr.hw,
2719	},
2720	.num_parents = 1,
2721	.flags = CLK_SET_RATE_PARENT,
2722	.ops = &clk_branch2_ops,
2723	},
2724	},
2725	};
2726
2727	static struct clk_branch cam_cc_ife_lite_clk = {
2728	.halt_reg = 0x1312c,
2729	.halt_check = BRANCH_HALT,
2730	.clkr = {
2731	.enable_reg = 0x1312c,
2732	.enable_mask = BIT(0),
2733	.hw.init = &(const struct clk_init_data) {
2734	.name = "cam_cc_ife_lite_clk",
2735	.parent_hws = (const struct clk_hw*[]) {
2736	&cam_cc_ife_lite_clk_src.clkr.hw,
2737	},
2738	.num_parents = 1,
2739	.flags = CLK_SET_RATE_PARENT,
2740	.ops = &clk_branch2_ops,
2741	},
2742	},
2743	};
2744
2745	static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
2746	.halt_reg = 0x13274,
2747	.halt_check = BRANCH_HALT,
2748	.clkr = {
2749	.enable_reg = 0x13274,
2750	.enable_mask = BIT(0),
2751	.hw.init = &(const struct clk_init_data) {
2752	.name = "cam_cc_ife_lite_cphy_rx_clk",
2753	.parent_hws = (const struct clk_hw*[]) {
2754	&cam_cc_cphy_rx_clk_src.clkr.hw,
2755	},
2756	.num_parents = 1,
2757	.flags = CLK_SET_RATE_PARENT,
2758	.ops = &clk_branch2_ops,
2759	},
2760	},
2761	};
2762
2763	static struct clk_branch cam_cc_ife_lite_csid_clk = {
2764	.halt_reg = 0x13268,
2765	.halt_check = BRANCH_HALT,
2766	.clkr = {
2767	.enable_reg = 0x13268,
2768	.enable_mask = BIT(0),
2769	.hw.init = &(const struct clk_init_data) {
2770	.name = "cam_cc_ife_lite_csid_clk",
2771	.parent_hws = (const struct clk_hw*[]) {
2772	&cam_cc_ife_lite_csid_clk_src.clkr.hw,
2773	},
2774	.num_parents = 1,
2775	.flags = CLK_SET_RATE_PARENT,
2776	.ops = &clk_branch2_ops,
2777	},
2778	},
2779	};
2780
2781	static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
2782	.halt_reg = 0x1051c,
2783	.halt_check = BRANCH_HALT,
2784	.clkr = {
2785	.enable_reg = 0x1051c,
2786	.enable_mask = BIT(0),
2787	.hw.init = &(const struct clk_init_data) {
2788	.name = "cam_cc_ipe_nps_ahb_clk",
2789	.parent_hws = (const struct clk_hw*[]) {
2790	&cam_cc_slow_ahb_clk_src.clkr.hw,
2791	},
2792	.num_parents = 1,
2793	.flags = CLK_SET_RATE_PARENT,
2794	.ops = &clk_branch2_ops,
2795	},
2796	},
2797	};
2798
2799	static struct clk_branch cam_cc_ipe_nps_clk = {
2800	.halt_reg = 0x104f8,
2801	.halt_check = BRANCH_HALT,
2802	.clkr = {
2803	.enable_reg = 0x104f8,
2804	.enable_mask = BIT(0),
2805	.hw.init = &(const struct clk_init_data) {
2806	.name = "cam_cc_ipe_nps_clk",
2807	.parent_hws = (const struct clk_hw*[]) {
2808	&cam_cc_ipe_nps_clk_src.clkr.hw,
2809	},
2810	.num_parents = 1,
2811	.flags = CLK_SET_RATE_PARENT,
2812	.ops = &clk_branch2_ops,
2813	},
2814	},
2815	};
2816
2817	static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
2818	.halt_reg = 0x10520,
2819	.halt_check = BRANCH_HALT,
2820	.clkr = {
2821	.enable_reg = 0x10520,
2822	.enable_mask = BIT(0),
2823	.hw.init = &(const struct clk_init_data) {
2824	.name = "cam_cc_ipe_nps_fast_ahb_clk",
2825	.parent_hws = (const struct clk_hw*[]) {
2826	&cam_cc_fast_ahb_clk_src.clkr.hw,
2827	},
2828	.num_parents = 1,
2829	.flags = CLK_SET_RATE_PARENT,
2830	.ops = &clk_branch2_ops,
2831	},
2832	},
2833	};
2834
2835	static struct clk_branch cam_cc_ipe_pps_clk = {
2836	.halt_reg = 0x10508,
2837	.halt_check = BRANCH_HALT,
2838	.clkr = {
2839	.enable_reg = 0x10508,
2840	.enable_mask = BIT(0),
2841	.hw.init = &(const struct clk_init_data) {
2842	.name = "cam_cc_ipe_pps_clk",
2843	.parent_hws = (const struct clk_hw*[]) {
2844	&cam_cc_ipe_nps_clk_src.clkr.hw,
2845	},
2846	.num_parents = 1,
2847	.flags = CLK_SET_RATE_PARENT,
2848	.ops = &clk_branch2_ops,
2849	},
2850	},
2851	};
2852
2853	static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
2854	.halt_reg = 0x10524,
2855	.halt_check = BRANCH_HALT,
2856	.clkr = {
2857	.enable_reg = 0x10524,
2858	.enable_mask = BIT(0),
2859	.hw.init = &(const struct clk_init_data) {
2860	.name = "cam_cc_ipe_pps_fast_ahb_clk",
2861	.parent_hws = (const struct clk_hw*[]) {
2862	&cam_cc_fast_ahb_clk_src.clkr.hw,
2863	},
2864	.num_parents = 1,
2865	.flags = CLK_SET_RATE_PARENT,
2866	.ops = &clk_branch2_ops,
2867	},
2868	},
2869	};
2870
2871	static struct clk_branch cam_cc_jpeg_1_clk = {
2872	.halt_reg = 0x137ac,
2873	.halt_check = BRANCH_HALT,
2874	.clkr = {
2875	.enable_reg = 0x137ac,
2876	.enable_mask = BIT(0),
2877	.hw.init = &(const struct clk_init_data) {
2878	.name = "cam_cc_jpeg_1_clk",
2879	.parent_hws = (const struct clk_hw*[]) {
2880	&cam_cc_jpeg_clk_src.clkr.hw,
2881	},
2882	.num_parents = 1,
2883	.flags = CLK_SET_RATE_PARENT,
2884	.ops = &clk_branch2_ops,
2885	},
2886	},
2887	};
2888
2889	static struct clk_branch cam_cc_jpeg_clk = {
2890	.halt_reg = 0x137a0,
2891	.halt_check = BRANCH_HALT,
2892	.clkr = {
2893	.enable_reg = 0x137a0,
2894	.enable_mask = BIT(0),
2895	.hw.init = &(const struct clk_init_data) {
2896	.name = "cam_cc_jpeg_clk",
2897	.parent_hws = (const struct clk_hw*[]) {
2898	&cam_cc_jpeg_clk_src.clkr.hw,
2899	},
2900	.num_parents = 1,
2901	.flags = CLK_SET_RATE_PARENT,
2902	.ops = &clk_branch2_ops,
2903	},
2904	},
2905	};
2906
2907	static struct clk_branch cam_cc_mclk0_clk = {
2908	.halt_reg = 0x1512c,
2909	.halt_check = BRANCH_HALT,
2910	.clkr = {
2911	.enable_reg = 0x1512c,
2912	.enable_mask = BIT(0),
2913	.hw.init = &(const struct clk_init_data) {
2914	.name = "cam_cc_mclk0_clk",
2915	.parent_hws = (const struct clk_hw*[]) {
2916	&cam_cc_mclk0_clk_src.clkr.hw,
2917	},
2918	.num_parents = 1,
2919	.flags = CLK_SET_RATE_PARENT,
2920	.ops = &clk_branch2_ops,
2921	},
2922	},
2923	};
2924
2925	static struct clk_branch cam_cc_mclk1_clk = {
2926	.halt_reg = 0x1525c,
2927	.halt_check = BRANCH_HALT,
2928	.clkr = {
2929	.enable_reg = 0x1525c,
2930	.enable_mask = BIT(0),
2931	.hw.init = &(const struct clk_init_data) {
2932	.name = "cam_cc_mclk1_clk",
2933	.parent_hws = (const struct clk_hw*[]) {
2934	&cam_cc_mclk1_clk_src.clkr.hw,
2935	},
2936	.num_parents = 1,
2937	.flags = CLK_SET_RATE_PARENT,
2938	.ops = &clk_branch2_ops,
2939	},
2940	},
2941	};
2942
2943	static struct clk_branch cam_cc_mclk2_clk = {
2944	.halt_reg = 0x1538c,
2945	.halt_check = BRANCH_HALT,
2946	.clkr = {
2947	.enable_reg = 0x1538c,
2948	.enable_mask = BIT(0),
2949	.hw.init = &(const struct clk_init_data) {
2950	.name = "cam_cc_mclk2_clk",
2951	.parent_hws = (const struct clk_hw*[]) {
2952	&cam_cc_mclk2_clk_src.clkr.hw,
2953	},
2954	.num_parents = 1,
2955	.flags = CLK_SET_RATE_PARENT,
2956	.ops = &clk_branch2_ops,
2957	},
2958	},
2959	};
2960
2961	static struct clk_branch cam_cc_mclk3_clk = {
2962	.halt_reg = 0x154bc,
2963	.halt_check = BRANCH_HALT,
2964	.clkr = {
2965	.enable_reg = 0x154bc,
2966	.enable_mask = BIT(0),
2967	.hw.init = &(const struct clk_init_data) {
2968	.name = "cam_cc_mclk3_clk",
2969	.parent_hws = (const struct clk_hw*[]) {
2970	&cam_cc_mclk3_clk_src.clkr.hw,
2971	},
2972	.num_parents = 1,
2973	.flags = CLK_SET_RATE_PARENT,
2974	.ops = &clk_branch2_ops,
2975	},
2976	},
2977	};
2978
2979	static struct clk_branch cam_cc_mclk4_clk = {
2980	.halt_reg = 0x155ec,
2981	.halt_check = BRANCH_HALT,
2982	.clkr = {
2983	.enable_reg = 0x155ec,
2984	.enable_mask = BIT(0),
2985	.hw.init = &(const struct clk_init_data) {
2986	.name = "cam_cc_mclk4_clk",
2987	.parent_hws = (const struct clk_hw*[]) {
2988	&cam_cc_mclk4_clk_src.clkr.hw,
2989	},
2990	.num_parents = 1,
2991	.flags = CLK_SET_RATE_PARENT,
2992	.ops = &clk_branch2_ops,
2993	},
2994	},
2995	};
2996
2997	static struct clk_branch cam_cc_mclk5_clk = {
2998	.halt_reg = 0x1571c,
2999	.halt_check = BRANCH_HALT,
3000	.clkr = {
3001	.enable_reg = 0x1571c,
3002	.enable_mask = BIT(0),
3003	.hw.init = &(const struct clk_init_data) {
3004	.name = "cam_cc_mclk5_clk",
3005	.parent_hws = (const struct clk_hw*[]) {
3006	&cam_cc_mclk5_clk_src.clkr.hw,
3007	},
3008	.num_parents = 1,
3009	.flags = CLK_SET_RATE_PARENT,
3010	.ops = &clk_branch2_ops,
3011	},
3012	},
3013	};
3014
3015	static struct clk_branch cam_cc_mclk6_clk = {
3016	.halt_reg = 0x1584c,
3017	.halt_check = BRANCH_HALT,
3018	.clkr = {
3019	.enable_reg = 0x1584c,
3020	.enable_mask = BIT(0),
3021	.hw.init = &(const struct clk_init_data) {
3022	.name = "cam_cc_mclk6_clk",
3023	.parent_hws = (const struct clk_hw*[]) {
3024	&cam_cc_mclk6_clk_src.clkr.hw,
3025	},
3026	.num_parents = 1,
3027	.flags = CLK_SET_RATE_PARENT,
3028	.ops = &clk_branch2_ops,
3029	},
3030	},
3031	};
3032
3033	static struct clk_branch cam_cc_mclk7_clk = {
3034	.halt_reg = 0x1597c,
3035	.halt_check = BRANCH_HALT,
3036	.clkr = {
3037	.enable_reg = 0x1597c,
3038	.enable_mask = BIT(0),
3039	.hw.init = &(const struct clk_init_data) {
3040	.name = "cam_cc_mclk7_clk",
3041	.parent_hws = (const struct clk_hw*[]) {
3042	&cam_cc_mclk7_clk_src.clkr.hw,
3043	},
3044	.num_parents = 1,
3045	.flags = CLK_SET_RATE_PARENT,
3046	.ops = &clk_branch2_ops,
3047	},
3048	},
3049	};
3050
3051	static struct clk_branch cam_cc_qdss_debug_clk = {
3052	.halt_reg = 0x14050,
3053	.halt_check = BRANCH_HALT,
3054	.clkr = {
3055	.enable_reg = 0x14050,
3056	.enable_mask = BIT(0),
3057	.hw.init = &(const struct clk_init_data) {
3058	.name = "cam_cc_qdss_debug_clk",
3059	.parent_hws = (const struct clk_hw*[]) {
3060	&cam_cc_qdss_debug_clk_src.clkr.hw,
3061	},
3062	.num_parents = 1,
3063	.flags = CLK_SET_RATE_PARENT,
3064	.ops = &clk_branch2_ops,
3065	},
3066	},
3067	};
3068
3069	static struct clk_branch cam_cc_qdss_debug_xo_clk = {
3070	.halt_reg = 0x14054,
3071	.halt_check = BRANCH_HALT,
3072	.clkr = {
3073	.enable_reg = 0x14054,
3074	.enable_mask = BIT(0),
3075	.hw.init = &(const struct clk_init_data) {
3076	.name = "cam_cc_qdss_debug_xo_clk",
3077	.parent_hws = (const struct clk_hw*[]) {
3078	&cam_cc_xo_clk_src.clkr.hw,
3079	},
3080	.num_parents = 1,
3081	.flags = CLK_SET_RATE_PARENT,
3082	.ops = &clk_branch2_ops,
3083	},
3084	},
3085	};
3086
3087	static struct clk_branch cam_cc_sbi_clk = {
3088	.halt_reg = 0x10540,
3089	.halt_check = BRANCH_HALT,
3090	.clkr = {
3091	.enable_reg = 0x10540,
3092	.enable_mask = BIT(0),
3093	.hw.init = &(const struct clk_init_data) {
3094	.name = "cam_cc_sbi_clk",
3095	.parent_hws = (const struct clk_hw*[]) {
3096	&cam_cc_ife_0_clk_src.clkr.hw,
3097	},
3098	.num_parents = 1,
3099	.flags = CLK_SET_RATE_PARENT,
3100	.ops = &clk_branch2_ops,
3101	},
3102	},
3103	};
3104
3105	static struct clk_branch cam_cc_sbi_fast_ahb_clk = {
3106	.halt_reg = 0x10550,
3107	.halt_check = BRANCH_HALT,
3108	.clkr = {
3109	.enable_reg = 0x10550,
3110	.enable_mask = BIT(0),
3111	.hw.init = &(const struct clk_init_data) {
3112	.name = "cam_cc_sbi_fast_ahb_clk",
3113	.parent_hws = (const struct clk_hw*[]) {
3114	&cam_cc_fast_ahb_clk_src.clkr.hw,
3115	},
3116	.num_parents = 1,
3117	.flags = CLK_SET_RATE_PARENT,
3118	.ops = &clk_branch2_ops,
3119	},
3120	},
3121	};
3122
3123	static struct clk_branch cam_cc_sfe_0_clk = {
3124	.halt_reg = 0x133c0,
3125	.halt_check = BRANCH_HALT,
3126	.clkr = {
3127	.enable_reg = 0x133c0,
3128	.enable_mask = BIT(0),
3129	.hw.init = &(const struct clk_init_data) {
3130	.name = "cam_cc_sfe_0_clk",
3131	.parent_hws = (const struct clk_hw*[]) {
3132	&cam_cc_sfe_0_clk_src.clkr.hw,
3133	},
3134	.num_parents = 1,
3135	.flags = CLK_SET_RATE_PARENT,
3136	.ops = &clk_branch2_ops,
3137	},
3138	},
3139	};
3140
3141	static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
3142	.halt_reg = 0x133d8,
3143	.halt_check = BRANCH_HALT,
3144	.clkr = {
3145	.enable_reg = 0x133d8,
3146	.enable_mask = BIT(0),
3147	.hw.init = &(const struct clk_init_data) {
3148	.name = "cam_cc_sfe_0_fast_ahb_clk",
3149	.parent_hws = (const struct clk_hw*[]) {
3150	&cam_cc_fast_ahb_clk_src.clkr.hw,
3151	},
3152	.num_parents = 1,
3153	.flags = CLK_SET_RATE_PARENT,
3154	.ops = &clk_branch2_ops,
3155	},
3156	},
3157	};
3158
3159	static struct clk_branch cam_cc_sfe_1_clk = {
3160	.halt_reg = 0x13520,
3161	.halt_check = BRANCH_HALT,
3162	.clkr = {
3163	.enable_reg = 0x13520,
3164	.enable_mask = BIT(0),
3165	.hw.init = &(const struct clk_init_data) {
3166	.name = "cam_cc_sfe_1_clk",
3167	.parent_hws = (const struct clk_hw*[]) {
3168	&cam_cc_sfe_1_clk_src.clkr.hw,
3169	},
3170	.num_parents = 1,
3171	.flags = CLK_SET_RATE_PARENT,
3172	.ops = &clk_branch2_ops,
3173	},
3174	},
3175	};
3176
3177	static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
3178	.halt_reg = 0x13538,
3179	.halt_check = BRANCH_HALT,
3180	.clkr = {
3181	.enable_reg = 0x13538,
3182	.enable_mask = BIT(0),
3183	.hw.init = &(const struct clk_init_data) {
3184	.name = "cam_cc_sfe_1_fast_ahb_clk",
3185	.parent_hws = (const struct clk_hw*[]) {
3186	&cam_cc_fast_ahb_clk_src.clkr.hw,
3187	},
3188	.num_parents = 1,
3189	.flags = CLK_SET_RATE_PARENT,
3190	.ops = &clk_branch2_ops,
3191	},
3192	},
3193	};
3194
3195	static struct gdsc cam_cc_bps_gdsc = {
3196	.gdscr = 0x10004,
3197	.en_rest_wait_val = 0x2,
3198	.en_few_wait_val = 0x2,
3199	.clk_dis_wait_val = 0xf,
3200	.pd = {
3201	.name = "cam_cc_bps_gdsc",
3202	},
3203	.pwrsts = PWRSTS_OFF_ON,
3204	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3205	};
3206
3207	static struct gdsc cam_cc_ife_0_gdsc = {
3208	.gdscr = 0x11004,
3209	.en_rest_wait_val = 0x2,
3210	.en_few_wait_val = 0x2,
3211	.clk_dis_wait_val = 0xf,
3212	.pd = {
3213	.name = "cam_cc_ife_0_gdsc",
3214	},
3215	.pwrsts = PWRSTS_OFF_ON,
3216	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3217	};
3218
3219	static struct gdsc cam_cc_ife_1_gdsc = {
3220	.gdscr = 0x12004,
3221	.en_rest_wait_val = 0x2,
3222	.en_few_wait_val = 0x2,
3223	.clk_dis_wait_val = 0xf,
3224	.pd = {
3225	.name = "cam_cc_ife_1_gdsc",
3226	},
3227	.pwrsts = PWRSTS_OFF_ON,
3228	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3229	};
3230
3231	static struct gdsc cam_cc_ife_2_gdsc = {
3232	.gdscr = 0x12294,
3233	.en_rest_wait_val = 0x2,
3234	.en_few_wait_val = 0x2,
3235	.clk_dis_wait_val = 0xf,
3236	.pd = {
3237	.name = "cam_cc_ife_2_gdsc",
3238	},
3239	.pwrsts = PWRSTS_OFF_ON,
3240	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3241	};
3242
3243	static struct gdsc cam_cc_ipe_0_gdsc = {
3244	.gdscr = 0x103b8,
3245	.en_rest_wait_val = 0x2,
3246	.en_few_wait_val = 0x2,
3247	.clk_dis_wait_val = 0xf,
3248	.pd = {
3249	.name = "cam_cc_ipe_0_gdsc",
3250	},
3251	.pwrsts = PWRSTS_OFF_ON,
3252	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3253	};
3254
3255	static struct gdsc cam_cc_sbi_gdsc = {
3256	.gdscr = 0x1052c,
3257	.en_rest_wait_val = 0x2,
3258	.en_few_wait_val = 0x2,
3259	.clk_dis_wait_val = 0xf,
3260	.pd = {
3261	.name = "cam_cc_sbi_gdsc",
3262	},
3263	.pwrsts = PWRSTS_OFF_ON,
3264	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3265	};
3266
3267	static struct gdsc cam_cc_sfe_0_gdsc = {
3268	.gdscr = 0x13280,
3269	.en_rest_wait_val = 0x2,
3270	.en_few_wait_val = 0x2,
3271	.clk_dis_wait_val = 0xf,
3272	.pd = {
3273	.name = "cam_cc_sfe_0_gdsc",
3274	},
3275	.pwrsts = PWRSTS_OFF_ON,
3276	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3277	};
3278
3279	static struct gdsc cam_cc_sfe_1_gdsc = {
3280	.gdscr = 0x133e0,
3281	.en_rest_wait_val = 0x2,
3282	.en_few_wait_val = 0x2,
3283	.clk_dis_wait_val = 0xf,
3284	.pd = {
3285	.name = "cam_cc_sfe_1_gdsc",
3286	},
3287	.pwrsts = PWRSTS_OFF_ON,
3288	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3289	};
3290
3291	static struct gdsc cam_cc_titan_top_gdsc = {
3292	.gdscr = 0x14058,
3293	.en_rest_wait_val = 0x2,
3294	.en_few_wait_val = 0x2,
3295	.clk_dis_wait_val = 0xf,
3296	.pd = {
3297	.name = "cam_cc_titan_top_gdsc",
3298	},
3299	.pwrsts = PWRSTS_OFF_ON,
3300	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3301	};
3302
3303	static struct clk_regmap *cam_cc_sm8550_clocks[] = {
3304	[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
3305	[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
3306	[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
3307	[CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
3308	[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
3309	[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
3310	[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
3311	[CAM_CC_CAMNOC_XO_CLK] = &cam_cc_camnoc_xo_clk.clkr,
3312	[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
3313	[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
3314	[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
3315	[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
3316	[CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr,
3317	[CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr,
3318	[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
3319	[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
3320	[CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
3321	[CAM_CC_CPAS_CRE_CLK] = &cam_cc_cpas_cre_clk.clkr,
3322	[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
3323	[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
3324	[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
3325	[CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
3326	[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
3327	[CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
3328	[CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
3329	[CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
3330	[CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
3331	[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
3332	[CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr,
3333	[CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr,
3334	[CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr,
3335	[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
3336	[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
3337	[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
3338	[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
3339	[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
3340	[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
3341	[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
3342	[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
3343	[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
3344	[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
3345	[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
3346	[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
3347	[CAM_CC_CSI6PHYTIMER_CLK] = &cam_cc_csi6phytimer_clk.clkr,
3348	[CAM_CC_CSI6PHYTIMER_CLK_SRC] = &cam_cc_csi6phytimer_clk_src.clkr,
3349	[CAM_CC_CSI7PHYTIMER_CLK] = &cam_cc_csi7phytimer_clk.clkr,
3350	[CAM_CC_CSI7PHYTIMER_CLK_SRC] = &cam_cc_csi7phytimer_clk_src.clkr,
3351	[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
3352	[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
3353	[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
3354	[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
3355	[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
3356	[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
3357	[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
3358	[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
3359	[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
3360	[CAM_CC_CSIPHY6_CLK] = &cam_cc_csiphy6_clk.clkr,
3361	[CAM_CC_CSIPHY7_CLK] = &cam_cc_csiphy7_clk.clkr,
3362	[CAM_CC_DRV_AHB_CLK] = &cam_cc_drv_ahb_clk.clkr,
3363	[CAM_CC_DRV_XO_CLK] = &cam_cc_drv_xo_clk.clkr,
3364	[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
3365	[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
3366	[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
3367	[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
3368	[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
3369	[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
3370	[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
3371	[CAM_CC_IFE_0_DSP_CLK_SRC] = &cam_cc_ife_0_dsp_clk_src.clkr,
3372	[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
3373	[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
3374	[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
3375	[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
3376	[CAM_CC_IFE_1_DSP_CLK_SRC] = &cam_cc_ife_1_dsp_clk_src.clkr,
3377	[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
3378	[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
3379	[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
3380	[CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
3381	[CAM_CC_IFE_2_DSP_CLK_SRC] = &cam_cc_ife_2_dsp_clk_src.clkr,
3382	[CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
3383	[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
3384	[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
3385	[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
3386	[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
3387	[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
3388	[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
3389	[CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
3390	[CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
3391	[CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
3392	[CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
3393	[CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
3394	[CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
3395	[CAM_CC_JPEG_1_CLK] = &cam_cc_jpeg_1_clk.clkr,
3396	[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
3397	[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
3398	[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
3399	[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
3400	[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
3401	[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
3402	[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
3403	[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
3404	[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
3405	[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
3406	[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
3407	[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
3408	[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
3409	[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
3410	[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
3411	[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
3412	[CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
3413	[CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
3414	[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
3415	[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
3416	[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
3417	[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
3418	[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
3419	[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
3420	[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
3421	[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
3422	[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
3423	[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
3424	[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
3425	[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
3426	[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
3427	[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
3428	[CAM_CC_PLL7] = &cam_cc_pll7.clkr,
3429	[CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
3430	[CAM_CC_PLL8] = &cam_cc_pll8.clkr,
3431	[CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
3432	[CAM_CC_PLL9] = &cam_cc_pll9.clkr,
3433	[CAM_CC_PLL9_OUT_EVEN] = &cam_cc_pll9_out_even.clkr,
3434	[CAM_CC_PLL10] = &cam_cc_pll10.clkr,
3435	[CAM_CC_PLL10_OUT_EVEN] = &cam_cc_pll10_out_even.clkr,
3436	[CAM_CC_PLL11] = &cam_cc_pll11.clkr,
3437	[CAM_CC_PLL11_OUT_EVEN] = &cam_cc_pll11_out_even.clkr,
3438	[CAM_CC_PLL12] = &cam_cc_pll12.clkr,
3439	[CAM_CC_PLL12_OUT_EVEN] = &cam_cc_pll12_out_even.clkr,
3440	[CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
3441	[CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
3442	[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
3443	[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
3444	[CAM_CC_SBI_FAST_AHB_CLK] = &cam_cc_sbi_fast_ahb_clk.clkr,
3445	[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
3446	[CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
3447	[CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
3448	[CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
3449	[CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
3450	[CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
3451	[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
3452	[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
3453	[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
3454	};
3455
3456	static struct gdsc *cam_cc_sm8550_gdscs[] = {
3457	[CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc,
3458	[CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc,
3459	[CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc,
3460	[CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc,
3461	[CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc,
3462	[CAM_CC_SBI_GDSC] = &cam_cc_sbi_gdsc,
3463	[CAM_CC_SFE_0_GDSC] = &cam_cc_sfe_0_gdsc,
3464	[CAM_CC_SFE_1_GDSC] = &cam_cc_sfe_1_gdsc,
3465	[CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
3466	};
3467
3468	static const struct qcom_reset_map cam_cc_sm8550_resets[] = {
3469	[CAM_CC_BPS_BCR] = { 0x10000 },
3470	[CAM_CC_DRV_BCR] = { 0x142d0 },
3471	[CAM_CC_ICP_BCR] = { 0x137c0 },
3472	[CAM_CC_IFE_0_BCR] = { 0x11000 },
3473	[CAM_CC_IFE_1_BCR] = { 0x12000 },
3474	[CAM_CC_IFE_2_BCR] = { 0x12290 },
3475	[CAM_CC_IPE_0_BCR] = { 0x103b4 },
3476	[CAM_CC_QDSS_DEBUG_BCR] = { 0x13f20 },
3477	[CAM_CC_SBI_BCR] = { 0x10528 },
3478	[CAM_CC_SFE_0_BCR] = { 0x1327c },
3479	[CAM_CC_SFE_1_BCR] = { 0x133dc },
3480	};
3481
3482	static const struct regmap_config cam_cc_sm8550_regmap_config = {
3483	.reg_bits = 32,
3484	.reg_stride = 4,
3485	.val_bits = 32,
3486	.max_register = 0x16320,
3487	.fast_io = true,
3488	};
3489
3490	static const struct qcom_cc_desc cam_cc_sm8550_desc = {
3491	.config = &cam_cc_sm8550_regmap_config,
3492	.clks = cam_cc_sm8550_clocks,
3493	.num_clks = ARRAY_SIZE(cam_cc_sm8550_clocks),
3494	.resets = cam_cc_sm8550_resets,
3495	.num_resets = ARRAY_SIZE(cam_cc_sm8550_resets),
3496	.gdscs = cam_cc_sm8550_gdscs,
3497	.num_gdscs = ARRAY_SIZE(cam_cc_sm8550_gdscs),
3498	};
3499
3500	static const struct of_device_id cam_cc_sm8550_match_table[] = {
3501	{ .compatible = "qcom,sm8550-camcc" },
3502	{ }
3503	};
3504	MODULE_DEVICE_TABLE(of, cam_cc_sm8550_match_table);
3505
3506	static int cam_cc_sm8550_probe(struct platform_device *pdev)
3507	{
3508	struct regmap *regmap;
3509	int ret;
3510
3511	ret = devm_pm_runtime_enable(dev: &pdev->dev);
3512	if (ret)
3513	return ret;
3514
3515	ret = pm_runtime_resume_and_get(dev: &pdev->dev);
3516	if (ret)
3517	return ret;
3518
3519	regmap = qcom_cc_map(pdev, desc: &cam_cc_sm8550_desc);
3520	if (IS_ERR(ptr: regmap)) {
3521	pm_runtime_put(dev: &pdev->dev);
3522	return PTR_ERR(ptr: regmap);
3523	}
3524
3525	clk_lucid_ole_pll_configure(pll: &cam_cc_pll0, regmap, config: &cam_cc_pll0_config);
3526	clk_lucid_ole_pll_configure(pll: &cam_cc_pll1, regmap, config: &cam_cc_pll1_config);
3527	clk_rivian_evo_pll_configure(pll: &cam_cc_pll2, regmap, config: &cam_cc_pll2_config);
3528	clk_lucid_ole_pll_configure(pll: &cam_cc_pll3, regmap, config: &cam_cc_pll3_config);
3529	clk_lucid_ole_pll_configure(pll: &cam_cc_pll4, regmap, config: &cam_cc_pll4_config);
3530	clk_lucid_ole_pll_configure(pll: &cam_cc_pll5, regmap, config: &cam_cc_pll5_config);
3531	clk_lucid_ole_pll_configure(pll: &cam_cc_pll6, regmap, config: &cam_cc_pll6_config);
3532	clk_lucid_ole_pll_configure(pll: &cam_cc_pll7, regmap, config: &cam_cc_pll7_config);
3533	clk_lucid_ole_pll_configure(pll: &cam_cc_pll8, regmap, config: &cam_cc_pll8_config);
3534	clk_lucid_ole_pll_configure(pll: &cam_cc_pll9, regmap, config: &cam_cc_pll9_config);
3535	clk_lucid_ole_pll_configure(pll: &cam_cc_pll10, regmap, config: &cam_cc_pll10_config);
3536	clk_lucid_ole_pll_configure(pll: &cam_cc_pll11, regmap, config: &cam_cc_pll11_config);
3537	clk_lucid_ole_pll_configure(pll: &cam_cc_pll12, regmap, config: &cam_cc_pll12_config);
3538
3539	/* Keep some clocks always-on */
3540	qcom_branch_set_clk_en(regmap, cbcr: 0x1419c); /* CAM_CC_GDSC_CLK */
3541	qcom_branch_set_clk_en(regmap, cbcr: 0x142cc); /* CAM_CC_SLEEP_CLK */
3542
3543	ret = qcom_cc_really_probe(dev: &pdev->dev, desc: &cam_cc_sm8550_desc, regmap);
3544
3545	pm_runtime_put(dev: &pdev->dev);
3546
3547	return ret;
3548	}
3549
3550	static struct platform_driver cam_cc_sm8550_driver = {
3551	.probe = cam_cc_sm8550_probe,
3552	.driver = {
3553	.name = "cam_cc-sm8550",
3554	.of_match_table = cam_cc_sm8550_match_table,
3555	},
3556	};
3557
3558	module_platform_driver(cam_cc_sm8550_driver);
3559
3560	MODULE_DESCRIPTION("QTI CAMCC SM8550 Driver");
3561	MODULE_LICENSE("GPL");
3562