1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#include <linux/kernel.h>
8#include <linux/export.h>
9#include <linux/clk-provider.h>
10#include <linux/regmap.h>
11#include <linux/delay.h>
12
13#include "clk-alpha-pll.h"
14#include "common.h"
15
16#define PLL_MODE(p) ((p)->offset + 0x0)
17# define PLL_OUTCTRL BIT(0)
18# define PLL_BYPASSNL BIT(1)
19# define PLL_RESET_N BIT(2)
20# define PLL_OFFLINE_REQ BIT(7)
21# define PLL_LOCK_COUNT_SHIFT 8
22# define PLL_LOCK_COUNT_MASK 0x3f
23# define PLL_BIAS_COUNT_SHIFT 14
24# define PLL_BIAS_COUNT_MASK 0x3f
25# define PLL_VOTE_FSM_ENA BIT(20)
26# define PLL_FSM_ENA BIT(20)
27# define PLL_VOTE_FSM_RESET BIT(21)
28# define PLL_UPDATE BIT(22)
29# define PLL_UPDATE_BYPASS BIT(23)
30# define PLL_FSM_LEGACY_MODE BIT(24)
31# define PLL_OFFLINE_ACK BIT(28)
32# define ALPHA_PLL_ACK_LATCH BIT(29)
33# define PLL_ACTIVE_FLAG BIT(30)
34# define PLL_LOCK_DET BIT(31)
35
36#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37#define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
40
41#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
42# define PLL_POST_DIV_SHIFT 8
43# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
44# define PLL_ALPHA_EN BIT(24)
45# define PLL_ALPHA_MODE BIT(25)
46# define PLL_VCO_SHIFT 20
47# define PLL_VCO_MASK 0x3
48
49#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
50#define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
51
52#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
53#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
54#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
55#define PLL_CONFIG_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U2])
56#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
57#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
58#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
59#define PLL_TEST_CTL_U2(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U2])
60#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
61#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
62#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
63
64const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
65 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
66 [PLL_OFF_L_VAL] = 0x04,
67 [PLL_OFF_ALPHA_VAL] = 0x08,
68 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
69 [PLL_OFF_USER_CTL] = 0x10,
70 [PLL_OFF_USER_CTL_U] = 0x14,
71 [PLL_OFF_CONFIG_CTL] = 0x18,
72 [PLL_OFF_TEST_CTL] = 0x1c,
73 [PLL_OFF_TEST_CTL_U] = 0x20,
74 [PLL_OFF_STATUS] = 0x24,
75 },
76 [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
77 [PLL_OFF_L_VAL] = 0x04,
78 [PLL_OFF_ALPHA_VAL] = 0x08,
79 [PLL_OFF_USER_CTL] = 0x10,
80 [PLL_OFF_CONFIG_CTL] = 0x14,
81 [PLL_OFF_CONFIG_CTL_U] = 0x18,
82 [PLL_OFF_TEST_CTL] = 0x1c,
83 [PLL_OFF_TEST_CTL_U] = 0x20,
84 [PLL_OFF_STATUS] = 0x24,
85 },
86 [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
87 [PLL_OFF_L_VAL] = 0x04,
88 [PLL_OFF_ALPHA_VAL] = 0x08,
89 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
90 [PLL_OFF_USER_CTL] = 0x10,
91 [PLL_OFF_CONFIG_CTL] = 0x18,
92 [PLL_OFF_TEST_CTL] = 0x1c,
93 [PLL_OFF_STATUS] = 0x24,
94 },
95 [CLK_ALPHA_PLL_TYPE_FABIA] = {
96 [PLL_OFF_L_VAL] = 0x04,
97 [PLL_OFF_USER_CTL] = 0x0c,
98 [PLL_OFF_USER_CTL_U] = 0x10,
99 [PLL_OFF_CONFIG_CTL] = 0x14,
100 [PLL_OFF_CONFIG_CTL_U] = 0x18,
101 [PLL_OFF_TEST_CTL] = 0x1c,
102 [PLL_OFF_TEST_CTL_U] = 0x20,
103 [PLL_OFF_STATUS] = 0x24,
104 [PLL_OFF_OPMODE] = 0x2c,
105 [PLL_OFF_FRAC] = 0x38,
106 },
107 [CLK_ALPHA_PLL_TYPE_TRION] = {
108 [PLL_OFF_L_VAL] = 0x04,
109 [PLL_OFF_CAL_L_VAL] = 0x08,
110 [PLL_OFF_USER_CTL] = 0x0c,
111 [PLL_OFF_USER_CTL_U] = 0x10,
112 [PLL_OFF_USER_CTL_U1] = 0x14,
113 [PLL_OFF_CONFIG_CTL] = 0x18,
114 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
115 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
116 [PLL_OFF_TEST_CTL] = 0x24,
117 [PLL_OFF_TEST_CTL_U] = 0x28,
118 [PLL_OFF_TEST_CTL_U1] = 0x2c,
119 [PLL_OFF_STATUS] = 0x30,
120 [PLL_OFF_OPMODE] = 0x38,
121 [PLL_OFF_ALPHA_VAL] = 0x40,
122 },
123 [CLK_ALPHA_PLL_TYPE_AGERA] = {
124 [PLL_OFF_L_VAL] = 0x04,
125 [PLL_OFF_ALPHA_VAL] = 0x08,
126 [PLL_OFF_USER_CTL] = 0x0c,
127 [PLL_OFF_CONFIG_CTL] = 0x10,
128 [PLL_OFF_CONFIG_CTL_U] = 0x14,
129 [PLL_OFF_TEST_CTL] = 0x18,
130 [PLL_OFF_TEST_CTL_U] = 0x1c,
131 [PLL_OFF_STATUS] = 0x2c,
132 },
133 [CLK_ALPHA_PLL_TYPE_ZONDA] = {
134 [PLL_OFF_L_VAL] = 0x04,
135 [PLL_OFF_ALPHA_VAL] = 0x08,
136 [PLL_OFF_USER_CTL] = 0x0c,
137 [PLL_OFF_CONFIG_CTL] = 0x10,
138 [PLL_OFF_CONFIG_CTL_U] = 0x14,
139 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
140 [PLL_OFF_TEST_CTL] = 0x1c,
141 [PLL_OFF_TEST_CTL_U] = 0x20,
142 [PLL_OFF_TEST_CTL_U1] = 0x24,
143 [PLL_OFF_OPMODE] = 0x28,
144 [PLL_OFF_STATUS] = 0x38,
145 },
146 [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
147 [PLL_OFF_OPMODE] = 0x04,
148 [PLL_OFF_STATUS] = 0x0c,
149 [PLL_OFF_L_VAL] = 0x10,
150 [PLL_OFF_ALPHA_VAL] = 0x14,
151 [PLL_OFF_USER_CTL] = 0x18,
152 [PLL_OFF_USER_CTL_U] = 0x1c,
153 [PLL_OFF_CONFIG_CTL] = 0x20,
154 [PLL_OFF_CONFIG_CTL_U] = 0x24,
155 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
156 [PLL_OFF_TEST_CTL] = 0x2c,
157 [PLL_OFF_TEST_CTL_U] = 0x30,
158 [PLL_OFF_TEST_CTL_U1] = 0x34,
159 },
160 [CLK_ALPHA_PLL_TYPE_LUCID_OLE] = {
161 [PLL_OFF_OPMODE] = 0x04,
162 [PLL_OFF_STATE] = 0x08,
163 [PLL_OFF_STATUS] = 0x0c,
164 [PLL_OFF_L_VAL] = 0x10,
165 [PLL_OFF_ALPHA_VAL] = 0x14,
166 [PLL_OFF_USER_CTL] = 0x18,
167 [PLL_OFF_USER_CTL_U] = 0x1c,
168 [PLL_OFF_CONFIG_CTL] = 0x20,
169 [PLL_OFF_CONFIG_CTL_U] = 0x24,
170 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
171 [PLL_OFF_TEST_CTL] = 0x2c,
172 [PLL_OFF_TEST_CTL_U] = 0x30,
173 [PLL_OFF_TEST_CTL_U1] = 0x34,
174 [PLL_OFF_TEST_CTL_U2] = 0x38,
175 },
176 [CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
177 [PLL_OFF_OPMODE] = 0x04,
178 [PLL_OFF_STATUS] = 0x0c,
179 [PLL_OFF_L_VAL] = 0x10,
180 [PLL_OFF_USER_CTL] = 0x14,
181 [PLL_OFF_USER_CTL_U] = 0x18,
182 [PLL_OFF_CONFIG_CTL] = 0x1c,
183 [PLL_OFF_CONFIG_CTL_U] = 0x20,
184 [PLL_OFF_CONFIG_CTL_U1] = 0x24,
185 [PLL_OFF_TEST_CTL] = 0x28,
186 [PLL_OFF_TEST_CTL_U] = 0x2c,
187 },
188 [CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
189 [PLL_OFF_L_VAL] = 0x04,
190 [PLL_OFF_ALPHA_VAL] = 0x08,
191 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
192 [PLL_OFF_TEST_CTL] = 0x10,
193 [PLL_OFF_TEST_CTL_U] = 0x14,
194 [PLL_OFF_USER_CTL] = 0x18,
195 [PLL_OFF_USER_CTL_U] = 0x1c,
196 [PLL_OFF_CONFIG_CTL] = 0x20,
197 [PLL_OFF_STATUS] = 0x24,
198 },
199 [CLK_ALPHA_PLL_TYPE_BRAMMO_EVO] = {
200 [PLL_OFF_L_VAL] = 0x04,
201 [PLL_OFF_ALPHA_VAL] = 0x08,
202 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
203 [PLL_OFF_TEST_CTL] = 0x10,
204 [PLL_OFF_TEST_CTL_U] = 0x14,
205 [PLL_OFF_USER_CTL] = 0x18,
206 [PLL_OFF_CONFIG_CTL] = 0x1C,
207 [PLL_OFF_STATUS] = 0x20,
208 },
209 [CLK_ALPHA_PLL_TYPE_STROMER] = {
210 [PLL_OFF_L_VAL] = 0x08,
211 [PLL_OFF_ALPHA_VAL] = 0x10,
212 [PLL_OFF_ALPHA_VAL_U] = 0x14,
213 [PLL_OFF_USER_CTL] = 0x18,
214 [PLL_OFF_USER_CTL_U] = 0x1c,
215 [PLL_OFF_CONFIG_CTL] = 0x20,
216 [PLL_OFF_CONFIG_CTL_U] = 0xff,
217 [PLL_OFF_TEST_CTL] = 0x30,
218 [PLL_OFF_TEST_CTL_U] = 0x34,
219 [PLL_OFF_STATUS] = 0x28,
220 },
221 [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
222 [PLL_OFF_L_VAL] = 0x04,
223 [PLL_OFF_USER_CTL] = 0x08,
224 [PLL_OFF_USER_CTL_U] = 0x0c,
225 [PLL_OFF_CONFIG_CTL] = 0x10,
226 [PLL_OFF_TEST_CTL] = 0x14,
227 [PLL_OFF_TEST_CTL_U] = 0x18,
228 [PLL_OFF_STATUS] = 0x1c,
229 [PLL_OFF_ALPHA_VAL] = 0x24,
230 [PLL_OFF_ALPHA_VAL_U] = 0x28,
231 },
232 [CLK_ALPHA_PLL_TYPE_ZONDA_OLE] = {
233 [PLL_OFF_L_VAL] = 0x04,
234 [PLL_OFF_ALPHA_VAL] = 0x08,
235 [PLL_OFF_USER_CTL] = 0x0c,
236 [PLL_OFF_USER_CTL_U] = 0x10,
237 [PLL_OFF_CONFIG_CTL] = 0x14,
238 [PLL_OFF_CONFIG_CTL_U] = 0x18,
239 [PLL_OFF_CONFIG_CTL_U1] = 0x1c,
240 [PLL_OFF_CONFIG_CTL_U2] = 0x20,
241 [PLL_OFF_TEST_CTL] = 0x24,
242 [PLL_OFF_TEST_CTL_U] = 0x28,
243 [PLL_OFF_TEST_CTL_U1] = 0x2c,
244 [PLL_OFF_OPMODE] = 0x30,
245 [PLL_OFF_STATUS] = 0x3c,
246 },
247};
248EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
249
250/*
251 * Even though 40 bits are present, use only 32 for ease of calculation.
252 */
253#define ALPHA_REG_BITWIDTH 40
254#define ALPHA_REG_16BIT_WIDTH 16
255#define ALPHA_BITWIDTH 32U
256#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
257
258#define ALPHA_PLL_STATUS_REG_SHIFT 8
259
260#define PLL_HUAYRA_M_WIDTH 8
261#define PLL_HUAYRA_M_SHIFT 8
262#define PLL_HUAYRA_M_MASK 0xff
263#define PLL_HUAYRA_N_SHIFT 0
264#define PLL_HUAYRA_N_MASK 0xff
265#define PLL_HUAYRA_ALPHA_WIDTH 16
266
267#define PLL_STANDBY 0x0
268#define PLL_RUN 0x1
269#define PLL_OUT_MASK 0x7
270#define PLL_RATE_MARGIN 500
271
272/* TRION PLL specific settings and offsets */
273#define TRION_PLL_CAL_VAL 0x44
274#define TRION_PCAL_DONE BIT(26)
275
276/* LUCID PLL specific settings and offsets */
277#define LUCID_PCAL_DONE BIT(27)
278
279/* LUCID 5LPE PLL specific settings and offsets */
280#define LUCID_5LPE_PCAL_DONE BIT(11)
281#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)
282#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
283#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
284
285/* LUCID EVO PLL specific settings and offsets */
286#define LUCID_EVO_PCAL_NOT_DONE BIT(8)
287#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
288#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
289#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
290#define LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT 24
291
292/* ZONDA PLL specific */
293#define ZONDA_PLL_OUT_MASK 0xf
294#define ZONDA_STAY_IN_CFA BIT(16)
295#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
296
297#define pll_alpha_width(p) \
298 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
299 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
300
301#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
302
303#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
304 struct clk_alpha_pll, clkr)
305
306#define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
307 struct clk_alpha_pll_postdiv, clkr)
308
309static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
310 const char *action)
311{
312 u32 val;
313 int count;
314 int ret;
315 const char *name = clk_hw_get_name(hw: &pll->clkr.hw);
316
317 ret = regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
318 if (ret)
319 return ret;
320
321 for (count = 200; count > 0; count--) {
322 ret = regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
323 if (ret)
324 return ret;
325 if (inverse && !(val & mask))
326 return 0;
327 else if ((val & mask) == mask)
328 return 0;
329
330 udelay(1);
331 }
332
333 WARN(1, "%s failed to %s!\n", name, action);
334 return -ETIMEDOUT;
335}
336
337#define wait_for_pll_enable_active(pll) \
338 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
339
340#define wait_for_pll_enable_lock(pll) \
341 wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
342
343#define wait_for_zonda_pll_freq_lock(pll) \
344 wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
345
346#define wait_for_pll_disable(pll) \
347 wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
348
349#define wait_for_pll_offline(pll) \
350 wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
351
352#define wait_for_pll_update(pll) \
353 wait_for_pll(pll, PLL_UPDATE, 1, "update")
354
355#define wait_for_pll_update_ack_set(pll) \
356 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
357
358#define wait_for_pll_update_ack_clear(pll) \
359 wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
360
361static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
362 unsigned int val)
363{
364 if (val)
365 regmap_write(map: regmap, reg, val);
366}
367
368void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
369 const struct alpha_pll_config *config)
370{
371 u32 val, mask;
372
373 regmap_write(map: regmap, PLL_L_VAL(pll), val: config->l);
374 regmap_write(map: regmap, PLL_ALPHA_VAL(pll), val: config->alpha);
375 regmap_write(map: regmap, PLL_CONFIG_CTL(pll), val: config->config_ctl_val);
376
377 if (pll_has_64bit_config(pll))
378 regmap_write(map: regmap, PLL_CONFIG_CTL_U(pll),
379 val: config->config_ctl_hi_val);
380
381 if (pll_alpha_width(pll) > 32)
382 regmap_write(map: regmap, PLL_ALPHA_VAL_U(pll), val: config->alpha_hi);
383
384 val = config->main_output_mask;
385 val |= config->aux_output_mask;
386 val |= config->aux2_output_mask;
387 val |= config->early_output_mask;
388 val |= config->pre_div_val;
389 val |= config->post_div_val;
390 val |= config->vco_val;
391 val |= config->alpha_en_mask;
392 val |= config->alpha_mode_mask;
393
394 mask = config->main_output_mask;
395 mask |= config->aux_output_mask;
396 mask |= config->aux2_output_mask;
397 mask |= config->early_output_mask;
398 mask |= config->pre_div_mask;
399 mask |= config->post_div_mask;
400 mask |= config->vco_mask;
401
402 regmap_update_bits(map: regmap, PLL_USER_CTL(pll), mask, val);
403
404 if (config->test_ctl_mask)
405 regmap_update_bits(map: regmap, PLL_TEST_CTL(pll),
406 mask: config->test_ctl_mask,
407 val: config->test_ctl_val);
408 else
409 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
410 val: config->test_ctl_val);
411
412 if (config->test_ctl_hi_mask)
413 regmap_update_bits(map: regmap, PLL_TEST_CTL_U(pll),
414 mask: config->test_ctl_hi_mask,
415 val: config->test_ctl_hi_val);
416 else
417 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
418 val: config->test_ctl_hi_val);
419
420 if (pll->flags & SUPPORTS_FSM_MODE)
421 qcom_pll_set_fsm_mode(m: regmap, PLL_MODE(pll), bias_count: 6, lock_count: 0);
422}
423EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
424
425static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
426{
427 int ret;
428 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
429 u32 val;
430
431 ret = regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
432 if (ret)
433 return ret;
434
435 val |= PLL_FSM_ENA;
436
437 if (pll->flags & SUPPORTS_OFFLINE_REQ)
438 val &= ~PLL_OFFLINE_REQ;
439
440 ret = regmap_write(map: pll->clkr.regmap, PLL_MODE(pll), val);
441 if (ret)
442 return ret;
443
444 /* Make sure enable request goes through before waiting for update */
445 mb();
446
447 return wait_for_pll_enable_active(pll);
448}
449
450static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
451{
452 int ret;
453 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
454 u32 val;
455
456 ret = regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
457 if (ret)
458 return;
459
460 if (pll->flags & SUPPORTS_OFFLINE_REQ) {
461 ret = regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll),
462 PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
463 if (ret)
464 return;
465
466 ret = wait_for_pll_offline(pll);
467 if (ret)
468 return;
469 }
470
471 /* Disable hwfsm */
472 ret = regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll),
473 PLL_FSM_ENA, val: 0);
474 if (ret)
475 return;
476
477 wait_for_pll_disable(pll);
478}
479
480static int pll_is_enabled(struct clk_hw *hw, u32 mask)
481{
482 int ret;
483 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
484 u32 val;
485
486 ret = regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
487 if (ret)
488 return ret;
489
490 return !!(val & mask);
491}
492
493static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
494{
495 return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
496}
497
498static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
499{
500 return pll_is_enabled(hw, PLL_LOCK_DET);
501}
502
503static int clk_alpha_pll_enable(struct clk_hw *hw)
504{
505 int ret;
506 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
507 u32 val, mask;
508
509 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
510 ret = regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
511 if (ret)
512 return ret;
513
514 /* If in FSM mode, just vote for it */
515 if (val & PLL_VOTE_FSM_ENA) {
516 ret = clk_enable_regmap(hw);
517 if (ret)
518 return ret;
519 return wait_for_pll_enable_active(pll);
520 }
521
522 /* Skip if already enabled */
523 if ((val & mask) == mask)
524 return 0;
525
526 ret = regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll),
527 PLL_BYPASSNL, PLL_BYPASSNL);
528 if (ret)
529 return ret;
530
531 /*
532 * H/W requires a 5us delay between disabling the bypass and
533 * de-asserting the reset.
534 */
535 mb();
536 udelay(5);
537
538 ret = regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll),
539 PLL_RESET_N, PLL_RESET_N);
540 if (ret)
541 return ret;
542
543 ret = wait_for_pll_enable_lock(pll);
544 if (ret)
545 return ret;
546
547 ret = regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll),
548 PLL_OUTCTRL, PLL_OUTCTRL);
549
550 /* Ensure that the write above goes through before returning. */
551 mb();
552 return ret;
553}
554
555static void clk_alpha_pll_disable(struct clk_hw *hw)
556{
557 int ret;
558 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
559 u32 val, mask;
560
561 ret = regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
562 if (ret)
563 return;
564
565 /* If in FSM mode, just unvote it */
566 if (val & PLL_VOTE_FSM_ENA) {
567 clk_disable_regmap(hw);
568 return;
569 }
570
571 mask = PLL_OUTCTRL;
572 regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), mask, val: 0);
573
574 /* Delay of 2 output clock ticks required until output is disabled */
575 mb();
576 udelay(1);
577
578 mask = PLL_RESET_N | PLL_BYPASSNL;
579 regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), mask, val: 0);
580}
581
582static unsigned long
583alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
584{
585 return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
586}
587
588static unsigned long
589alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
590 u32 alpha_width)
591{
592 u64 remainder;
593 u64 quotient;
594
595 quotient = rate;
596 remainder = do_div(quotient, prate);
597 *l = quotient;
598
599 if (!remainder) {
600 *a = 0;
601 return rate;
602 }
603
604 /* Upper ALPHA_BITWIDTH bits of Alpha */
605 quotient = remainder << ALPHA_SHIFT(alpha_width);
606
607 remainder = do_div(quotient, prate);
608
609 if (remainder)
610 quotient++;
611
612 *a = quotient;
613 return alpha_pll_calc_rate(prate, l: *l, a: *a, alpha_width);
614}
615
616static const struct pll_vco *
617alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
618{
619 const struct pll_vco *v = pll->vco_table;
620 const struct pll_vco *end = v + pll->num_vco;
621
622 for (; v < end; v++)
623 if (rate >= v->min_freq && rate <= v->max_freq)
624 return v;
625
626 return NULL;
627}
628
629static unsigned long
630clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
631{
632 u32 l, low, high, ctl;
633 u64 a = 0, prate = parent_rate;
634 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
635 u32 alpha_width = pll_alpha_width(pll);
636
637 regmap_read(map: pll->clkr.regmap, PLL_L_VAL(pll), val: &l);
638
639 regmap_read(map: pll->clkr.regmap, PLL_USER_CTL(pll), val: &ctl);
640 if (ctl & PLL_ALPHA_EN) {
641 regmap_read(map: pll->clkr.regmap, PLL_ALPHA_VAL(pll), val: &low);
642 if (alpha_width > 32) {
643 regmap_read(map: pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
644 val: &high);
645 a = (u64)high << 32 | low;
646 } else {
647 a = low & GENMASK(alpha_width - 1, 0);
648 }
649
650 if (alpha_width > ALPHA_BITWIDTH)
651 a >>= alpha_width - ALPHA_BITWIDTH;
652 }
653
654 return alpha_pll_calc_rate(prate, l, a, alpha_width);
655}
656
657
658static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
659{
660 int ret;
661 u32 mode;
662
663 regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &mode);
664
665 /* Latch the input to the PLL */
666 regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
667 PLL_UPDATE);
668
669 /* Wait for 2 reference cycle before checking ACK bit */
670 udelay(1);
671
672 /*
673 * PLL will latch the new L, Alpha and freq control word.
674 * PLL will respond by raising PLL_ACK_LATCH output when new programming
675 * has been latched in and PLL is being updated. When
676 * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
677 * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
678 */
679 if (mode & PLL_UPDATE_BYPASS) {
680 ret = wait_for_pll_update_ack_set(pll);
681 if (ret)
682 return ret;
683
684 regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, val: 0);
685 } else {
686 ret = wait_for_pll_update(pll);
687 if (ret)
688 return ret;
689 }
690
691 ret = wait_for_pll_update_ack_clear(pll);
692 if (ret)
693 return ret;
694
695 /* Wait for PLL output to stabilize */
696 udelay(10);
697
698 return 0;
699}
700
701static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
702 int (*is_enabled)(struct clk_hw *))
703{
704 if (!is_enabled(&pll->clkr.hw) ||
705 !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
706 return 0;
707
708 return __clk_alpha_pll_update_latch(pll);
709}
710
711static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
712 unsigned long prate,
713 int (*is_enabled)(struct clk_hw *))
714{
715 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
716 const struct pll_vco *vco;
717 u32 l, alpha_width = pll_alpha_width(pll);
718 u64 a;
719
720 rate = alpha_pll_round_rate(rate, prate, l: &l, a: &a, alpha_width);
721 vco = alpha_pll_find_vco(pll, rate);
722 if (pll->vco_table && !vco) {
723 pr_err("%s: alpha pll not in a valid vco range\n",
724 clk_hw_get_name(hw));
725 return -EINVAL;
726 }
727
728 regmap_write(map: pll->clkr.regmap, PLL_L_VAL(pll), val: l);
729
730 if (alpha_width > ALPHA_BITWIDTH)
731 a <<= alpha_width - ALPHA_BITWIDTH;
732
733 if (alpha_width > 32)
734 regmap_write(map: pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), val: a >> 32);
735
736 regmap_write(map: pll->clkr.regmap, PLL_ALPHA_VAL(pll), val: a);
737
738 if (vco) {
739 regmap_update_bits(map: pll->clkr.regmap, PLL_USER_CTL(pll),
740 PLL_VCO_MASK << PLL_VCO_SHIFT,
741 val: vco->val << PLL_VCO_SHIFT);
742 }
743
744 regmap_update_bits(map: pll->clkr.regmap, PLL_USER_CTL(pll),
745 PLL_ALPHA_EN, PLL_ALPHA_EN);
746
747 return clk_alpha_pll_update_latch(pll, is_enabled);
748}
749
750static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
751 unsigned long prate)
752{
753 return __clk_alpha_pll_set_rate(hw, rate, prate,
754 is_enabled: clk_alpha_pll_is_enabled);
755}
756
757static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
758 unsigned long prate)
759{
760 return __clk_alpha_pll_set_rate(hw, rate, prate,
761 is_enabled: clk_alpha_pll_hwfsm_is_enabled);
762}
763
764static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
765 unsigned long *prate)
766{
767 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
768 u32 l, alpha_width = pll_alpha_width(pll);
769 u64 a;
770 unsigned long min_freq, max_freq;
771
772 rate = alpha_pll_round_rate(rate, prate: *prate, l: &l, a: &a, alpha_width);
773 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
774 return rate;
775
776 min_freq = pll->vco_table[0].min_freq;
777 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
778
779 return clamp(rate, min_freq, max_freq);
780}
781
782static unsigned long
783alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
784{
785 /*
786 * a contains 16 bit alpha_val in two’s complement number in the range
787 * of [-0.5, 0.5).
788 */
789 if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
790 l -= 1;
791
792 return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
793}
794
795static unsigned long
796alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
797 u32 *l, u32 *a)
798{
799 u64 remainder;
800 u64 quotient;
801
802 quotient = rate;
803 remainder = do_div(quotient, prate);
804 *l = quotient;
805
806 if (!remainder) {
807 *a = 0;
808 return rate;
809 }
810
811 quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
812 remainder = do_div(quotient, prate);
813
814 if (remainder)
815 quotient++;
816
817 /*
818 * alpha_val should be in two’s complement number in the range
819 * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
820 * since alpha value will be subtracted in this case.
821 */
822 if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
823 *l += 1;
824
825 *a = quotient;
826 return alpha_huayra_pll_calc_rate(prate, l: *l, a: *a);
827}
828
829static unsigned long
830alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
831{
832 u64 rate = parent_rate, tmp;
833 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
834 u32 l, alpha = 0, ctl, alpha_m, alpha_n;
835
836 regmap_read(map: pll->clkr.regmap, PLL_L_VAL(pll), val: &l);
837 regmap_read(map: pll->clkr.regmap, PLL_USER_CTL(pll), val: &ctl);
838
839 if (ctl & PLL_ALPHA_EN) {
840 regmap_read(map: pll->clkr.regmap, PLL_ALPHA_VAL(pll), val: &alpha);
841 /*
842 * Depending upon alpha_mode, it can be treated as M/N value or
843 * as a two’s complement number. When alpha_mode=1,
844 * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
845 *
846 * Fout=FIN*(L+(M/N))
847 *
848 * M is a signed number (-128 to 127) and N is unsigned
849 * (0 to 255). M/N has to be within +/-0.5.
850 *
851 * When alpha_mode=0, it is a two’s complement number in the
852 * range [-0.5, 0.5).
853 *
854 * Fout=FIN*(L+(alpha_val)/2^16)
855 *
856 * where alpha_val is two’s complement number.
857 */
858 if (!(ctl & PLL_ALPHA_MODE))
859 return alpha_huayra_pll_calc_rate(prate: rate, l, a: alpha);
860
861 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
862 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
863
864 rate *= l;
865 tmp = parent_rate;
866 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
867 alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
868 tmp *= alpha_m;
869 do_div(tmp, alpha_n);
870 rate -= tmp;
871 } else {
872 tmp *= alpha_m;
873 do_div(tmp, alpha_n);
874 rate += tmp;
875 }
876
877 return rate;
878 }
879
880 return alpha_huayra_pll_calc_rate(prate: rate, l, a: alpha);
881}
882
883static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
884 unsigned long prate)
885{
886 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
887 u32 l, a, ctl, cur_alpha = 0;
888
889 rate = alpha_huayra_pll_round_rate(rate, prate, l: &l, a: &a);
890
891 regmap_read(map: pll->clkr.regmap, PLL_USER_CTL(pll), val: &ctl);
892
893 if (ctl & PLL_ALPHA_EN)
894 regmap_read(map: pll->clkr.regmap, PLL_ALPHA_VAL(pll), val: &cur_alpha);
895
896 /*
897 * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
898 * without having to go through the power on sequence.
899 */
900 if (clk_alpha_pll_is_enabled(hw)) {
901 if (cur_alpha != a) {
902 pr_err("%s: clock needs to be gated\n",
903 clk_hw_get_name(hw));
904 return -EBUSY;
905 }
906
907 regmap_write(map: pll->clkr.regmap, PLL_L_VAL(pll), val: l);
908 /* Ensure that the write above goes to detect L val change. */
909 mb();
910 return wait_for_pll_enable_lock(pll);
911 }
912
913 regmap_write(map: pll->clkr.regmap, PLL_L_VAL(pll), val: l);
914 regmap_write(map: pll->clkr.regmap, PLL_ALPHA_VAL(pll), val: a);
915
916 if (a == 0)
917 regmap_update_bits(map: pll->clkr.regmap, PLL_USER_CTL(pll),
918 PLL_ALPHA_EN, val: 0x0);
919 else
920 regmap_update_bits(map: pll->clkr.regmap, PLL_USER_CTL(pll),
921 PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
922
923 return 0;
924}
925
926static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
927 unsigned long *prate)
928{
929 u32 l, a;
930
931 return alpha_huayra_pll_round_rate(rate, prate: *prate, l: &l, a: &a);
932}
933
934static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
935 struct regmap *regmap)
936{
937 u32 mode_val, opmode_val;
938 int ret;
939
940 ret = regmap_read(map: regmap, PLL_MODE(pll), val: &mode_val);
941 ret |= regmap_read(map: regmap, PLL_OPMODE(pll), val: &opmode_val);
942 if (ret)
943 return 0;
944
945 return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
946}
947
948static int clk_trion_pll_is_enabled(struct clk_hw *hw)
949{
950 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
951
952 return trion_pll_is_enabled(pll, regmap: pll->clkr.regmap);
953}
954
955static int clk_trion_pll_enable(struct clk_hw *hw)
956{
957 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
958 struct regmap *regmap = pll->clkr.regmap;
959 u32 val;
960 int ret;
961
962 ret = regmap_read(map: regmap, PLL_MODE(pll), val: &val);
963 if (ret)
964 return ret;
965
966 /* If in FSM mode, just vote for it */
967 if (val & PLL_VOTE_FSM_ENA) {
968 ret = clk_enable_regmap(hw);
969 if (ret)
970 return ret;
971 return wait_for_pll_enable_active(pll);
972 }
973
974 /* Set operation mode to RUN */
975 regmap_write(map: regmap, PLL_OPMODE(pll), PLL_RUN);
976
977 ret = wait_for_pll_enable_lock(pll);
978 if (ret)
979 return ret;
980
981 /* Enable the PLL outputs */
982 ret = regmap_update_bits(map: regmap, PLL_USER_CTL(pll),
983 PLL_OUT_MASK, PLL_OUT_MASK);
984 if (ret)
985 return ret;
986
987 /* Enable the global PLL outputs */
988 return regmap_update_bits(map: regmap, PLL_MODE(pll),
989 PLL_OUTCTRL, PLL_OUTCTRL);
990}
991
992static void clk_trion_pll_disable(struct clk_hw *hw)
993{
994 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
995 struct regmap *regmap = pll->clkr.regmap;
996 u32 val;
997 int ret;
998
999 ret = regmap_read(map: regmap, PLL_MODE(pll), val: &val);
1000 if (ret)
1001 return;
1002
1003 /* If in FSM mode, just unvote it */
1004 if (val & PLL_VOTE_FSM_ENA) {
1005 clk_disable_regmap(hw);
1006 return;
1007 }
1008
1009 /* Disable the global PLL output */
1010 ret = regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL, val: 0);
1011 if (ret)
1012 return;
1013
1014 /* Disable the PLL outputs */
1015 ret = regmap_update_bits(map: regmap, PLL_USER_CTL(pll),
1016 PLL_OUT_MASK, val: 0);
1017 if (ret)
1018 return;
1019
1020 /* Place the PLL mode in STANDBY */
1021 regmap_write(map: regmap, PLL_OPMODE(pll), PLL_STANDBY);
1022 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1023}
1024
1025static unsigned long
1026clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1027{
1028 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1029 u32 l, frac, alpha_width = pll_alpha_width(pll);
1030
1031 regmap_read(map: pll->clkr.regmap, PLL_L_VAL(pll), val: &l);
1032 regmap_read(map: pll->clkr.regmap, PLL_ALPHA_VAL(pll), val: &frac);
1033
1034 return alpha_pll_calc_rate(prate: parent_rate, l, a: frac, alpha_width);
1035}
1036
1037const struct clk_ops clk_alpha_pll_fixed_ops = {
1038 .enable = clk_alpha_pll_enable,
1039 .disable = clk_alpha_pll_disable,
1040 .is_enabled = clk_alpha_pll_is_enabled,
1041 .recalc_rate = clk_alpha_pll_recalc_rate,
1042};
1043EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
1044
1045const struct clk_ops clk_alpha_pll_ops = {
1046 .enable = clk_alpha_pll_enable,
1047 .disable = clk_alpha_pll_disable,
1048 .is_enabled = clk_alpha_pll_is_enabled,
1049 .recalc_rate = clk_alpha_pll_recalc_rate,
1050 .round_rate = clk_alpha_pll_round_rate,
1051 .set_rate = clk_alpha_pll_set_rate,
1052};
1053EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
1054
1055const struct clk_ops clk_alpha_pll_huayra_ops = {
1056 .enable = clk_alpha_pll_enable,
1057 .disable = clk_alpha_pll_disable,
1058 .is_enabled = clk_alpha_pll_is_enabled,
1059 .recalc_rate = alpha_pll_huayra_recalc_rate,
1060 .round_rate = alpha_pll_huayra_round_rate,
1061 .set_rate = alpha_pll_huayra_set_rate,
1062};
1063EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
1064
1065const struct clk_ops clk_alpha_pll_hwfsm_ops = {
1066 .enable = clk_alpha_pll_hwfsm_enable,
1067 .disable = clk_alpha_pll_hwfsm_disable,
1068 .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
1069 .recalc_rate = clk_alpha_pll_recalc_rate,
1070 .round_rate = clk_alpha_pll_round_rate,
1071 .set_rate = clk_alpha_pll_hwfsm_set_rate,
1072};
1073EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
1074
1075const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
1076 .enable = clk_trion_pll_enable,
1077 .disable = clk_trion_pll_disable,
1078 .is_enabled = clk_trion_pll_is_enabled,
1079 .recalc_rate = clk_trion_pll_recalc_rate,
1080 .round_rate = clk_alpha_pll_round_rate,
1081};
1082EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
1083
1084static unsigned long
1085clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1086{
1087 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1088 u32 ctl;
1089
1090 regmap_read(map: pll->clkr.regmap, PLL_USER_CTL(pll), val: &ctl);
1091
1092 ctl >>= PLL_POST_DIV_SHIFT;
1093 ctl &= PLL_POST_DIV_MASK(pll);
1094
1095 return parent_rate >> fls(x: ctl);
1096}
1097
1098static const struct clk_div_table clk_alpha_div_table[] = {
1099 { 0x0, 1 },
1100 { 0x1, 2 },
1101 { 0x3, 4 },
1102 { 0x7, 8 },
1103 { 0xf, 16 },
1104 { }
1105};
1106
1107static const struct clk_div_table clk_alpha_2bit_div_table[] = {
1108 { 0x0, 1 },
1109 { 0x1, 2 },
1110 { 0x3, 4 },
1111 { }
1112};
1113
1114static long
1115clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1116 unsigned long *prate)
1117{
1118 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1119 const struct clk_div_table *table;
1120
1121 if (pll->width == 2)
1122 table = clk_alpha_2bit_div_table;
1123 else
1124 table = clk_alpha_div_table;
1125
1126 return divider_round_rate(hw, rate, prate, table,
1127 width: pll->width, CLK_DIVIDER_POWER_OF_TWO);
1128}
1129
1130static long
1131clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1132 unsigned long *prate)
1133{
1134 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1135 u32 ctl, div;
1136
1137 regmap_read(map: pll->clkr.regmap, PLL_USER_CTL(pll), val: &ctl);
1138
1139 ctl >>= PLL_POST_DIV_SHIFT;
1140 ctl &= BIT(pll->width) - 1;
1141 div = 1 << fls(x: ctl);
1142
1143 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1144 *prate = clk_hw_round_rate(hw: clk_hw_get_parent(hw), rate: div * rate);
1145
1146 return DIV_ROUND_UP_ULL((u64)*prate, div);
1147}
1148
1149static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1150 unsigned long parent_rate)
1151{
1152 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1153 int div;
1154
1155 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
1156 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1157
1158 return regmap_update_bits(map: pll->clkr.regmap, PLL_USER_CTL(pll),
1159 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1160 val: div << PLL_POST_DIV_SHIFT);
1161}
1162
1163const struct clk_ops clk_alpha_pll_postdiv_ops = {
1164 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1165 .round_rate = clk_alpha_pll_postdiv_round_rate,
1166 .set_rate = clk_alpha_pll_postdiv_set_rate,
1167};
1168EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1169
1170const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1171 .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1172 .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1173};
1174EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1175
1176void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1177 const struct alpha_pll_config *config)
1178{
1179 u32 val, mask;
1180
1181 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), val: config->l);
1182 clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), val: config->alpha);
1183 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1184 val: config->config_ctl_val);
1185 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1186 val: config->config_ctl_hi_val);
1187 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1188 val: config->user_ctl_val);
1189 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1190 val: config->user_ctl_hi_val);
1191 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1192 val: config->test_ctl_val);
1193 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1194 val: config->test_ctl_hi_val);
1195
1196 if (config->post_div_mask) {
1197 mask = config->post_div_mask;
1198 val = config->post_div_val;
1199 regmap_update_bits(map: regmap, PLL_USER_CTL(pll), mask, val);
1200 }
1201
1202 if (pll->flags & SUPPORTS_FSM_LEGACY_MODE)
1203 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_FSM_LEGACY_MODE,
1204 PLL_FSM_LEGACY_MODE);
1205
1206 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1207 PLL_UPDATE_BYPASS);
1208
1209 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1210}
1211EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1212
1213static int alpha_pll_fabia_enable(struct clk_hw *hw)
1214{
1215 int ret;
1216 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1217 u32 val, opmode_val;
1218 struct regmap *regmap = pll->clkr.regmap;
1219
1220 ret = regmap_read(map: regmap, PLL_MODE(pll), val: &val);
1221 if (ret)
1222 return ret;
1223
1224 /* If in FSM mode, just vote for it */
1225 if (val & PLL_VOTE_FSM_ENA) {
1226 ret = clk_enable_regmap(hw);
1227 if (ret)
1228 return ret;
1229 return wait_for_pll_enable_active(pll);
1230 }
1231
1232 ret = regmap_read(map: regmap, PLL_OPMODE(pll), val: &opmode_val);
1233 if (ret)
1234 return ret;
1235
1236 /* Skip If PLL is already running */
1237 if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1238 return 0;
1239
1240 ret = regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL, val: 0);
1241 if (ret)
1242 return ret;
1243
1244 ret = regmap_write(map: regmap, PLL_OPMODE(pll), PLL_STANDBY);
1245 if (ret)
1246 return ret;
1247
1248 ret = regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_RESET_N,
1249 PLL_RESET_N);
1250 if (ret)
1251 return ret;
1252
1253 ret = regmap_write(map: regmap, PLL_OPMODE(pll), PLL_RUN);
1254 if (ret)
1255 return ret;
1256
1257 ret = wait_for_pll_enable_lock(pll);
1258 if (ret)
1259 return ret;
1260
1261 ret = regmap_update_bits(map: regmap, PLL_USER_CTL(pll),
1262 PLL_OUT_MASK, PLL_OUT_MASK);
1263 if (ret)
1264 return ret;
1265
1266 return regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL,
1267 PLL_OUTCTRL);
1268}
1269
1270static void alpha_pll_fabia_disable(struct clk_hw *hw)
1271{
1272 int ret;
1273 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1274 u32 val;
1275 struct regmap *regmap = pll->clkr.regmap;
1276
1277 ret = regmap_read(map: regmap, PLL_MODE(pll), val: &val);
1278 if (ret)
1279 return;
1280
1281 /* If in FSM mode, just unvote it */
1282 if (val & PLL_FSM_ENA) {
1283 clk_disable_regmap(hw);
1284 return;
1285 }
1286
1287 ret = regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL, val: 0);
1288 if (ret)
1289 return;
1290
1291 /* Disable main outputs */
1292 ret = regmap_update_bits(map: regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, val: 0);
1293 if (ret)
1294 return;
1295
1296 /* Place the PLL in STANDBY */
1297 regmap_write(map: regmap, PLL_OPMODE(pll), PLL_STANDBY);
1298}
1299
1300static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1301 unsigned long parent_rate)
1302{
1303 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1304 u32 l, frac, alpha_width = pll_alpha_width(pll);
1305
1306 regmap_read(map: pll->clkr.regmap, PLL_L_VAL(pll), val: &l);
1307 regmap_read(map: pll->clkr.regmap, PLL_FRAC(pll), val: &frac);
1308
1309 return alpha_pll_calc_rate(prate: parent_rate, l, a: frac, alpha_width);
1310}
1311
1312/*
1313 * Due to limited number of bits for fractional rate programming, the
1314 * rounded up rate could be marginally higher than the requested rate.
1315 */
1316static int alpha_pll_check_rate_margin(struct clk_hw *hw,
1317 unsigned long rrate, unsigned long rate)
1318{
1319 unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1320
1321 if (rrate > rate_margin || rrate < rate) {
1322 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1323 clk_hw_get_name(hw), rrate, rate, rate_margin);
1324 return -EINVAL;
1325 }
1326
1327 return 0;
1328}
1329
1330static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1331 unsigned long prate)
1332{
1333 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1334 u32 l, alpha_width = pll_alpha_width(pll);
1335 unsigned long rrate;
1336 int ret;
1337 u64 a;
1338
1339 rrate = alpha_pll_round_rate(rate, prate, l: &l, a: &a, alpha_width);
1340
1341 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1342 if (ret < 0)
1343 return ret;
1344
1345 regmap_write(map: pll->clkr.regmap, PLL_L_VAL(pll), val: l);
1346 regmap_write(map: pll->clkr.regmap, PLL_FRAC(pll), val: a);
1347
1348 return __clk_alpha_pll_update_latch(pll);
1349}
1350
1351static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1352{
1353 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1354 const struct pll_vco *vco;
1355 struct clk_hw *parent_hw;
1356 unsigned long cal_freq, rrate;
1357 u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1358 const char *name = clk_hw_get_name(hw);
1359 u64 a;
1360 int ret;
1361
1362 /* Check if calibration needs to be done i.e. PLL is in reset */
1363 ret = regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
1364 if (ret)
1365 return ret;
1366
1367 /* Return early if calibration is not needed. */
1368 if (val & PLL_RESET_N)
1369 return 0;
1370
1371 vco = alpha_pll_find_vco(pll, rate: clk_hw_get_rate(hw));
1372 if (!vco) {
1373 pr_err("%s: alpha pll not in a valid vco range\n", name);
1374 return -EINVAL;
1375 }
1376
1377 cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1378 pll->vco_table[0].max_freq) * 54, 100);
1379
1380 parent_hw = clk_hw_get_parent(hw);
1381 if (!parent_hw)
1382 return -EINVAL;
1383
1384 rrate = alpha_pll_round_rate(rate: cal_freq, prate: clk_hw_get_rate(hw: parent_hw),
1385 l: &cal_l, a: &a, alpha_width);
1386
1387 ret = alpha_pll_check_rate_margin(hw, rrate, rate: cal_freq);
1388 if (ret < 0)
1389 return ret;
1390
1391 /* Setup PLL for calibration frequency */
1392 regmap_write(map: pll->clkr.regmap, PLL_CAL_L_VAL(pll), val: cal_l);
1393
1394 /* Bringup the PLL at calibration frequency */
1395 ret = clk_alpha_pll_enable(hw);
1396 if (ret) {
1397 pr_err("%s: alpha pll calibration failed\n", name);
1398 return ret;
1399 }
1400
1401 clk_alpha_pll_disable(hw);
1402
1403 return 0;
1404}
1405
1406const struct clk_ops clk_alpha_pll_fabia_ops = {
1407 .prepare = alpha_pll_fabia_prepare,
1408 .enable = alpha_pll_fabia_enable,
1409 .disable = alpha_pll_fabia_disable,
1410 .is_enabled = clk_alpha_pll_is_enabled,
1411 .set_rate = alpha_pll_fabia_set_rate,
1412 .recalc_rate = alpha_pll_fabia_recalc_rate,
1413 .round_rate = clk_alpha_pll_round_rate,
1414};
1415EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1416
1417const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1418 .enable = alpha_pll_fabia_enable,
1419 .disable = alpha_pll_fabia_disable,
1420 .is_enabled = clk_alpha_pll_is_enabled,
1421 .recalc_rate = alpha_pll_fabia_recalc_rate,
1422 .round_rate = clk_alpha_pll_round_rate,
1423};
1424EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1425
1426static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1427 unsigned long parent_rate)
1428{
1429 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1430 u32 i, div = 1, val;
1431 int ret;
1432
1433 ret = regmap_read(map: pll->clkr.regmap, PLL_USER_CTL(pll), val: &val);
1434 if (ret)
1435 return ret;
1436
1437 val >>= pll->post_div_shift;
1438 val &= BIT(pll->width) - 1;
1439
1440 for (i = 0; i < pll->num_post_div; i++) {
1441 if (pll->post_div_table[i].val == val) {
1442 div = pll->post_div_table[i].div;
1443 break;
1444 }
1445 }
1446
1447 return (parent_rate / div);
1448}
1449
1450static unsigned long
1451clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1452{
1453 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1454 struct regmap *regmap = pll->clkr.regmap;
1455 u32 i, div = 1, val;
1456
1457 regmap_read(map: regmap, PLL_USER_CTL(pll), val: &val);
1458
1459 val >>= pll->post_div_shift;
1460 val &= PLL_POST_DIV_MASK(pll);
1461
1462 for (i = 0; i < pll->num_post_div; i++) {
1463 if (pll->post_div_table[i].val == val) {
1464 div = pll->post_div_table[i].div;
1465 break;
1466 }
1467 }
1468
1469 return (parent_rate / div);
1470}
1471
1472static long
1473clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1474 unsigned long *prate)
1475{
1476 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1477
1478 return divider_round_rate(hw, rate, prate, table: pll->post_div_table,
1479 width: pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1480};
1481
1482static int
1483clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1484 unsigned long parent_rate)
1485{
1486 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1487 struct regmap *regmap = pll->clkr.regmap;
1488 int i, val = 0, div;
1489
1490 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1491 for (i = 0; i < pll->num_post_div; i++) {
1492 if (pll->post_div_table[i].div == div) {
1493 val = pll->post_div_table[i].val;
1494 break;
1495 }
1496 }
1497
1498 return regmap_update_bits(map: regmap, PLL_USER_CTL(pll),
1499 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1500 val: val << PLL_POST_DIV_SHIFT);
1501}
1502
1503const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1504 .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1505 .round_rate = clk_trion_pll_postdiv_round_rate,
1506 .set_rate = clk_trion_pll_postdiv_set_rate,
1507};
1508EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1509
1510static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1511 unsigned long rate, unsigned long *prate)
1512{
1513 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1514
1515 return divider_round_rate(hw, rate, prate, table: pll->post_div_table,
1516 width: pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1517}
1518
1519static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1520 unsigned long rate, unsigned long parent_rate)
1521{
1522 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1523 int i, val = 0, div, ret;
1524
1525 /*
1526 * If the PLL is in FSM mode, then treat set_rate callback as a
1527 * no-operation.
1528 */
1529 ret = regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
1530 if (ret)
1531 return ret;
1532
1533 if (val & PLL_VOTE_FSM_ENA)
1534 return 0;
1535
1536 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1537 for (i = 0; i < pll->num_post_div; i++) {
1538 if (pll->post_div_table[i].div == div) {
1539 val = pll->post_div_table[i].val;
1540 break;
1541 }
1542 }
1543
1544 return regmap_update_bits(map: pll->clkr.regmap, PLL_USER_CTL(pll),
1545 mask: (BIT(pll->width) - 1) << pll->post_div_shift,
1546 val: val << pll->post_div_shift);
1547}
1548
1549const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1550 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1551 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1552 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1553};
1554EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1555
1556/**
1557 * clk_trion_pll_configure - configure the trion pll
1558 *
1559 * @pll: clk alpha pll
1560 * @regmap: register map
1561 * @config: configuration to apply for pll
1562 */
1563void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1564 const struct alpha_pll_config *config)
1565{
1566 /*
1567 * If the bootloader left the PLL enabled it's likely that there are
1568 * RCGs that will lock up if we disable the PLL below.
1569 */
1570 if (trion_pll_is_enabled(pll, regmap)) {
1571 pr_debug("Trion PLL is already enabled, skipping configuration\n");
1572 return;
1573 }
1574
1575 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), val: config->l);
1576 regmap_write(map: regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1577 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), val: config->alpha);
1578 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1579 val: config->config_ctl_val);
1580 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1581 val: config->config_ctl_hi_val);
1582 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1583 val: config->config_ctl_hi1_val);
1584 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1585 val: config->user_ctl_val);
1586 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1587 val: config->user_ctl_hi_val);
1588 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1589 val: config->user_ctl_hi1_val);
1590 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1591 val: config->test_ctl_val);
1592 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1593 val: config->test_ctl_hi_val);
1594 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1595 val: config->test_ctl_hi1_val);
1596
1597 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1598 PLL_UPDATE_BYPASS);
1599
1600 /* Disable PLL output */
1601 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL, val: 0);
1602
1603 /* Set operation mode to OFF */
1604 regmap_write(map: regmap, PLL_OPMODE(pll), PLL_STANDBY);
1605
1606 /* Place the PLL in STANDBY mode */
1607 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1608}
1609EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1610
1611/*
1612 * The TRION PLL requires a power-on self-calibration which happens when the
1613 * PLL comes out of reset. Calibrate in case it is not completed.
1614 */
1615static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1616{
1617 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1618 u32 val;
1619 int ret;
1620
1621 /* Return early if calibration is not needed. */
1622 regmap_read(map: pll->clkr.regmap, PLL_STATUS(pll), val: &val);
1623 if (val & pcal_done)
1624 return 0;
1625
1626 /* On/off to calibrate */
1627 ret = clk_trion_pll_enable(hw);
1628 if (!ret)
1629 clk_trion_pll_disable(hw);
1630
1631 return ret;
1632}
1633
1634static int alpha_pll_trion_prepare(struct clk_hw *hw)
1635{
1636 return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1637}
1638
1639static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1640{
1641 return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1642}
1643
1644static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1645 unsigned long prate, u32 latch_bit, u32 latch_ack)
1646{
1647 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1648 unsigned long rrate;
1649 u32 val, l, alpha_width = pll_alpha_width(pll);
1650 u64 a;
1651 int ret;
1652
1653 rrate = alpha_pll_round_rate(rate, prate, l: &l, a: &a, alpha_width);
1654
1655 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1656 if (ret < 0)
1657 return ret;
1658
1659 regmap_write(map: pll->clkr.regmap, PLL_L_VAL(pll), val: l);
1660 regmap_write(map: pll->clkr.regmap, PLL_ALPHA_VAL(pll), val: a);
1661
1662 /* Latch the PLL input */
1663 ret = regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), mask: latch_bit, val: latch_bit);
1664 if (ret)
1665 return ret;
1666
1667 /* Wait for 2 reference cycles before checking the ACK bit. */
1668 udelay(1);
1669 regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
1670 if (!(val & latch_ack)) {
1671 pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1672 return -EINVAL;
1673 }
1674
1675 /* Return the latch input to 0 */
1676 ret = regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), mask: latch_bit, val: 0);
1677 if (ret)
1678 return ret;
1679
1680 if (clk_hw_is_enabled(hw)) {
1681 ret = wait_for_pll_enable_lock(pll);
1682 if (ret)
1683 return ret;
1684 }
1685
1686 /* Wait for PLL output to stabilize */
1687 udelay(100);
1688 return 0;
1689}
1690
1691static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1692 unsigned long prate)
1693{
1694 return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1695}
1696
1697const struct clk_ops clk_alpha_pll_trion_ops = {
1698 .prepare = alpha_pll_trion_prepare,
1699 .enable = clk_trion_pll_enable,
1700 .disable = clk_trion_pll_disable,
1701 .is_enabled = clk_trion_pll_is_enabled,
1702 .recalc_rate = clk_trion_pll_recalc_rate,
1703 .round_rate = clk_alpha_pll_round_rate,
1704 .set_rate = alpha_pll_trion_set_rate,
1705};
1706EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1707
1708const struct clk_ops clk_alpha_pll_lucid_ops = {
1709 .prepare = alpha_pll_lucid_prepare,
1710 .enable = clk_trion_pll_enable,
1711 .disable = clk_trion_pll_disable,
1712 .is_enabled = clk_trion_pll_is_enabled,
1713 .recalc_rate = clk_trion_pll_recalc_rate,
1714 .round_rate = clk_alpha_pll_round_rate,
1715 .set_rate = alpha_pll_trion_set_rate,
1716};
1717EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1718
1719const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1720 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1721 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1722 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1723};
1724EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
1725
1726void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1727 const struct alpha_pll_config *config)
1728{
1729 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), val: config->l);
1730 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), val: config->alpha);
1731 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1732 val: config->user_ctl_val);
1733 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1734 val: config->config_ctl_val);
1735 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1736 val: config->config_ctl_hi_val);
1737 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1738 val: config->test_ctl_val);
1739 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1740 val: config->test_ctl_hi_val);
1741}
1742EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
1743
1744static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1745 unsigned long prate)
1746{
1747 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1748 u32 l, alpha_width = pll_alpha_width(pll);
1749 int ret;
1750 unsigned long rrate;
1751 u64 a;
1752
1753 rrate = alpha_pll_round_rate(rate, prate, l: &l, a: &a, alpha_width);
1754 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1755 if (ret < 0)
1756 return ret;
1757
1758 /* change L_VAL without having to go through the power on sequence */
1759 regmap_write(map: pll->clkr.regmap, PLL_L_VAL(pll), val: l);
1760 regmap_write(map: pll->clkr.regmap, PLL_ALPHA_VAL(pll), val: a);
1761
1762 if (clk_hw_is_enabled(hw))
1763 return wait_for_pll_enable_lock(pll);
1764
1765 return 0;
1766}
1767
1768const struct clk_ops clk_alpha_pll_agera_ops = {
1769 .enable = clk_alpha_pll_enable,
1770 .disable = clk_alpha_pll_disable,
1771 .is_enabled = clk_alpha_pll_is_enabled,
1772 .recalc_rate = alpha_pll_fabia_recalc_rate,
1773 .round_rate = clk_alpha_pll_round_rate,
1774 .set_rate = clk_alpha_pll_agera_set_rate,
1775};
1776EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
1777
1778static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
1779{
1780 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1781 u32 val;
1782 int ret;
1783
1784 ret = regmap_read(map: pll->clkr.regmap, PLL_USER_CTL(pll), val: &val);
1785 if (ret)
1786 return ret;
1787
1788 /* If in FSM mode, just vote for it */
1789 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1790 ret = clk_enable_regmap(hw);
1791 if (ret)
1792 return ret;
1793 return wait_for_pll_enable_lock(pll);
1794 }
1795
1796 /* Check if PLL is already enabled, return if enabled */
1797 ret = trion_pll_is_enabled(pll, regmap: pll->clkr.regmap);
1798 if (ret < 0)
1799 return ret;
1800
1801 ret = regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1802 if (ret)
1803 return ret;
1804
1805 regmap_write(map: pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1806
1807 ret = wait_for_pll_enable_lock(pll);
1808 if (ret)
1809 return ret;
1810
1811 /* Enable the PLL outputs */
1812 ret = regmap_update_bits(map: pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1813 if (ret)
1814 return ret;
1815
1816 /* Enable the global PLL outputs */
1817 return regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1818}
1819
1820static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
1821{
1822 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1823 u32 val;
1824 int ret;
1825
1826 ret = regmap_read(map: pll->clkr.regmap, PLL_USER_CTL(pll), val: &val);
1827 if (ret)
1828 return;
1829
1830 /* If in FSM mode, just unvote it */
1831 if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1832 clk_disable_regmap(hw);
1833 return;
1834 }
1835
1836 /* Disable the global PLL output */
1837 ret = regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, val: 0);
1838 if (ret)
1839 return;
1840
1841 /* Disable the PLL outputs */
1842 ret = regmap_update_bits(map: pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, val: 0);
1843 if (ret)
1844 return;
1845
1846 /* Place the PLL mode in STANDBY */
1847 regmap_write(map: pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
1848}
1849
1850/*
1851 * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1852 * when the PLL comes out of reset. Calibrate in case it is not completed.
1853 */
1854static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
1855{
1856 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1857 struct clk_hw *p;
1858 u32 val = 0;
1859 int ret;
1860
1861 /* Return early if calibration is not needed. */
1862 regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
1863 if (val & LUCID_5LPE_PCAL_DONE)
1864 return 0;
1865
1866 p = clk_hw_get_parent(hw);
1867 if (!p)
1868 return -EINVAL;
1869
1870 ret = alpha_pll_lucid_5lpe_enable(hw);
1871 if (ret)
1872 return ret;
1873
1874 alpha_pll_lucid_5lpe_disable(hw);
1875
1876 return 0;
1877}
1878
1879static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
1880 unsigned long prate)
1881{
1882 return __alpha_pll_trion_set_rate(hw, rate, prate,
1883 LUCID_5LPE_PLL_LATCH_INPUT,
1884 LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
1885}
1886
1887static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1888 unsigned long parent_rate,
1889 unsigned long enable_vote_run)
1890{
1891 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1892 struct regmap *regmap = pll->clkr.regmap;
1893 int i, val, div, ret;
1894 u32 mask;
1895
1896 /*
1897 * If the PLL is in FSM mode, then treat set_rate callback as a
1898 * no-operation.
1899 */
1900 ret = regmap_read(map: regmap, PLL_USER_CTL(pll), val: &val);
1901 if (ret)
1902 return ret;
1903
1904 if (val & enable_vote_run)
1905 return 0;
1906
1907 if (!pll->post_div_table) {
1908 pr_err("Missing the post_div_table for the %s PLL\n",
1909 clk_hw_get_name(&pll->clkr.hw));
1910 return -EINVAL;
1911 }
1912
1913 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1914 for (i = 0; i < pll->num_post_div; i++) {
1915 if (pll->post_div_table[i].div == div) {
1916 val = pll->post_div_table[i].val;
1917 break;
1918 }
1919 }
1920
1921 mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
1922 return regmap_update_bits(map: pll->clkr.regmap, PLL_USER_CTL(pll),
1923 mask, val: val << pll->post_div_shift);
1924}
1925
1926static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1927 unsigned long parent_rate)
1928{
1929 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
1930}
1931
1932const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
1933 .prepare = alpha_pll_lucid_5lpe_prepare,
1934 .enable = alpha_pll_lucid_5lpe_enable,
1935 .disable = alpha_pll_lucid_5lpe_disable,
1936 .is_enabled = clk_trion_pll_is_enabled,
1937 .recalc_rate = clk_trion_pll_recalc_rate,
1938 .round_rate = clk_alpha_pll_round_rate,
1939 .set_rate = alpha_pll_lucid_5lpe_set_rate,
1940};
1941EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
1942
1943const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
1944 .enable = alpha_pll_lucid_5lpe_enable,
1945 .disable = alpha_pll_lucid_5lpe_disable,
1946 .is_enabled = clk_trion_pll_is_enabled,
1947 .recalc_rate = clk_trion_pll_recalc_rate,
1948 .round_rate = clk_alpha_pll_round_rate,
1949};
1950EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
1951
1952const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
1953 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1954 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1955 .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
1956};
1957EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
1958
1959void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1960 const struct alpha_pll_config *config)
1961{
1962 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), val: config->l);
1963 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), val: config->alpha);
1964 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), val: config->config_ctl_val);
1965 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), val: config->config_ctl_hi_val);
1966 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), val: config->config_ctl_hi1_val);
1967 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), val: config->user_ctl_val);
1968 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), val: config->user_ctl_hi_val);
1969 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), val: config->user_ctl_hi1_val);
1970 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), val: config->test_ctl_val);
1971 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), val: config->test_ctl_hi_val);
1972 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), val: config->test_ctl_hi1_val);
1973
1974 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_BYPASSNL, val: 0);
1975
1976 /* Disable PLL output */
1977 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL, val: 0);
1978
1979 /* Set operation mode to OFF */
1980 regmap_write(map: regmap, PLL_OPMODE(pll), PLL_STANDBY);
1981
1982 /* Place the PLL in STANDBY mode */
1983 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1984}
1985EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
1986
1987static int clk_zonda_pll_enable(struct clk_hw *hw)
1988{
1989 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1990 struct regmap *regmap = pll->clkr.regmap;
1991 u32 val;
1992 int ret;
1993
1994 regmap_read(map: regmap, PLL_MODE(pll), val: &val);
1995
1996 /* If in FSM mode, just vote for it */
1997 if (val & PLL_VOTE_FSM_ENA) {
1998 ret = clk_enable_regmap(hw);
1999 if (ret)
2000 return ret;
2001 return wait_for_pll_enable_active(pll);
2002 }
2003
2004 /* Get the PLL out of bypass mode */
2005 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
2006
2007 /*
2008 * H/W requires a 1us delay between disabling the bypass and
2009 * de-asserting the reset.
2010 */
2011 udelay(1);
2012
2013 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2014
2015 /* Set operation mode to RUN */
2016 regmap_write(map: regmap, PLL_OPMODE(pll), PLL_RUN);
2017
2018 regmap_read(map: regmap, PLL_TEST_CTL(pll), val: &val);
2019
2020 /* If cfa mode then poll for freq lock */
2021 if (val & ZONDA_STAY_IN_CFA)
2022 ret = wait_for_zonda_pll_freq_lock(pll);
2023 else
2024 ret = wait_for_pll_enable_lock(pll);
2025 if (ret)
2026 return ret;
2027
2028 /* Enable the PLL outputs */
2029 regmap_update_bits(map: regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
2030
2031 /* Enable the global PLL outputs */
2032 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2033
2034 return 0;
2035}
2036
2037static void clk_zonda_pll_disable(struct clk_hw *hw)
2038{
2039 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2040 struct regmap *regmap = pll->clkr.regmap;
2041 u32 val;
2042
2043 regmap_read(map: regmap, PLL_MODE(pll), val: &val);
2044
2045 /* If in FSM mode, just unvote it */
2046 if (val & PLL_VOTE_FSM_ENA) {
2047 clk_disable_regmap(hw);
2048 return;
2049 }
2050
2051 /* Disable the global PLL output */
2052 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL, val: 0);
2053
2054 /* Disable the PLL outputs */
2055 regmap_update_bits(map: regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, val: 0);
2056
2057 /* Put the PLL in bypass and reset */
2058 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, val: 0);
2059
2060 /* Place the PLL mode in OFF state */
2061 regmap_write(map: regmap, PLL_OPMODE(pll), val: 0x0);
2062}
2063
2064static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
2065 unsigned long prate)
2066{
2067 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2068 unsigned long rrate;
2069 u32 test_ctl_val;
2070 u32 l, alpha_width = pll_alpha_width(pll);
2071 u64 a;
2072 int ret;
2073
2074 rrate = alpha_pll_round_rate(rate, prate, l: &l, a: &a, alpha_width);
2075
2076 ret = alpha_pll_check_rate_margin(hw, rrate, rate);
2077 if (ret < 0)
2078 return ret;
2079
2080 regmap_write(map: pll->clkr.regmap, PLL_ALPHA_VAL(pll), val: a);
2081 regmap_write(map: pll->clkr.regmap, PLL_L_VAL(pll), val: l);
2082
2083 /* Wait before polling for the frequency latch */
2084 udelay(5);
2085
2086 /* Read stay in cfa mode */
2087 regmap_read(map: pll->clkr.regmap, PLL_TEST_CTL(pll), val: &test_ctl_val);
2088
2089 /* If cfa mode then poll for freq lock */
2090 if (test_ctl_val & ZONDA_STAY_IN_CFA)
2091 ret = wait_for_zonda_pll_freq_lock(pll);
2092 else
2093 ret = wait_for_pll_enable_lock(pll);
2094 if (ret)
2095 return ret;
2096
2097 /* Wait for PLL output to stabilize */
2098 udelay(100);
2099 return 0;
2100}
2101
2102const struct clk_ops clk_alpha_pll_zonda_ops = {
2103 .enable = clk_zonda_pll_enable,
2104 .disable = clk_zonda_pll_disable,
2105 .is_enabled = clk_trion_pll_is_enabled,
2106 .recalc_rate = clk_trion_pll_recalc_rate,
2107 .round_rate = clk_alpha_pll_round_rate,
2108 .set_rate = clk_zonda_pll_set_rate,
2109};
2110EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
2111
2112void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2113 const struct alpha_pll_config *config)
2114{
2115 u32 lval = config->l;
2116
2117 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2118 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), val: lval);
2119 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), val: config->alpha);
2120 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), val: config->config_ctl_val);
2121 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), val: config->config_ctl_hi_val);
2122 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), val: config->config_ctl_hi1_val);
2123 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), val: config->user_ctl_val);
2124 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), val: config->user_ctl_hi_val);
2125 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), val: config->test_ctl_val);
2126 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), val: config->test_ctl_hi_val);
2127 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), val: config->test_ctl_hi1_val);
2128 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), val: config->test_ctl_hi2_val);
2129
2130 /* Disable PLL output */
2131 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL, val: 0);
2132
2133 /* Set operation mode to STANDBY and de-assert the reset */
2134 regmap_write(map: regmap, PLL_OPMODE(pll), PLL_STANDBY);
2135 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2136}
2137EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
2138
2139void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2140 const struct alpha_pll_config *config)
2141{
2142 u32 lval = config->l;
2143
2144 lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2145 lval |= TRION_PLL_CAL_VAL << LUCID_OLE_PLL_RINGOSC_CAL_L_VAL_SHIFT;
2146 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), val: lval);
2147 clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), val: config->alpha);
2148 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), val: config->config_ctl_val);
2149 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), val: config->config_ctl_hi_val);
2150 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), val: config->config_ctl_hi1_val);
2151 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), val: config->user_ctl_val);
2152 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), val: config->user_ctl_hi_val);
2153 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), val: config->test_ctl_val);
2154 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), val: config->test_ctl_hi_val);
2155 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), val: config->test_ctl_hi1_val);
2156 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U2(pll), val: config->test_ctl_hi2_val);
2157
2158 /* Disable PLL output */
2159 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL, val: 0);
2160
2161 /* Set operation mode to STANDBY and de-assert the reset */
2162 regmap_write(map: regmap, PLL_OPMODE(pll), PLL_STANDBY);
2163 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2164}
2165EXPORT_SYMBOL_GPL(clk_lucid_ole_pll_configure);
2166
2167static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
2168{
2169 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2170 struct regmap *regmap = pll->clkr.regmap;
2171 u32 val;
2172 int ret;
2173
2174 ret = regmap_read(map: regmap, PLL_USER_CTL(pll), val: &val);
2175 if (ret)
2176 return ret;
2177
2178 /* If in FSM mode, just vote for it */
2179 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2180 ret = clk_enable_regmap(hw);
2181 if (ret)
2182 return ret;
2183 return wait_for_pll_enable_lock(pll);
2184 }
2185
2186 /* Check if PLL is already enabled */
2187 ret = trion_pll_is_enabled(pll, regmap);
2188 if (ret < 0) {
2189 return ret;
2190 } else if (ret) {
2191 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
2192 return 0;
2193 }
2194
2195 ret = regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2196 if (ret)
2197 return ret;
2198
2199 /* Set operation mode to RUN */
2200 regmap_write(map: regmap, PLL_OPMODE(pll), PLL_RUN);
2201
2202 ret = wait_for_pll_enable_lock(pll);
2203 if (ret)
2204 return ret;
2205
2206 /* Enable the PLL outputs */
2207 ret = regmap_update_bits(map: regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2208 if (ret)
2209 return ret;
2210
2211 /* Enable the global PLL outputs */
2212 ret = regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2213 if (ret)
2214 return ret;
2215
2216 /* Ensure that the write above goes through before returning. */
2217 mb();
2218 return ret;
2219}
2220
2221static void _alpha_pll_lucid_evo_disable(struct clk_hw *hw, bool reset)
2222{
2223 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2224 struct regmap *regmap = pll->clkr.regmap;
2225 u32 val;
2226 int ret;
2227
2228 ret = regmap_read(map: regmap, PLL_USER_CTL(pll), val: &val);
2229 if (ret)
2230 return;
2231
2232 /* If in FSM mode, just unvote it */
2233 if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2234 clk_disable_regmap(hw);
2235 return;
2236 }
2237
2238 /* Disable the global PLL output */
2239 ret = regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_OUTCTRL, val: 0);
2240 if (ret)
2241 return;
2242
2243 /* Disable the PLL outputs */
2244 ret = regmap_update_bits(map: regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, val: 0);
2245 if (ret)
2246 return;
2247
2248 /* Place the PLL mode in STANDBY */
2249 regmap_write(map: regmap, PLL_OPMODE(pll), PLL_STANDBY);
2250
2251 if (reset)
2252 regmap_update_bits(map: regmap, PLL_MODE(pll), PLL_RESET_N, val: 0);
2253}
2254
2255static int _alpha_pll_lucid_evo_prepare(struct clk_hw *hw, bool reset)
2256{
2257 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2258 struct clk_hw *p;
2259 u32 val = 0;
2260 int ret;
2261
2262 /* Return early if calibration is not needed. */
2263 regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &val);
2264 if (!(val & LUCID_EVO_PCAL_NOT_DONE))
2265 return 0;
2266
2267 p = clk_hw_get_parent(hw);
2268 if (!p)
2269 return -EINVAL;
2270
2271 ret = alpha_pll_lucid_evo_enable(hw);
2272 if (ret)
2273 return ret;
2274
2275 _alpha_pll_lucid_evo_disable(hw, reset);
2276
2277 return 0;
2278}
2279
2280static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2281{
2282 _alpha_pll_lucid_evo_disable(hw, reset: false);
2283}
2284
2285static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
2286{
2287 return _alpha_pll_lucid_evo_prepare(hw, reset: false);
2288}
2289
2290static void alpha_pll_reset_lucid_evo_disable(struct clk_hw *hw)
2291{
2292 _alpha_pll_lucid_evo_disable(hw, reset: true);
2293}
2294
2295static int alpha_pll_reset_lucid_evo_prepare(struct clk_hw *hw)
2296{
2297 return _alpha_pll_lucid_evo_prepare(hw, reset: true);
2298}
2299
2300static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2301 unsigned long parent_rate)
2302{
2303 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2304 struct regmap *regmap = pll->clkr.regmap;
2305 u32 l, frac;
2306
2307 regmap_read(map: regmap, PLL_L_VAL(pll), val: &l);
2308 l &= LUCID_EVO_PLL_L_VAL_MASK;
2309 regmap_read(map: regmap, PLL_ALPHA_VAL(pll), val: &frac);
2310
2311 return alpha_pll_calc_rate(prate: parent_rate, l, a: frac, pll_alpha_width(pll));
2312}
2313
2314static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2315 unsigned long parent_rate)
2316{
2317 return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2318}
2319
2320const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2321 .enable = alpha_pll_lucid_evo_enable,
2322 .disable = alpha_pll_lucid_evo_disable,
2323 .is_enabled = clk_trion_pll_is_enabled,
2324 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2325 .round_rate = clk_alpha_pll_round_rate,
2326};
2327EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2328
2329const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2330 .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2331 .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2332 .set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2333};
2334EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
2335
2336const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
2337 .prepare = alpha_pll_lucid_evo_prepare,
2338 .enable = alpha_pll_lucid_evo_enable,
2339 .disable = alpha_pll_lucid_evo_disable,
2340 .is_enabled = clk_trion_pll_is_enabled,
2341 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2342 .round_rate = clk_alpha_pll_round_rate,
2343 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2344};
2345EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
2346
2347const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops = {
2348 .prepare = alpha_pll_reset_lucid_evo_prepare,
2349 .enable = alpha_pll_lucid_evo_enable,
2350 .disable = alpha_pll_reset_lucid_evo_disable,
2351 .is_enabled = clk_trion_pll_is_enabled,
2352 .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2353 .round_rate = clk_alpha_pll_round_rate,
2354 .set_rate = alpha_pll_lucid_5lpe_set_rate,
2355};
2356EXPORT_SYMBOL_GPL(clk_alpha_pll_reset_lucid_evo_ops);
2357
2358void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2359 const struct alpha_pll_config *config)
2360{
2361 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), val: config->config_ctl_val);
2362 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), val: config->config_ctl_hi_val);
2363 clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), val: config->config_ctl_hi1_val);
2364 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), val: config->test_ctl_val);
2365 clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), val: config->test_ctl_hi_val);
2366 clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), val: config->l);
2367 clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), val: config->user_ctl_val);
2368 clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), val: config->user_ctl_hi_val);
2369
2370 regmap_write(map: regmap, PLL_OPMODE(pll), PLL_STANDBY);
2371
2372 regmap_update_bits(map: regmap, PLL_MODE(pll),
2373 PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
2374 PLL_RESET_N | PLL_BYPASSNL);
2375}
2376EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
2377
2378static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
2379 unsigned long parent_rate)
2380{
2381 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2382 u32 l;
2383
2384 regmap_read(map: pll->clkr.regmap, PLL_L_VAL(pll), val: &l);
2385
2386 return parent_rate * l;
2387}
2388
2389static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2390 unsigned long *prate)
2391{
2392 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2393 unsigned long min_freq, max_freq;
2394 u32 l;
2395 u64 a;
2396
2397 rate = alpha_pll_round_rate(rate, prate: *prate, l: &l, a: &a, alpha_width: 0);
2398 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2399 return rate;
2400
2401 min_freq = pll->vco_table[0].min_freq;
2402 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2403
2404 return clamp(rate, min_freq, max_freq);
2405}
2406
2407const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
2408 .enable = alpha_pll_lucid_5lpe_enable,
2409 .disable = alpha_pll_lucid_5lpe_disable,
2410 .is_enabled = clk_trion_pll_is_enabled,
2411 .recalc_rate = clk_rivian_evo_pll_recalc_rate,
2412 .round_rate = clk_rivian_evo_pll_round_rate,
2413};
2414EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
2415
2416void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2417 const struct alpha_pll_config *config)
2418{
2419 u32 val, val_u, mask, mask_u;
2420
2421 regmap_write(map: regmap, PLL_L_VAL(pll), val: config->l);
2422 regmap_write(map: regmap, PLL_ALPHA_VAL(pll), val: config->alpha);
2423 regmap_write(map: regmap, PLL_CONFIG_CTL(pll), val: config->config_ctl_val);
2424
2425 if (pll_has_64bit_config(pll))
2426 regmap_write(map: regmap, PLL_CONFIG_CTL_U(pll),
2427 val: config->config_ctl_hi_val);
2428
2429 if (pll_alpha_width(pll) > 32)
2430 regmap_write(map: regmap, PLL_ALPHA_VAL_U(pll), val: config->alpha_hi);
2431
2432 val = config->main_output_mask;
2433 val |= config->aux_output_mask;
2434 val |= config->aux2_output_mask;
2435 val |= config->early_output_mask;
2436 val |= config->pre_div_val;
2437 val |= config->post_div_val;
2438 val |= config->vco_val;
2439 val |= config->alpha_en_mask;
2440 val |= config->alpha_mode_mask;
2441
2442 mask = config->main_output_mask;
2443 mask |= config->aux_output_mask;
2444 mask |= config->aux2_output_mask;
2445 mask |= config->early_output_mask;
2446 mask |= config->pre_div_mask;
2447 mask |= config->post_div_mask;
2448 mask |= config->vco_mask;
2449 mask |= config->alpha_en_mask;
2450 mask |= config->alpha_mode_mask;
2451
2452 regmap_update_bits(map: regmap, PLL_USER_CTL(pll), mask, val);
2453
2454 /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
2455 val_u = config->status_val << ALPHA_PLL_STATUS_REG_SHIFT;
2456 val_u |= config->lock_det;
2457
2458 mask_u = config->status_mask;
2459 mask_u |= config->lock_det;
2460
2461 regmap_update_bits(map: regmap, PLL_USER_CTL_U(pll), mask: mask_u, val: val_u);
2462 regmap_write(map: regmap, PLL_TEST_CTL(pll), val: config->test_ctl_val);
2463 regmap_write(map: regmap, PLL_TEST_CTL_U(pll), val: config->test_ctl_hi_val);
2464
2465 if (pll->flags & SUPPORTS_FSM_MODE)
2466 qcom_pll_set_fsm_mode(m: regmap, PLL_MODE(pll), bias_count: 6, lock_count: 0);
2467}
2468EXPORT_SYMBOL_GPL(clk_stromer_pll_configure);
2469
2470static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
2471 struct clk_rate_request *req)
2472{
2473 u32 l;
2474 u64 a;
2475
2476 req->rate = alpha_pll_round_rate(rate: req->rate, prate: req->best_parent_rate,
2477 l: &l, a: &a, ALPHA_REG_BITWIDTH);
2478
2479 return 0;
2480}
2481
2482static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
2483 unsigned long prate)
2484{
2485 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2486 int ret;
2487 u32 l;
2488 u64 a;
2489
2490 rate = alpha_pll_round_rate(rate, prate, l: &l, a: &a, ALPHA_REG_BITWIDTH);
2491
2492 regmap_write(map: pll->clkr.regmap, PLL_L_VAL(pll), val: l);
2493 regmap_write(map: pll->clkr.regmap, PLL_ALPHA_VAL(pll), val: a);
2494 regmap_write(map: pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2495 val: a >> ALPHA_BITWIDTH);
2496
2497 regmap_update_bits(map: pll->clkr.regmap, PLL_USER_CTL(pll),
2498 PLL_ALPHA_EN, PLL_ALPHA_EN);
2499
2500 if (!clk_hw_is_enabled(hw))
2501 return 0;
2502
2503 /*
2504 * Stromer PLL supports Dynamic programming.
2505 * It allows the PLL frequency to be changed on-the-fly without first
2506 * execution of a shutdown procedure followed by a bring up procedure.
2507 */
2508 regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
2509 PLL_UPDATE);
2510
2511 ret = wait_for_pll_update(pll);
2512 if (ret)
2513 return ret;
2514
2515 return wait_for_pll_enable_lock(pll);
2516}
2517
2518const struct clk_ops clk_alpha_pll_stromer_ops = {
2519 .enable = clk_alpha_pll_enable,
2520 .disable = clk_alpha_pll_disable,
2521 .is_enabled = clk_alpha_pll_is_enabled,
2522 .recalc_rate = clk_alpha_pll_recalc_rate,
2523 .determine_rate = clk_alpha_pll_stromer_determine_rate,
2524 .set_rate = clk_alpha_pll_stromer_set_rate,
2525};
2526EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
2527
2528static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
2529 unsigned long rate,
2530 unsigned long prate)
2531{
2532 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2533 u32 l, alpha_width = pll_alpha_width(pll);
2534 int ret, pll_mode;
2535 u64 a;
2536
2537 rate = alpha_pll_round_rate(rate, prate, l: &l, a: &a, alpha_width);
2538
2539 ret = regmap_read(map: pll->clkr.regmap, PLL_MODE(pll), val: &pll_mode);
2540 if (ret)
2541 return ret;
2542
2543 regmap_write(map: pll->clkr.regmap, PLL_MODE(pll), val: 0);
2544
2545 /* Delay of 2 output clock ticks required until output is disabled */
2546 udelay(1);
2547
2548 regmap_write(map: pll->clkr.regmap, PLL_L_VAL(pll), val: l);
2549
2550 if (alpha_width > ALPHA_BITWIDTH)
2551 a <<= alpha_width - ALPHA_BITWIDTH;
2552
2553 regmap_write(map: pll->clkr.regmap, PLL_ALPHA_VAL(pll), val: a);
2554 regmap_write(map: pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
2555 val: a >> ALPHA_BITWIDTH);
2556
2557 regmap_write(map: pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
2558
2559 /* Wait five micro seconds or more */
2560 udelay(5);
2561 regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N,
2562 PLL_RESET_N);
2563
2564 /* The lock time should be less than 50 micro seconds worst case */
2565 usleep_range(min: 50, max: 60);
2566
2567 ret = wait_for_pll_enable_lock(pll);
2568 if (ret) {
2569 pr_err("Wait for PLL enable lock failed [%s] %d\n",
2570 clk_hw_get_name(hw), ret);
2571 return ret;
2572 }
2573
2574 if (pll_mode & PLL_OUTCTRL)
2575 regmap_update_bits(map: pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL,
2576 PLL_OUTCTRL);
2577
2578 return 0;
2579}
2580
2581const struct clk_ops clk_alpha_pll_stromer_plus_ops = {
2582 .prepare = clk_alpha_pll_enable,
2583 .unprepare = clk_alpha_pll_disable,
2584 .is_enabled = clk_alpha_pll_is_enabled,
2585 .recalc_rate = clk_alpha_pll_recalc_rate,
2586 .determine_rate = clk_alpha_pll_stromer_determine_rate,
2587 .set_rate = clk_alpha_pll_stromer_plus_set_rate,
2588};
2589EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_plus_ops);
2590

source code of linux/drivers/clk/qcom/clk-alpha-pll.c