1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2016, Linaro Limited |
4 | * Copyright (c) 2014, The Linux Foundation. All rights reserved. |
5 | */ |
6 | |
7 | #include <linux/clk-provider.h> |
8 | #include <linux/err.h> |
9 | #include <linux/export.h> |
10 | #include <linux/init.h> |
11 | #include <linux/kernel.h> |
12 | #include <linux/module.h> |
13 | #include <linux/mutex.h> |
14 | #include <linux/of.h> |
15 | #include <linux/platform_device.h> |
16 | #include <linux/soc/qcom/smd-rpm.h> |
17 | |
18 | #include <dt-bindings/clock/qcom,rpmcc.h> |
19 | |
20 | #define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \ |
21 | type, r_id, key, ao_rate, ao_flags) \ |
22 | static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ |
23 | static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ |
24 | .rpm_res_type = (type), \ |
25 | .rpm_clk_id = (r_id), \ |
26 | .rpm_key = (key), \ |
27 | .peer = &clk_smd_rpm_##_prefix##_active, \ |
28 | .rate = INT_MAX, \ |
29 | .hw.init = &(struct clk_init_data){ \ |
30 | .ops = &clk_smd_rpm_ops, \ |
31 | .name = #_name, \ |
32 | .parent_data = &(const struct clk_parent_data){ \ |
33 | .fw_name = "xo", \ |
34 | .name = "xo_board", \ |
35 | }, \ |
36 | .num_parents = 1, \ |
37 | }, \ |
38 | }; \ |
39 | static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ |
40 | .rpm_res_type = (type), \ |
41 | .rpm_clk_id = (r_id), \ |
42 | .active_only = true, \ |
43 | .rpm_key = (key), \ |
44 | .peer = &clk_smd_rpm_##_prefix##_name, \ |
45 | .rate = (ao_rate), \ |
46 | .hw.init = &(struct clk_init_data){ \ |
47 | .ops = &clk_smd_rpm_ops, \ |
48 | .name = #_active, \ |
49 | .parent_data = &(const struct clk_parent_data){ \ |
50 | .fw_name = "xo", \ |
51 | .name = "xo_board", \ |
52 | }, \ |
53 | .num_parents = 1, \ |
54 | .flags = (ao_flags), \ |
55 | }, \ |
56 | } |
57 | |
58 | #define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key,\ |
59 | ao_rate, ao_flags) \ |
60 | __DEFINE_CLK_SMD_RPM_PREFIX(/* empty */, _name, _active, \ |
61 | type, r_id, key, ao_rate, ao_flags) |
62 | |
63 | #define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\ |
64 | type, r_id, r, key, ao_flags) \ |
65 | static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ |
66 | static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ |
67 | .rpm_res_type = (type), \ |
68 | .rpm_clk_id = (r_id), \ |
69 | .rpm_key = (key), \ |
70 | .branch = true, \ |
71 | .peer = &clk_smd_rpm_##_prefix##_active, \ |
72 | .rate = (r), \ |
73 | .hw.init = &(struct clk_init_data){ \ |
74 | .ops = &clk_smd_rpm_branch_ops, \ |
75 | .name = #_name, \ |
76 | .parent_data = &(const struct clk_parent_data){ \ |
77 | .fw_name = "xo", \ |
78 | .name = "xo_board", \ |
79 | }, \ |
80 | .num_parents = 1, \ |
81 | }, \ |
82 | }; \ |
83 | static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ |
84 | .rpm_res_type = (type), \ |
85 | .rpm_clk_id = (r_id), \ |
86 | .active_only = true, \ |
87 | .rpm_key = (key), \ |
88 | .branch = true, \ |
89 | .peer = &clk_smd_rpm_##_prefix##_name, \ |
90 | .rate = (r), \ |
91 | .hw.init = &(struct clk_init_data){ \ |
92 | .ops = &clk_smd_rpm_branch_ops, \ |
93 | .name = #_active, \ |
94 | .parent_data = &(const struct clk_parent_data){ \ |
95 | .fw_name = "xo", \ |
96 | .name = "xo_board", \ |
97 | }, \ |
98 | .num_parents = 1, \ |
99 | .flags = (ao_flags), \ |
100 | }, \ |
101 | } |
102 | |
103 | #define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \ |
104 | __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \ |
105 | _name, _active, type, r_id, r, key, 0) |
106 | |
107 | #define DEFINE_CLK_SMD_RPM(_name, type, r_id) \ |
108 | __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ |
109 | type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0) |
110 | |
111 | #define DEFINE_CLK_SMD_RPM_BUS(_name, r_id) \ |
112 | __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \ |
113 | _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ |
114 | QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0) |
115 | |
116 | #define DEFINE_CLK_SMD_RPM_BUS_A(_name, r_id, ao_rate, ao_flags) \ |
117 | __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \ |
118 | _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ |
119 | QCOM_RPM_SMD_KEY_RATE, ao_rate, ao_flags) |
120 | |
121 | #define DEFINE_CLK_SMD_RPM_CLK_SRC(_name, type, r_id) \ |
122 | __DEFINE_CLK_SMD_RPM( \ |
123 | _name##_clk_src, _name##_a_clk_src, \ |
124 | type, r_id, QCOM_RPM_SMD_KEY_RATE, INT_MAX, 0) |
125 | |
126 | #define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \ |
127 | __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ |
128 | _name##_clk, _name##_a_clk, \ |
129 | type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE, 0) |
130 | |
131 | #define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r, ao_flags) \ |
132 | __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ |
133 | _name, _name##_a, type, \ |
134 | r_id, r, QCOM_RPM_SMD_KEY_ENABLE, ao_flags) |
135 | |
136 | #define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \ |
137 | __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ |
138 | type, r_id, QCOM_RPM_SMD_KEY_STATE, INT_MAX, 0) |
139 | |
140 | #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r) \ |
141 | __DEFINE_CLK_SMD_RPM_BRANCH(_name, _name##_a, \ |
142 | QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ |
143 | QCOM_RPM_KEY_SOFTWARE_ENABLE) |
144 | |
145 | #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(_prefix, _name, r_id, r) \ |
146 | __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \ |
147 | _name, _name##_a, \ |
148 | QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ |
149 | QCOM_RPM_KEY_SOFTWARE_ENABLE, 0) |
150 | |
151 | #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \ |
152 | DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \ |
153 | __DEFINE_CLK_SMD_RPM_BRANCH(_name##_pin, _name##_a##_pin, \ |
154 | QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ |
155 | QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) |
156 | |
157 | #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw) |
158 | |
159 | static struct qcom_smd_rpm *rpmcc_smd_rpm; |
160 | |
161 | struct clk_smd_rpm { |
162 | const int rpm_res_type; |
163 | const int rpm_key; |
164 | const int rpm_clk_id; |
165 | const bool active_only; |
166 | bool enabled; |
167 | bool branch; |
168 | struct clk_smd_rpm *peer; |
169 | struct clk_hw hw; |
170 | unsigned long rate; |
171 | }; |
172 | |
173 | struct rpm_smd_clk_desc { |
174 | struct clk_smd_rpm **clks; |
175 | size_t num_clks; |
176 | |
177 | /* |
178 | * Interconnect clocks are managed by the icc framework, this driver |
179 | * only kickstarts them so that they don't get gated between |
180 | * clk_smd_rpm_enable_scaling() and interconnect driver initialization. |
181 | */ |
182 | const struct clk_smd_rpm ** const icc_clks; |
183 | size_t num_icc_clks; |
184 | bool scaling_before_handover; |
185 | }; |
186 | |
187 | static DEFINE_MUTEX(rpm_smd_clk_lock); |
188 | |
189 | static int clk_smd_rpm_handoff(const struct clk_smd_rpm *r) |
190 | { |
191 | int ret; |
192 | struct clk_smd_rpm_req req = { |
193 | .key = cpu_to_le32(r->rpm_key), |
194 | .nbytes = cpu_to_le32(sizeof(u32)), |
195 | .value = cpu_to_le32(r->branch ? 1 : INT_MAX), |
196 | }; |
197 | |
198 | ret = qcom_rpm_smd_write(rpm: rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, |
199 | resource_type: r->rpm_res_type, resource_id: r->rpm_clk_id, buf: &req, |
200 | count: sizeof(req)); |
201 | if (ret) |
202 | return ret; |
203 | ret = qcom_rpm_smd_write(rpm: rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, |
204 | resource_type: r->rpm_res_type, resource_id: r->rpm_clk_id, buf: &req, |
205 | count: sizeof(req)); |
206 | if (ret) |
207 | return ret; |
208 | |
209 | return 0; |
210 | } |
211 | |
212 | static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r, |
213 | unsigned long rate) |
214 | { |
215 | struct clk_smd_rpm_req req = { |
216 | .key = cpu_to_le32(r->rpm_key), |
217 | .nbytes = cpu_to_le32(sizeof(u32)), |
218 | .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ |
219 | }; |
220 | |
221 | return qcom_rpm_smd_write(rpm: rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, |
222 | resource_type: r->rpm_res_type, resource_id: r->rpm_clk_id, buf: &req, |
223 | count: sizeof(req)); |
224 | } |
225 | |
226 | static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r, |
227 | unsigned long rate) |
228 | { |
229 | struct clk_smd_rpm_req req = { |
230 | .key = cpu_to_le32(r->rpm_key), |
231 | .nbytes = cpu_to_le32(sizeof(u32)), |
232 | .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */ |
233 | }; |
234 | |
235 | return qcom_rpm_smd_write(rpm: rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, |
236 | resource_type: r->rpm_res_type, resource_id: r->rpm_clk_id, buf: &req, |
237 | count: sizeof(req)); |
238 | } |
239 | |
240 | static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate, |
241 | unsigned long *active, unsigned long *sleep) |
242 | { |
243 | *active = rate; |
244 | |
245 | /* |
246 | * Active-only clocks don't care what the rate is during sleep. So, |
247 | * they vote for zero. |
248 | */ |
249 | if (r->active_only) |
250 | *sleep = 0; |
251 | else |
252 | *sleep = *active; |
253 | } |
254 | |
255 | static int clk_smd_rpm_prepare(struct clk_hw *hw) |
256 | { |
257 | struct clk_smd_rpm *r = to_clk_smd_rpm(hw); |
258 | struct clk_smd_rpm *peer = r->peer; |
259 | unsigned long this_rate = 0, this_sleep_rate = 0; |
260 | unsigned long peer_rate = 0, peer_sleep_rate = 0; |
261 | unsigned long active_rate, sleep_rate; |
262 | int ret = 0; |
263 | |
264 | mutex_lock(&rpm_smd_clk_lock); |
265 | |
266 | /* Don't send requests to the RPM if the rate has not been set. */ |
267 | if (!r->rate) |
268 | goto out; |
269 | |
270 | to_active_sleep(r, rate: r->rate, active: &this_rate, sleep: &this_sleep_rate); |
271 | |
272 | /* Take peer clock's rate into account only if it's enabled. */ |
273 | if (peer->enabled) |
274 | to_active_sleep(r: peer, rate: peer->rate, |
275 | active: &peer_rate, sleep: &peer_sleep_rate); |
276 | |
277 | active_rate = max(this_rate, peer_rate); |
278 | |
279 | if (r->branch) |
280 | active_rate = !!active_rate; |
281 | |
282 | ret = clk_smd_rpm_set_rate_active(r, rate: active_rate); |
283 | if (ret) |
284 | goto out; |
285 | |
286 | sleep_rate = max(this_sleep_rate, peer_sleep_rate); |
287 | if (r->branch) |
288 | sleep_rate = !!sleep_rate; |
289 | |
290 | ret = clk_smd_rpm_set_rate_sleep(r, rate: sleep_rate); |
291 | if (ret) |
292 | /* Undo the active set vote and restore it */ |
293 | ret = clk_smd_rpm_set_rate_active(r, rate: peer_rate); |
294 | |
295 | out: |
296 | if (!ret) |
297 | r->enabled = true; |
298 | |
299 | mutex_unlock(lock: &rpm_smd_clk_lock); |
300 | |
301 | return ret; |
302 | } |
303 | |
304 | static void clk_smd_rpm_unprepare(struct clk_hw *hw) |
305 | { |
306 | struct clk_smd_rpm *r = to_clk_smd_rpm(hw); |
307 | struct clk_smd_rpm *peer = r->peer; |
308 | unsigned long peer_rate = 0, peer_sleep_rate = 0; |
309 | unsigned long active_rate, sleep_rate; |
310 | int ret; |
311 | |
312 | mutex_lock(&rpm_smd_clk_lock); |
313 | |
314 | if (!r->rate) |
315 | goto out; |
316 | |
317 | /* Take peer clock's rate into account only if it's enabled. */ |
318 | if (peer->enabled) |
319 | to_active_sleep(r: peer, rate: peer->rate, active: &peer_rate, |
320 | sleep: &peer_sleep_rate); |
321 | |
322 | active_rate = r->branch ? !!peer_rate : peer_rate; |
323 | ret = clk_smd_rpm_set_rate_active(r, rate: active_rate); |
324 | if (ret) |
325 | goto out; |
326 | |
327 | sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate; |
328 | ret = clk_smd_rpm_set_rate_sleep(r, rate: sleep_rate); |
329 | if (ret) |
330 | goto out; |
331 | |
332 | r->enabled = false; |
333 | |
334 | out: |
335 | mutex_unlock(lock: &rpm_smd_clk_lock); |
336 | } |
337 | |
338 | static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate, |
339 | unsigned long parent_rate) |
340 | { |
341 | struct clk_smd_rpm *r = to_clk_smd_rpm(hw); |
342 | struct clk_smd_rpm *peer = r->peer; |
343 | unsigned long active_rate, sleep_rate; |
344 | unsigned long this_rate = 0, this_sleep_rate = 0; |
345 | unsigned long peer_rate = 0, peer_sleep_rate = 0; |
346 | int ret = 0; |
347 | |
348 | mutex_lock(&rpm_smd_clk_lock); |
349 | |
350 | if (!r->enabled) |
351 | goto out; |
352 | |
353 | to_active_sleep(r, rate, active: &this_rate, sleep: &this_sleep_rate); |
354 | |
355 | /* Take peer clock's rate into account only if it's enabled. */ |
356 | if (peer->enabled) |
357 | to_active_sleep(r: peer, rate: peer->rate, |
358 | active: &peer_rate, sleep: &peer_sleep_rate); |
359 | |
360 | active_rate = max(this_rate, peer_rate); |
361 | ret = clk_smd_rpm_set_rate_active(r, rate: active_rate); |
362 | if (ret) |
363 | goto out; |
364 | |
365 | sleep_rate = max(this_sleep_rate, peer_sleep_rate); |
366 | ret = clk_smd_rpm_set_rate_sleep(r, rate: sleep_rate); |
367 | if (ret) |
368 | goto out; |
369 | |
370 | r->rate = rate; |
371 | |
372 | out: |
373 | mutex_unlock(lock: &rpm_smd_clk_lock); |
374 | |
375 | return ret; |
376 | } |
377 | |
378 | static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate, |
379 | unsigned long *parent_rate) |
380 | { |
381 | /* |
382 | * RPM handles rate rounding and we don't have a way to |
383 | * know what the rate will be, so just return whatever |
384 | * rate is requested. |
385 | */ |
386 | return rate; |
387 | } |
388 | |
389 | static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw, |
390 | unsigned long parent_rate) |
391 | { |
392 | struct clk_smd_rpm *r = to_clk_smd_rpm(hw); |
393 | |
394 | /* |
395 | * RPM handles rate rounding and we don't have a way to |
396 | * know what the rate will be, so just return whatever |
397 | * rate was set. |
398 | */ |
399 | return r->rate; |
400 | } |
401 | |
402 | static int clk_smd_rpm_enable_scaling(void) |
403 | { |
404 | int ret; |
405 | struct clk_smd_rpm_req req = { |
406 | .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE), |
407 | .nbytes = cpu_to_le32(sizeof(u32)), |
408 | .value = cpu_to_le32(1), |
409 | }; |
410 | |
411 | ret = qcom_rpm_smd_write(rpm: rpmcc_smd_rpm, QCOM_SMD_RPM_SLEEP_STATE, |
412 | QCOM_SMD_RPM_MISC_CLK, |
413 | QCOM_RPM_SCALING_ENABLE_ID, buf: &req, count: sizeof(req)); |
414 | if (ret) { |
415 | pr_err("RPM clock scaling (sleep set) not enabled!\n" ); |
416 | return ret; |
417 | } |
418 | |
419 | ret = qcom_rpm_smd_write(rpm: rpmcc_smd_rpm, QCOM_SMD_RPM_ACTIVE_STATE, |
420 | QCOM_SMD_RPM_MISC_CLK, |
421 | QCOM_RPM_SCALING_ENABLE_ID, buf: &req, count: sizeof(req)); |
422 | if (ret) { |
423 | pr_err("RPM clock scaling (active set) not enabled!\n" ); |
424 | return ret; |
425 | } |
426 | |
427 | pr_debug("%s: RPM clock scaling is enabled\n" , __func__); |
428 | return 0; |
429 | } |
430 | |
431 | static const struct clk_ops clk_smd_rpm_ops = { |
432 | .prepare = clk_smd_rpm_prepare, |
433 | .unprepare = clk_smd_rpm_unprepare, |
434 | .set_rate = clk_smd_rpm_set_rate, |
435 | .round_rate = clk_smd_rpm_round_rate, |
436 | .recalc_rate = clk_smd_rpm_recalc_rate, |
437 | }; |
438 | |
439 | static const struct clk_ops clk_smd_rpm_branch_ops = { |
440 | .prepare = clk_smd_rpm_prepare, |
441 | .unprepare = clk_smd_rpm_unprepare, |
442 | .recalc_rate = clk_smd_rpm_recalc_rate, |
443 | }; |
444 | |
445 | /* Disabling BI_TCXO_AO could gate the root clock source of the entire system. */ |
446 | DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000, CLK_IS_CRITICAL); |
447 | DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); |
448 | DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1); |
449 | DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1, 0); |
450 | |
451 | DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); |
452 | |
453 | DEFINE_CLK_SMD_RPM_BRANCH(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); |
454 | DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); |
455 | DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); |
456 | DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); |
457 | |
458 | DEFINE_CLK_SMD_RPM_BUS_A(pcnoc, 0, 19200000, CLK_IS_CRITICAL); |
459 | DEFINE_CLK_SMD_RPM_BUS(snoc, 1); |
460 | DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2); |
461 | DEFINE_CLK_SMD_RPM_BUS(cnoc, 2); |
462 | DEFINE_CLK_SMD_RPM_BUS(mmssnoc_ahb, 3); |
463 | DEFINE_CLK_SMD_RPM_BUS(snoc_periph, 0); |
464 | DEFINE_CLK_SMD_RPM_BUS(cnoc, 1); |
465 | DEFINE_CLK_SMD_RPM_BUS(snoc, 2); |
466 | DEFINE_CLK_SMD_RPM_BUS(snoc_lpass, 5); |
467 | |
468 | DEFINE_CLK_SMD_RPM(bimc, QCOM_SMD_RPM_MEM_CLK, 0); |
469 | DEFINE_CLK_SMD_RPM(cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1); |
470 | DEFINE_CLK_SMD_RPM_CLK_SRC(gfx3d, QCOM_SMD_RPM_MEM_CLK, 1); |
471 | DEFINE_CLK_SMD_RPM(ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2); |
472 | DEFINE_CLK_SMD_RPM(bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2); |
473 | |
474 | DEFINE_CLK_SMD_RPM(ce1, QCOM_SMD_RPM_CE_CLK, 0); |
475 | DEFINE_CLK_SMD_RPM(ce2, QCOM_SMD_RPM_CE_CLK, 1); |
476 | DEFINE_CLK_SMD_RPM(ce3, QCOM_SMD_RPM_CE_CLK, 2); |
477 | |
478 | DEFINE_CLK_SMD_RPM(ipa, QCOM_SMD_RPM_IPA_CLK, 0); |
479 | |
480 | DEFINE_CLK_SMD_RPM(hwkm, QCOM_SMD_RPM_HWKM_CLK, 0); |
481 | |
482 | DEFINE_CLK_SMD_RPM(mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0); |
483 | DEFINE_CLK_SMD_RPM(mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0); |
484 | DEFINE_CLK_SMD_RPM(mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1); |
485 | |
486 | DEFINE_CLK_SMD_RPM(pka, QCOM_SMD_RPM_PKA_CLK, 0); |
487 | |
488 | DEFINE_CLK_SMD_RPM(qpic, QCOM_SMD_RPM_QPIC_CLK, 0); |
489 | |
490 | DEFINE_CLK_SMD_RPM(qup, QCOM_SMD_RPM_QUP_CLK, 0); |
491 | |
492 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk1, 1, 19200000); |
493 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk2, 2, 19200000); |
494 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk1, 1, 19200000); |
495 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk2, 2, 19200000); |
496 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk3, 3, 19200000); |
497 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk1, 4, 19200000); |
498 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk2, 5, 19200000); |
499 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk3, 6, 19200000); |
500 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk, 8, 19200000); |
501 | |
502 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(38m4_, rf_clk3, 6, 38400000); |
503 | |
504 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d0, 1, 19200000); |
505 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d1, 2, 19200000); |
506 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a0, 4, 19200000); |
507 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a1, 5, 19200000); |
508 | DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a2, 6, 19200000); |
509 | |
510 | DEFINE_CLK_SMD_RPM_XO_BUFFER(diff_clk, 7, 19200000); |
511 | DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000); |
512 | DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000); |
513 | DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000); |
514 | |
515 | static const struct clk_smd_rpm *bimc_pcnoc_icc_clks[] = { |
516 | &clk_smd_rpm_bimc_clk, |
517 | &clk_smd_rpm_bus_0_pcnoc_clk, |
518 | }; |
519 | |
520 | static const struct clk_smd_rpm *bimc_pcnoc_snoc_icc_clks[] = { |
521 | &clk_smd_rpm_bimc_clk, |
522 | &clk_smd_rpm_bus_0_pcnoc_clk, |
523 | &clk_smd_rpm_bus_1_snoc_clk, |
524 | }; |
525 | |
526 | static const struct clk_smd_rpm *bimc_pcnoc_snoc_smmnoc_icc_clks[] = { |
527 | &clk_smd_rpm_bimc_clk, |
528 | &clk_smd_rpm_bus_0_pcnoc_clk, |
529 | &clk_smd_rpm_bus_1_snoc_clk, |
530 | &clk_smd_rpm_bus_2_sysmmnoc_clk, |
531 | }; |
532 | |
533 | static const struct clk_smd_rpm *bimc_pcnoc_snoc_cnoc_ocmem_icc_clks[] = { |
534 | &clk_smd_rpm_bimc_clk, |
535 | &clk_smd_rpm_bus_0_pcnoc_clk, |
536 | &clk_smd_rpm_bus_1_snoc_clk, |
537 | &clk_smd_rpm_bus_2_cnoc_clk, |
538 | &clk_smd_rpm_ocmemgx_clk, |
539 | }; |
540 | |
541 | static const struct clk_smd_rpm *msm8996_icc_clks[] = { |
542 | &clk_smd_rpm_bimc_clk, |
543 | &clk_smd_rpm_branch_aggre1_noc_clk, |
544 | &clk_smd_rpm_branch_aggre2_noc_clk, |
545 | &clk_smd_rpm_bus_0_pcnoc_clk, |
546 | &clk_smd_rpm_bus_1_snoc_clk, |
547 | &clk_smd_rpm_bus_2_cnoc_clk, |
548 | &clk_smd_rpm_mmssnoc_axi_rpm_clk, |
549 | }; |
550 | |
551 | static const struct clk_smd_rpm *msm8998_icc_clks[] = { |
552 | &clk_smd_rpm_aggre1_noc_clk, |
553 | &clk_smd_rpm_aggre2_noc_clk, |
554 | &clk_smd_rpm_bimc_clk, |
555 | &clk_smd_rpm_bus_1_snoc_clk, |
556 | &clk_smd_rpm_bus_2_cnoc_clk, |
557 | &clk_smd_rpm_mmssnoc_axi_rpm_clk, |
558 | }; |
559 | |
560 | static const struct clk_smd_rpm *sdm660_icc_clks[] = { |
561 | &clk_smd_rpm_aggre2_noc_clk, |
562 | &clk_smd_rpm_bimc_clk, |
563 | &clk_smd_rpm_bus_1_snoc_clk, |
564 | &clk_smd_rpm_bus_2_cnoc_clk, |
565 | &clk_smd_rpm_mmssnoc_axi_rpm_clk, |
566 | }; |
567 | |
568 | static const struct clk_smd_rpm *sm_qnoc_icc_clks[] = { |
569 | &clk_smd_rpm_bimc_clk, |
570 | &clk_smd_rpm_bus_1_cnoc_clk, |
571 | &clk_smd_rpm_mmnrt_clk, |
572 | &clk_smd_rpm_mmrt_clk, |
573 | &clk_smd_rpm_qup_clk, |
574 | &clk_smd_rpm_bus_2_snoc_clk, |
575 | }; |
576 | |
577 | static const struct clk_smd_rpm *qcm2290_icc_clks[] = { |
578 | &clk_smd_rpm_bimc_clk, |
579 | &clk_smd_rpm_bus_1_cnoc_clk, |
580 | &clk_smd_rpm_mmnrt_clk, |
581 | &clk_smd_rpm_mmrt_clk, |
582 | &clk_smd_rpm_qup_clk, |
583 | &clk_smd_rpm_bus_2_snoc_clk, |
584 | &clk_smd_rpm_cpuss_gnoc_clk, |
585 | }; |
586 | |
587 | static struct clk_smd_rpm *msm8909_clks[] = { |
588 | [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, |
589 | [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, |
590 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
591 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
592 | [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, |
593 | [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, |
594 | [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, |
595 | [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, |
596 | [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, |
597 | [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, |
598 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
599 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
600 | [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, |
601 | [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, |
602 | [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, |
603 | [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, |
604 | [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, |
605 | [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, |
606 | [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, |
607 | [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, |
608 | }; |
609 | |
610 | static const struct rpm_smd_clk_desc rpm_clk_msm8909 = { |
611 | .clks = msm8909_clks, |
612 | .num_clks = ARRAY_SIZE(msm8909_clks), |
613 | .icc_clks = bimc_pcnoc_snoc_icc_clks, |
614 | .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), |
615 | }; |
616 | |
617 | static struct clk_smd_rpm *msm8916_clks[] = { |
618 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
619 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
620 | [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, |
621 | [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, |
622 | [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, |
623 | [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, |
624 | [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, |
625 | [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, |
626 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
627 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
628 | [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, |
629 | [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, |
630 | [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, |
631 | [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, |
632 | [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, |
633 | [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, |
634 | [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, |
635 | [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, |
636 | }; |
637 | |
638 | static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { |
639 | .clks = msm8916_clks, |
640 | .num_clks = ARRAY_SIZE(msm8916_clks), |
641 | .icc_clks = bimc_pcnoc_snoc_icc_clks, |
642 | .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), |
643 | }; |
644 | |
645 | static struct clk_smd_rpm *msm8917_clks[] = { |
646 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
647 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
648 | [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, |
649 | [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, |
650 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
651 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
652 | [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, |
653 | [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, |
654 | [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, |
655 | [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, |
656 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
657 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
658 | [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, |
659 | [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, |
660 | [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, |
661 | [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, |
662 | [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, |
663 | [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, |
664 | }; |
665 | |
666 | static const struct rpm_smd_clk_desc rpm_clk_msm8917 = { |
667 | .clks = msm8917_clks, |
668 | .num_clks = ARRAY_SIZE(msm8917_clks), |
669 | .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, |
670 | .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), |
671 | }; |
672 | |
673 | static struct clk_smd_rpm *msm8936_clks[] = { |
674 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
675 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
676 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
677 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
678 | [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, |
679 | [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, |
680 | [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, |
681 | [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, |
682 | [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, |
683 | [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, |
684 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
685 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
686 | [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, |
687 | [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, |
688 | [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, |
689 | [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, |
690 | [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, |
691 | [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, |
692 | [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, |
693 | [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, |
694 | }; |
695 | |
696 | static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { |
697 | .clks = msm8936_clks, |
698 | .num_clks = ARRAY_SIZE(msm8936_clks), |
699 | .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, |
700 | .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), |
701 | }; |
702 | |
703 | static struct clk_smd_rpm *msm8974_clks[] = { |
704 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
705 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
706 | [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, |
707 | [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, |
708 | [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, |
709 | [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, |
710 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
711 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
712 | [RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0, |
713 | [RPM_SMD_CXO_D0_A] = &clk_smd_rpm_cxo_d0_a, |
714 | [RPM_SMD_CXO_D1] = &clk_smd_rpm_cxo_d1, |
715 | [RPM_SMD_CXO_D1_A] = &clk_smd_rpm_cxo_d1_a, |
716 | [RPM_SMD_CXO_A0] = &clk_smd_rpm_cxo_a0, |
717 | [RPM_SMD_CXO_A0_A] = &clk_smd_rpm_cxo_a0_a, |
718 | [RPM_SMD_CXO_A1] = &clk_smd_rpm_cxo_a1, |
719 | [RPM_SMD_CXO_A1_A] = &clk_smd_rpm_cxo_a1_a, |
720 | [RPM_SMD_CXO_A2] = &clk_smd_rpm_cxo_a2, |
721 | [RPM_SMD_CXO_A2_A] = &clk_smd_rpm_cxo_a2_a, |
722 | [RPM_SMD_DIFF_CLK] = &clk_smd_rpm_diff_clk, |
723 | [RPM_SMD_DIFF_A_CLK] = &clk_smd_rpm_diff_clk_a, |
724 | [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, |
725 | [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, |
726 | [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, |
727 | [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, |
728 | [RPM_SMD_CXO_D0_PIN] = &clk_smd_rpm_cxo_d0_pin, |
729 | [RPM_SMD_CXO_D0_A_PIN] = &clk_smd_rpm_cxo_d0_a_pin, |
730 | [RPM_SMD_CXO_D1_PIN] = &clk_smd_rpm_cxo_d1_pin, |
731 | [RPM_SMD_CXO_D1_A_PIN] = &clk_smd_rpm_cxo_d1_a_pin, |
732 | [RPM_SMD_CXO_A0_PIN] = &clk_smd_rpm_cxo_a0_pin, |
733 | [RPM_SMD_CXO_A0_A_PIN] = &clk_smd_rpm_cxo_a0_a_pin, |
734 | [RPM_SMD_CXO_A1_PIN] = &clk_smd_rpm_cxo_a1_pin, |
735 | [RPM_SMD_CXO_A1_A_PIN] = &clk_smd_rpm_cxo_a1_a_pin, |
736 | [RPM_SMD_CXO_A2_PIN] = &clk_smd_rpm_cxo_a2_pin, |
737 | [RPM_SMD_CXO_A2_A_PIN] = &clk_smd_rpm_cxo_a2_a_pin, |
738 | }; |
739 | |
740 | static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { |
741 | .clks = msm8974_clks, |
742 | .num_clks = ARRAY_SIZE(msm8974_clks), |
743 | .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, |
744 | .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), |
745 | .scaling_before_handover = true, |
746 | }; |
747 | |
748 | static struct clk_smd_rpm *msm8976_clks[] = { |
749 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
750 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
751 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
752 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
753 | [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, |
754 | [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, |
755 | [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, |
756 | [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, |
757 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
758 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
759 | [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, |
760 | [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, |
761 | [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, |
762 | [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, |
763 | [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, |
764 | [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, |
765 | [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, |
766 | [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, |
767 | }; |
768 | |
769 | static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { |
770 | .clks = msm8976_clks, |
771 | .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, |
772 | .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), |
773 | }; |
774 | |
775 | static struct clk_smd_rpm *msm8992_clks[] = { |
776 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
777 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
778 | [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, |
779 | [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, |
780 | [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, |
781 | [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, |
782 | [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, |
783 | [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, |
784 | [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, |
785 | [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, |
786 | [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, |
787 | [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, |
788 | [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, |
789 | [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, |
790 | [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, |
791 | [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, |
792 | [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, |
793 | [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, |
794 | [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, |
795 | [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, |
796 | [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, |
797 | [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, |
798 | [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, |
799 | [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, |
800 | [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, |
801 | [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, |
802 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
803 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
804 | [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, |
805 | [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, |
806 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
807 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
808 | [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, |
809 | [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, |
810 | [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, |
811 | [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, |
812 | [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, |
813 | [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, |
814 | [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, |
815 | [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, |
816 | }; |
817 | |
818 | static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { |
819 | .clks = msm8992_clks, |
820 | .num_clks = ARRAY_SIZE(msm8992_clks), |
821 | .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, |
822 | .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), |
823 | }; |
824 | |
825 | static struct clk_smd_rpm *msm8994_clks[] = { |
826 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
827 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
828 | [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, |
829 | [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, |
830 | [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, |
831 | [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, |
832 | [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, |
833 | [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, |
834 | [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, |
835 | [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, |
836 | [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, |
837 | [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, |
838 | [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, |
839 | [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, |
840 | [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, |
841 | [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, |
842 | [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, |
843 | [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, |
844 | [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, |
845 | [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, |
846 | [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, |
847 | [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, |
848 | [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, |
849 | [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, |
850 | [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, |
851 | [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, |
852 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
853 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
854 | [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, |
855 | [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, |
856 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
857 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
858 | [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, |
859 | [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, |
860 | [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, |
861 | [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, |
862 | [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, |
863 | [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, |
864 | [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, |
865 | [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, |
866 | [RPM_SMD_CE3_CLK] = &clk_smd_rpm_ce3_clk, |
867 | [RPM_SMD_CE3_A_CLK] = &clk_smd_rpm_ce3_a_clk, |
868 | }; |
869 | |
870 | static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { |
871 | .clks = msm8994_clks, |
872 | .num_clks = ARRAY_SIZE(msm8994_clks), |
873 | .icc_clks = bimc_pcnoc_snoc_cnoc_ocmem_icc_clks, |
874 | .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_cnoc_ocmem_icc_clks), |
875 | }; |
876 | |
877 | static struct clk_smd_rpm *msm8996_clks[] = { |
878 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
879 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
880 | [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, |
881 | [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, |
882 | [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, |
883 | [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, |
884 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
885 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
886 | [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, |
887 | [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, |
888 | [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, |
889 | [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, |
890 | [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, |
891 | [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, |
892 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
893 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
894 | [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, |
895 | [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, |
896 | [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, |
897 | [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, |
898 | [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, |
899 | [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, |
900 | [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, |
901 | [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, |
902 | [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, |
903 | [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, |
904 | [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, |
905 | [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, |
906 | [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, |
907 | [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, |
908 | [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, |
909 | [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, |
910 | }; |
911 | |
912 | static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { |
913 | .clks = msm8996_clks, |
914 | .num_clks = ARRAY_SIZE(msm8996_clks), |
915 | .icc_clks = msm8996_icc_clks, |
916 | .num_icc_clks = ARRAY_SIZE(msm8996_icc_clks), |
917 | }; |
918 | |
919 | static struct clk_smd_rpm *qcs404_clks[] = { |
920 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
921 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
922 | [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, |
923 | [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, |
924 | [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, |
925 | [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, |
926 | [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, |
927 | [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, |
928 | [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, |
929 | [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, |
930 | [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, |
931 | [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, |
932 | [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, |
933 | [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, |
934 | [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, |
935 | [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, |
936 | [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, |
937 | [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, |
938 | [RPM_SMD_LN_BB_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_pin, |
939 | [RPM_SMD_LN_BB_A_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_a_pin, |
940 | }; |
941 | |
942 | static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { |
943 | .clks = qcs404_clks, |
944 | .num_clks = ARRAY_SIZE(qcs404_clks), |
945 | .icc_clks = bimc_pcnoc_snoc_icc_clks, |
946 | .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_icc_clks), |
947 | }; |
948 | |
949 | static struct clk_smd_rpm *msm8998_clks[] = { |
950 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
951 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
952 | [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, |
953 | [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, |
954 | [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, |
955 | [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, |
956 | [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, |
957 | [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, |
958 | [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, |
959 | [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, |
960 | [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, |
961 | [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, |
962 | [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, |
963 | [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, |
964 | [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, |
965 | [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, |
966 | [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, |
967 | [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, |
968 | [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, |
969 | [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, |
970 | [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, |
971 | [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, |
972 | [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, |
973 | [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, |
974 | [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, |
975 | [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, |
976 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
977 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
978 | [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, |
979 | [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, |
980 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
981 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
982 | [RPM_SMD_RF_CLK3] = &clk_smd_rpm_rf_clk3, |
983 | [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_rf_clk3_a, |
984 | [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, |
985 | [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, |
986 | [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, |
987 | [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, |
988 | [RPM_SMD_RF_CLK3_PIN] = &clk_smd_rpm_rf_clk3_pin, |
989 | [RPM_SMD_RF_CLK3_A_PIN] = &clk_smd_rpm_rf_clk3_a_pin, |
990 | }; |
991 | |
992 | static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { |
993 | .clks = msm8998_clks, |
994 | .num_clks = ARRAY_SIZE(msm8998_clks), |
995 | .icc_clks = msm8998_icc_clks, |
996 | .num_icc_clks = ARRAY_SIZE(msm8998_icc_clks), |
997 | }; |
998 | |
999 | static struct clk_smd_rpm *sdm660_clks[] = { |
1000 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
1001 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
1002 | [RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, |
1003 | [RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, |
1004 | [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, |
1005 | [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, |
1006 | [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, |
1007 | [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, |
1008 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
1009 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
1010 | [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, |
1011 | [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, |
1012 | [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, |
1013 | [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, |
1014 | [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk1, |
1015 | [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk1_a, |
1016 | [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, |
1017 | [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, |
1018 | [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, |
1019 | [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, |
1020 | [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, |
1021 | [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, |
1022 | [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, |
1023 | [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, |
1024 | [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, |
1025 | [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, |
1026 | [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, |
1027 | [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, |
1028 | }; |
1029 | |
1030 | static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { |
1031 | .clks = sdm660_clks, |
1032 | .num_clks = ARRAY_SIZE(sdm660_clks), |
1033 | .icc_clks = sdm660_icc_clks, |
1034 | .num_icc_clks = ARRAY_SIZE(sdm660_icc_clks), |
1035 | }; |
1036 | |
1037 | static struct clk_smd_rpm *mdm9607_clks[] = { |
1038 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
1039 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
1040 | [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, |
1041 | [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, |
1042 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
1043 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
1044 | [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, |
1045 | [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, |
1046 | [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, |
1047 | [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, |
1048 | }; |
1049 | |
1050 | static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { |
1051 | .clks = mdm9607_clks, |
1052 | .num_clks = ARRAY_SIZE(mdm9607_clks), |
1053 | .icc_clks = bimc_pcnoc_icc_clks, |
1054 | .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_icc_clks), |
1055 | }; |
1056 | |
1057 | static struct clk_smd_rpm *msm8953_clks[] = { |
1058 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
1059 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
1060 | [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, |
1061 | [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, |
1062 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, |
1063 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, |
1064 | [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, |
1065 | [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, |
1066 | [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, |
1067 | [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, |
1068 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
1069 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
1070 | [RPM_SMD_RF_CLK3] = &clk_smd_rpm_ln_bb_clk, |
1071 | [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_ln_bb_clk_a, |
1072 | [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, |
1073 | [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, |
1074 | [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, |
1075 | [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, |
1076 | [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, |
1077 | [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, |
1078 | }; |
1079 | |
1080 | static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { |
1081 | .clks = msm8953_clks, |
1082 | .num_clks = ARRAY_SIZE(msm8953_clks), |
1083 | .icc_clks = bimc_pcnoc_snoc_smmnoc_icc_clks, |
1084 | .num_icc_clks = ARRAY_SIZE(bimc_pcnoc_snoc_smmnoc_icc_clks), |
1085 | }; |
1086 | |
1087 | static struct clk_smd_rpm *sm6125_clks[] = { |
1088 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
1089 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
1090 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, |
1091 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, |
1092 | [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, |
1093 | [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, |
1094 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
1095 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
1096 | [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, |
1097 | [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, |
1098 | [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, |
1099 | [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, |
1100 | [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, |
1101 | [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, |
1102 | [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, |
1103 | [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, |
1104 | [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, |
1105 | [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, |
1106 | [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, |
1107 | [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, |
1108 | [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, |
1109 | [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, |
1110 | }; |
1111 | |
1112 | static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { |
1113 | .clks = sm6125_clks, |
1114 | .num_clks = ARRAY_SIZE(sm6125_clks), |
1115 | .icc_clks = sm_qnoc_icc_clks, |
1116 | .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) |
1117 | }; |
1118 | |
1119 | /* SM6115 */ |
1120 | static struct clk_smd_rpm *sm6115_clks[] = { |
1121 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
1122 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
1123 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, |
1124 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, |
1125 | [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, |
1126 | [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, |
1127 | [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, |
1128 | [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, |
1129 | [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, |
1130 | [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, |
1131 | [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, |
1132 | [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, |
1133 | [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, |
1134 | [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, |
1135 | [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, |
1136 | [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, |
1137 | [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, |
1138 | [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, |
1139 | [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, |
1140 | [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, |
1141 | }; |
1142 | |
1143 | static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { |
1144 | .clks = sm6115_clks, |
1145 | .num_clks = ARRAY_SIZE(sm6115_clks), |
1146 | .icc_clks = sm_qnoc_icc_clks, |
1147 | .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) |
1148 | }; |
1149 | |
1150 | static struct clk_smd_rpm *sm6375_clks[] = { |
1151 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
1152 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
1153 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, |
1154 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, |
1155 | [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, |
1156 | [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, |
1157 | [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, |
1158 | [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, |
1159 | [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, |
1160 | [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, |
1161 | [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, |
1162 | [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, |
1163 | [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, |
1164 | [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, |
1165 | [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, |
1166 | [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, |
1167 | [RPM_SMD_BIMC_FREQ_LOG] = &clk_smd_rpm_branch_bimc_freq_log, |
1168 | }; |
1169 | |
1170 | static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { |
1171 | .clks = sm6375_clks, |
1172 | .num_clks = ARRAY_SIZE(sm6375_clks), |
1173 | .icc_clks = sm_qnoc_icc_clks, |
1174 | .num_icc_clks = ARRAY_SIZE(sm_qnoc_icc_clks) |
1175 | }; |
1176 | |
1177 | static struct clk_smd_rpm *qcm2290_clks[] = { |
1178 | [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, |
1179 | [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, |
1180 | [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, |
1181 | [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, |
1182 | [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, |
1183 | [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, |
1184 | [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3, |
1185 | [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a, |
1186 | [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, |
1187 | [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, |
1188 | [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, |
1189 | [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, |
1190 | [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, |
1191 | [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, |
1192 | [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, |
1193 | [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, |
1194 | [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, |
1195 | [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, |
1196 | [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, |
1197 | [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, |
1198 | [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, |
1199 | [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, |
1200 | [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, |
1201 | [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, |
1202 | }; |
1203 | |
1204 | static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = { |
1205 | .clks = qcm2290_clks, |
1206 | .num_clks = ARRAY_SIZE(qcm2290_clks), |
1207 | .icc_clks = qcm2290_icc_clks, |
1208 | .num_icc_clks = ARRAY_SIZE(qcm2290_icc_clks) |
1209 | }; |
1210 | |
1211 | static const struct of_device_id rpm_smd_clk_match_table[] = { |
1212 | { .compatible = "qcom,rpmcc-mdm9607" , .data = &rpm_clk_mdm9607 }, |
1213 | { .compatible = "qcom,rpmcc-msm8226" , .data = &rpm_clk_msm8974 }, |
1214 | { .compatible = "qcom,rpmcc-msm8909" , .data = &rpm_clk_msm8909 }, |
1215 | { .compatible = "qcom,rpmcc-msm8916" , .data = &rpm_clk_msm8916 }, |
1216 | { .compatible = "qcom,rpmcc-msm8917" , .data = &rpm_clk_msm8917 }, |
1217 | { .compatible = "qcom,rpmcc-msm8936" , .data = &rpm_clk_msm8936 }, |
1218 | { .compatible = "qcom,rpmcc-msm8953" , .data = &rpm_clk_msm8953 }, |
1219 | { .compatible = "qcom,rpmcc-msm8974" , .data = &rpm_clk_msm8974 }, |
1220 | { .compatible = "qcom,rpmcc-msm8976" , .data = &rpm_clk_msm8976 }, |
1221 | { .compatible = "qcom,rpmcc-msm8992" , .data = &rpm_clk_msm8992 }, |
1222 | { .compatible = "qcom,rpmcc-msm8994" , .data = &rpm_clk_msm8994 }, |
1223 | { .compatible = "qcom,rpmcc-msm8996" , .data = &rpm_clk_msm8996 }, |
1224 | { .compatible = "qcom,rpmcc-msm8998" , .data = &rpm_clk_msm8998 }, |
1225 | { .compatible = "qcom,rpmcc-qcm2290" , .data = &rpm_clk_qcm2290 }, |
1226 | { .compatible = "qcom,rpmcc-qcs404" , .data = &rpm_clk_qcs404 }, |
1227 | { .compatible = "qcom,rpmcc-sdm660" , .data = &rpm_clk_sdm660 }, |
1228 | { .compatible = "qcom,rpmcc-sm6115" , .data = &rpm_clk_sm6115 }, |
1229 | { .compatible = "qcom,rpmcc-sm6125" , .data = &rpm_clk_sm6125 }, |
1230 | { .compatible = "qcom,rpmcc-sm6375" , .data = &rpm_clk_sm6375 }, |
1231 | { } |
1232 | }; |
1233 | MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); |
1234 | |
1235 | static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec, |
1236 | void *data) |
1237 | { |
1238 | const struct rpm_smd_clk_desc *desc = data; |
1239 | unsigned int idx = clkspec->args[0]; |
1240 | |
1241 | if (idx >= desc->num_clks) { |
1242 | pr_err("%s: invalid index %u\n" , __func__, idx); |
1243 | return ERR_PTR(error: -EINVAL); |
1244 | } |
1245 | |
1246 | return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(error: -ENOENT); |
1247 | } |
1248 | |
1249 | static void rpm_smd_unregister_icc(void *data) |
1250 | { |
1251 | struct platform_device *icc_pdev = data; |
1252 | |
1253 | platform_device_unregister(icc_pdev); |
1254 | } |
1255 | |
1256 | static int rpm_smd_clk_probe(struct platform_device *pdev) |
1257 | { |
1258 | int ret; |
1259 | size_t num_clks, i; |
1260 | struct clk_smd_rpm **rpm_smd_clks; |
1261 | const struct rpm_smd_clk_desc *desc; |
1262 | struct platform_device *icc_pdev; |
1263 | |
1264 | rpmcc_smd_rpm = dev_get_drvdata(dev: pdev->dev.parent); |
1265 | if (!rpmcc_smd_rpm) { |
1266 | dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n" ); |
1267 | return -ENODEV; |
1268 | } |
1269 | |
1270 | desc = of_device_get_match_data(dev: &pdev->dev); |
1271 | if (!desc) |
1272 | return -EINVAL; |
1273 | |
1274 | rpm_smd_clks = desc->clks; |
1275 | num_clks = desc->num_clks; |
1276 | |
1277 | if (desc->scaling_before_handover) { |
1278 | ret = clk_smd_rpm_enable_scaling(); |
1279 | if (ret) |
1280 | goto err; |
1281 | } |
1282 | |
1283 | for (i = 0; i < num_clks; i++) { |
1284 | if (!rpm_smd_clks[i]) |
1285 | continue; |
1286 | |
1287 | ret = clk_smd_rpm_handoff(r: rpm_smd_clks[i]); |
1288 | if (ret) |
1289 | goto err; |
1290 | } |
1291 | |
1292 | for (i = 0; i < desc->num_icc_clks; i++) { |
1293 | if (!desc->icc_clks[i]) |
1294 | continue; |
1295 | |
1296 | ret = clk_smd_rpm_handoff(r: desc->icc_clks[i]); |
1297 | if (ret) |
1298 | goto err; |
1299 | } |
1300 | |
1301 | if (!desc->scaling_before_handover) { |
1302 | ret = clk_smd_rpm_enable_scaling(); |
1303 | if (ret) |
1304 | goto err; |
1305 | } |
1306 | |
1307 | for (i = 0; i < num_clks; i++) { |
1308 | if (!rpm_smd_clks[i]) |
1309 | continue; |
1310 | |
1311 | ret = devm_clk_hw_register(dev: &pdev->dev, hw: &rpm_smd_clks[i]->hw); |
1312 | if (ret) |
1313 | goto err; |
1314 | } |
1315 | |
1316 | ret = devm_of_clk_add_hw_provider(dev: &pdev->dev, get: qcom_smdrpm_clk_hw_get, |
1317 | data: (void *)desc); |
1318 | if (ret) |
1319 | goto err; |
1320 | |
1321 | icc_pdev = platform_device_register_data(parent: pdev->dev.parent, |
1322 | name: "icc_smd_rpm" , id: -1, NULL, size: 0); |
1323 | if (IS_ERR(ptr: icc_pdev)) { |
1324 | dev_err(&pdev->dev, "Failed to register icc_smd_rpm device: %pE\n" , |
1325 | icc_pdev); |
1326 | /* No need to unregister clocks because of this */ |
1327 | } else { |
1328 | ret = devm_add_action_or_reset(&pdev->dev, rpm_smd_unregister_icc, |
1329 | icc_pdev); |
1330 | if (ret) |
1331 | goto err; |
1332 | } |
1333 | |
1334 | return 0; |
1335 | err: |
1336 | dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n" , ret); |
1337 | return ret; |
1338 | } |
1339 | |
1340 | static struct platform_driver rpm_smd_clk_driver = { |
1341 | .driver = { |
1342 | .name = "qcom-clk-smd-rpm" , |
1343 | .of_match_table = rpm_smd_clk_match_table, |
1344 | }, |
1345 | .probe = rpm_smd_clk_probe, |
1346 | }; |
1347 | |
1348 | static int __init rpm_smd_clk_init(void) |
1349 | { |
1350 | return platform_driver_register(&rpm_smd_clk_driver); |
1351 | } |
1352 | core_initcall(rpm_smd_clk_init); |
1353 | |
1354 | static void __exit rpm_smd_clk_exit(void) |
1355 | { |
1356 | platform_driver_unregister(&rpm_smd_clk_driver); |
1357 | } |
1358 | module_exit(rpm_smd_clk_exit); |
1359 | |
1360 | MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver" ); |
1361 | MODULE_LICENSE("GPL v2" ); |
1362 | MODULE_ALIAS("platform:qcom-clk-smd-rpm" ); |
1363 | |