1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4	* Copyright (c) 2020-2021, Linaro Limited
5	*/
6
7	#include <linux/clk-provider.h>
8	#include <linux/module.h>
9	#include <linux/platform_device.h>
10	#include <linux/regmap.h>
11
12	#include <dt-bindings/clock/qcom,gcc-sm8350.h>
13
14	#include "clk-alpha-pll.h"
15	#include "clk-branch.h"
16	#include "clk-rcg.h"
17	#include "clk-regmap.h"
18	#include "clk-regmap-divider.h"
19	#include "clk-regmap-mux.h"
20	#include "clk-regmap-phy-mux.h"
21	#include "gdsc.h"
22	#include "reset.h"
23
24	enum {
25	P_BI_TCXO,
26	P_GCC_GPLL0_OUT_EVEN,
27	P_GCC_GPLL0_OUT_MAIN,
28	P_GCC_GPLL4_OUT_MAIN,
29	P_GCC_GPLL9_OUT_MAIN,
30	P_PCIE_0_PIPE_CLK,
31	P_PCIE_1_PIPE_CLK,
32	P_SLEEP_CLK,
33	P_UFS_CARD_RX_SYMBOL_0_CLK,
34	P_UFS_CARD_RX_SYMBOL_1_CLK,
35	P_UFS_CARD_TX_SYMBOL_0_CLK,
36	P_UFS_PHY_RX_SYMBOL_0_CLK,
37	P_UFS_PHY_RX_SYMBOL_1_CLK,
38	P_UFS_PHY_TX_SYMBOL_0_CLK,
39	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
40	P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
41	};
42
43	static struct clk_alpha_pll gcc_gpll0 = {
44	.offset = 0x0,
45	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
46	.clkr = {
47	.enable_reg = 0x52018,
48	.enable_mask = BIT(0),
49	.hw.init = &(struct clk_init_data){
50	.name = "gcc_gpll0",
51	.parent_data = &(const struct clk_parent_data){
52	.fw_name = "bi_tcxo",
53	},
54	.num_parents = 1,
55	.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
56	},
57	},
58	};
59
60	static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
61	{ 0x1, 2 },
62	{ }
63	};
64
65	static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
66	.offset = 0x0,
67	.post_div_shift = 8,
68	.post_div_table = post_div_table_gcc_gpll0_out_even,
69	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
70	.width = 4,
71	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
72	.clkr.hw.init = &(struct clk_init_data){
73	.name = "gcc_gpll0_out_even",
74	.parent_hws = (const struct clk_hw*[]){
75	&gcc_gpll0.clkr.hw,
76	},
77	.num_parents = 1,
78	.ops = &clk_alpha_pll_postdiv_lucid_5lpe_ops,
79	},
80	};
81
82	static struct clk_alpha_pll gcc_gpll4 = {
83	.offset = 0x76000,
84	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
85	.clkr = {
86	.enable_reg = 0x52018,
87	.enable_mask = BIT(4),
88	.hw.init = &(struct clk_init_data){
89	.name = "gcc_gpll4",
90	.parent_data = &(const struct clk_parent_data){
91	.fw_name = "bi_tcxo",
92	.name = "bi_tcxo",
93	},
94	.num_parents = 1,
95	.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
96	},
97	},
98	};
99
100	static struct clk_alpha_pll gcc_gpll9 = {
101	.offset = 0x1c000,
102	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
103	.clkr = {
104	.enable_reg = 0x52018,
105	.enable_mask = BIT(9),
106	.hw.init = &(struct clk_init_data){
107	.name = "gcc_gpll9",
108	.parent_data = &(const struct clk_parent_data){
109	.fw_name = "bi_tcxo",
110	.name = "bi_tcxo",
111	},
112	.num_parents = 1,
113	.ops = &clk_alpha_pll_fixed_lucid_5lpe_ops,
114	},
115	},
116	};
117
118	static const struct parent_map gcc_parent_map_0[] = {
119	{ P_BI_TCXO, 0 },
120	{ P_GCC_GPLL0_OUT_MAIN, 1 },
121	{ P_GCC_GPLL0_OUT_EVEN, 6 },
122	};
123
124	static const struct clk_parent_data gcc_parent_data_0[] = {
125	{ .fw_name = "bi_tcxo" },
126	{ .hw = &gcc_gpll0.clkr.hw },
127	{ .hw = &gcc_gpll0_out_even.clkr.hw },
128	};
129
130	static const struct parent_map gcc_parent_map_1[] = {
131	{ P_BI_TCXO, 0 },
132	{ P_GCC_GPLL0_OUT_MAIN, 1 },
133	{ P_SLEEP_CLK, 5 },
134	{ P_GCC_GPLL0_OUT_EVEN, 6 },
135	};
136
137	static const struct clk_parent_data gcc_parent_data_1[] = {
138	{ .fw_name = "bi_tcxo" },
139	{ .hw = &gcc_gpll0.clkr.hw },
140	{ .fw_name = "sleep_clk" },
141	{ .hw = &gcc_gpll0_out_even.clkr.hw },
142	};
143
144	static const struct parent_map gcc_parent_map_2[] = {
145	{ P_BI_TCXO, 0 },
146	{ P_SLEEP_CLK, 5 },
147	};
148
149	static const struct clk_parent_data gcc_parent_data_2[] = {
150	{ .fw_name = "bi_tcxo" },
151	{ .fw_name = "sleep_clk" },
152	};
153
154	static const struct parent_map gcc_parent_map_3[] = {
155	{ P_BI_TCXO, 0 },
156	};
157
158	static const struct clk_parent_data gcc_parent_data_3[] = {
159	{ .fw_name = "bi_tcxo" },
160	};
161
162	static const struct parent_map gcc_parent_map_6[] = {
163	{ P_BI_TCXO, 0 },
164	{ P_GCC_GPLL0_OUT_MAIN, 1 },
165	{ P_GCC_GPLL9_OUT_MAIN, 2 },
166	{ P_GCC_GPLL4_OUT_MAIN, 5 },
167	{ P_GCC_GPLL0_OUT_EVEN, 6 },
168	};
169
170	static const struct clk_parent_data gcc_parent_data_6[] = {
171	{ .fw_name = "bi_tcxo" },
172	{ .hw = &gcc_gpll0.clkr.hw },
173	{ .hw = &gcc_gpll9.clkr.hw },
174	{ .hw = &gcc_gpll4.clkr.hw },
175	{ .hw = &gcc_gpll0_out_even.clkr.hw },
176	};
177
178	static const struct parent_map gcc_parent_map_7[] = {
179	{ P_UFS_CARD_RX_SYMBOL_0_CLK, 0 },
180	{ P_BI_TCXO, 2 },
181	};
182
183	static const struct clk_parent_data gcc_parent_data_7[] = {
184	{ .fw_name = "ufs_card_rx_symbol_0_clk" },
185	{ .fw_name = "bi_tcxo" },
186	};
187
188	static const struct parent_map gcc_parent_map_8[] = {
189	{ P_UFS_CARD_RX_SYMBOL_1_CLK, 0 },
190	{ P_BI_TCXO, 2 },
191	};
192
193	static const struct clk_parent_data gcc_parent_data_8[] = {
194	{ .fw_name = "ufs_card_rx_symbol_1_clk" },
195	{ .fw_name = "bi_tcxo" },
196	};
197
198	static const struct parent_map gcc_parent_map_9[] = {
199	{ P_UFS_CARD_TX_SYMBOL_0_CLK, 0 },
200	{ P_BI_TCXO, 2 },
201	};
202
203	static const struct clk_parent_data gcc_parent_data_9[] = {
204	{ .fw_name = "ufs_card_tx_symbol_0_clk" },
205	{ .fw_name = "bi_tcxo" },
206	};
207
208	static const struct parent_map gcc_parent_map_10[] = {
209	{ P_UFS_PHY_RX_SYMBOL_0_CLK, 0 },
210	{ P_BI_TCXO, 2 },
211	};
212
213	static const struct clk_parent_data gcc_parent_data_10[] = {
214	{ .fw_name = "ufs_phy_rx_symbol_0_clk" },
215	{ .fw_name = "bi_tcxo" },
216	};
217
218	static const struct parent_map gcc_parent_map_11[] = {
219	{ P_UFS_PHY_RX_SYMBOL_1_CLK, 0 },
220	{ P_BI_TCXO, 2 },
221	};
222
223	static const struct clk_parent_data gcc_parent_data_11[] = {
224	{ .fw_name = "ufs_phy_rx_symbol_1_clk" },
225	{ .fw_name = "bi_tcxo" },
226	};
227
228	static const struct parent_map gcc_parent_map_12[] = {
229	{ P_UFS_PHY_TX_SYMBOL_0_CLK, 0 },
230	{ P_BI_TCXO, 2 },
231	};
232
233	static const struct clk_parent_data gcc_parent_data_12[] = {
234	{ .fw_name = "ufs_phy_tx_symbol_0_clk" },
235	{ .fw_name = "bi_tcxo" },
236	};
237
238	static const struct parent_map gcc_parent_map_13[] = {
239	{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
240	{ P_BI_TCXO, 2 },
241	};
242
243	static const struct clk_parent_data gcc_parent_data_13[] = {
244	{ .fw_name = "usb3_phy_wrapper_gcc_usb30_pipe_clk" },
245	{ .fw_name = "bi_tcxo" },
246	};
247
248	static const struct parent_map gcc_parent_map_14[] = {
249	{ P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK, 0 },
250	{ P_BI_TCXO, 2 },
251	};
252
253	static const struct clk_parent_data gcc_parent_data_14[] = {
254	{ .fw_name = "usb3_uni_phy_sec_gcc_usb30_pipe_clk" },
255	{ .fw_name = "bi_tcxo" },
256	};
257
258	static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
259	.reg = 0x6b054,
260	.clkr = {
261	.hw.init = &(struct clk_init_data){
262	.name = "gcc_pcie_0_pipe_clk_src",
263	.parent_data = &(const struct clk_parent_data){
264	.fw_name = "pcie_0_pipe_clk",
265	},
266	.num_parents = 1,
267	.ops = &clk_regmap_phy_mux_ops,
268	},
269	},
270	};
271
272	static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
273	.reg = 0x8d054,
274	.clkr = {
275	.hw.init = &(struct clk_init_data){
276	.name = "gcc_pcie_1_pipe_clk_src",
277	.parent_data = &(const struct clk_parent_data){
278	.fw_name = "pcie_1_pipe_clk",
279	},
280	.num_parents = 1,
281	.ops = &clk_regmap_phy_mux_ops,
282	},
283	},
284	};
285
286	static struct clk_regmap_mux gcc_ufs_card_rx_symbol_0_clk_src = {
287	.reg = 0x75058,
288	.shift = 0,
289	.width = 2,
290	.parent_map = gcc_parent_map_7,
291	.clkr = {
292	.hw.init = &(struct clk_init_data){
293	.name = "gcc_ufs_card_rx_symbol_0_clk_src",
294	.parent_data = gcc_parent_data_7,
295	.num_parents = ARRAY_SIZE(gcc_parent_data_7),
296	.ops = &clk_regmap_mux_closest_ops,
297	},
298	},
299	};
300
301	static struct clk_regmap_mux gcc_ufs_card_rx_symbol_1_clk_src = {
302	.reg = 0x750c8,
303	.shift = 0,
304	.width = 2,
305	.parent_map = gcc_parent_map_8,
306	.clkr = {
307	.hw.init = &(struct clk_init_data){
308	.name = "gcc_ufs_card_rx_symbol_1_clk_src",
309	.parent_data = gcc_parent_data_8,
310	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
311	.ops = &clk_regmap_mux_closest_ops,
312	},
313	},
314	};
315
316	static struct clk_regmap_mux gcc_ufs_card_tx_symbol_0_clk_src = {
317	.reg = 0x75048,
318	.shift = 0,
319	.width = 2,
320	.parent_map = gcc_parent_map_9,
321	.clkr = {
322	.hw.init = &(struct clk_init_data){
323	.name = "gcc_ufs_card_tx_symbol_0_clk_src",
324	.parent_data = gcc_parent_data_9,
325	.num_parents = ARRAY_SIZE(gcc_parent_data_9),
326	.ops = &clk_regmap_mux_closest_ops,
327	},
328	},
329	};
330
331	static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
332	.reg = 0x77058,
333	.shift = 0,
334	.width = 2,
335	.parent_map = gcc_parent_map_10,
336	.clkr = {
337	.hw.init = &(struct clk_init_data){
338	.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
339	.parent_data = gcc_parent_data_10,
340	.num_parents = ARRAY_SIZE(gcc_parent_data_10),
341	.ops = &clk_regmap_mux_closest_ops,
342	},
343	},
344	};
345
346	static struct clk_regmap_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
347	.reg = 0x770c8,
348	.shift = 0,
349	.width = 2,
350	.parent_map = gcc_parent_map_11,
351	.clkr = {
352	.hw.init = &(struct clk_init_data){
353	.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
354	.parent_data = gcc_parent_data_11,
355	.num_parents = ARRAY_SIZE(gcc_parent_data_11),
356	.ops = &clk_regmap_mux_closest_ops,
357	},
358	},
359	};
360
361	static struct clk_regmap_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
362	.reg = 0x77048,
363	.shift = 0,
364	.width = 2,
365	.parent_map = gcc_parent_map_12,
366	.clkr = {
367	.hw.init = &(struct clk_init_data){
368	.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
369	.parent_data = gcc_parent_data_12,
370	.num_parents = ARRAY_SIZE(gcc_parent_data_12),
371	.ops = &clk_regmap_mux_closest_ops,
372	},
373	},
374	};
375
376	static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
377	.reg = 0xf060,
378	.shift = 0,
379	.width = 2,
380	.parent_map = gcc_parent_map_13,
381	.clkr = {
382	.hw.init = &(struct clk_init_data){
383	.name = "gcc_usb3_prim_phy_pipe_clk_src",
384	.parent_data = gcc_parent_data_13,
385	.num_parents = ARRAY_SIZE(gcc_parent_data_13),
386	.ops = &clk_regmap_mux_closest_ops,
387	},
388	},
389	};
390
391	static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
392	.reg = 0x10060,
393	.shift = 0,
394	.width = 2,
395	.parent_map = gcc_parent_map_14,
396	.clkr = {
397	.hw.init = &(struct clk_init_data){
398	.name = "gcc_usb3_sec_phy_pipe_clk_src",
399	.parent_data = gcc_parent_data_14,
400	.num_parents = ARRAY_SIZE(gcc_parent_data_14),
401	.ops = &clk_regmap_mux_closest_ops,
402	},
403	},
404	};
405
406	static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
407	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
408	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
409	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
410	{ }
411	};
412
413	static struct clk_rcg2 gcc_gp1_clk_src = {
414	.cmd_rcgr = 0x64004,
415	.mnd_width = 8,
416	.hid_width = 5,
417	.parent_map = gcc_parent_map_1,
418	.freq_tbl = ftbl_gcc_gp1_clk_src,
419	.clkr.hw.init = &(struct clk_init_data){
420	.name = "gcc_gp1_clk_src",
421	.parent_data = gcc_parent_data_1,
422	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
423	.flags = CLK_SET_RATE_PARENT,
424	.ops = &clk_rcg2_ops,
425	},
426	};
427
428	static struct clk_rcg2 gcc_gp2_clk_src = {
429	.cmd_rcgr = 0x65004,
430	.mnd_width = 8,
431	.hid_width = 5,
432	.parent_map = gcc_parent_map_1,
433	.freq_tbl = ftbl_gcc_gp1_clk_src,
434	.clkr.hw.init = &(struct clk_init_data){
435	.name = "gcc_gp2_clk_src",
436	.parent_data = gcc_parent_data_1,
437	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
438	.flags = CLK_SET_RATE_PARENT,
439	.ops = &clk_rcg2_ops,
440	},
441	};
442
443	static struct clk_rcg2 gcc_gp3_clk_src = {
444	.cmd_rcgr = 0x66004,
445	.mnd_width = 8,
446	.hid_width = 5,
447	.parent_map = gcc_parent_map_1,
448	.freq_tbl = ftbl_gcc_gp1_clk_src,
449	.clkr.hw.init = &(struct clk_init_data){
450	.name = "gcc_gp3_clk_src",
451	.parent_data = gcc_parent_data_1,
452	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
453	.flags = CLK_SET_RATE_PARENT,
454	.ops = &clk_rcg2_ops,
455	},
456	};
457
458	static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
459	F(9600000, P_BI_TCXO, 2, 0, 0),
460	F(19200000, P_BI_TCXO, 1, 0, 0),
461	{ }
462	};
463
464	static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
465	.cmd_rcgr = 0x6b058,
466	.mnd_width = 16,
467	.hid_width = 5,
468	.parent_map = gcc_parent_map_2,
469	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
470	.clkr.hw.init = &(struct clk_init_data){
471	.name = "gcc_pcie_0_aux_clk_src",
472	.parent_data = gcc_parent_data_2,
473	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
474	.flags = CLK_SET_RATE_PARENT,
475	.ops = &clk_rcg2_ops,
476	},
477	};
478
479	static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
480	F(19200000, P_BI_TCXO, 1, 0, 0),
481	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
482	{ }
483	};
484
485	static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
486	.cmd_rcgr = 0x6b03c,
487	.mnd_width = 0,
488	.hid_width = 5,
489	.parent_map = gcc_parent_map_0,
490	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
491	.clkr.hw.init = &(struct clk_init_data){
492	.name = "gcc_pcie_0_phy_rchng_clk_src",
493	.parent_data = gcc_parent_data_0,
494	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
495	.flags = CLK_SET_RATE_PARENT,
496	.ops = &clk_rcg2_ops,
497	},
498	};
499
500	static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
501	.cmd_rcgr = 0x8d058,
502	.mnd_width = 16,
503	.hid_width = 5,
504	.parent_map = gcc_parent_map_2,
505	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
506	.clkr.hw.init = &(struct clk_init_data){
507	.name = "gcc_pcie_1_aux_clk_src",
508	.parent_data = gcc_parent_data_2,
509	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
510	.flags = CLK_SET_RATE_PARENT,
511	.ops = &clk_rcg2_ops,
512	},
513	};
514
515	static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
516	.cmd_rcgr = 0x8d03c,
517	.mnd_width = 0,
518	.hid_width = 5,
519	.parent_map = gcc_parent_map_0,
520	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
521	.clkr.hw.init = &(struct clk_init_data){
522	.name = "gcc_pcie_1_phy_rchng_clk_src",
523	.parent_data = gcc_parent_data_0,
524	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
525	.flags = CLK_SET_RATE_PARENT,
526	.ops = &clk_rcg2_ops,
527	},
528	};
529
530	static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
531	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
532	{ }
533	};
534
535	static struct clk_rcg2 gcc_pdm2_clk_src = {
536	.cmd_rcgr = 0x33010,
537	.mnd_width = 0,
538	.hid_width = 5,
539	.parent_map = gcc_parent_map_0,
540	.freq_tbl = ftbl_gcc_pdm2_clk_src,
541	.clkr.hw.init = &(struct clk_init_data){
542	.name = "gcc_pdm2_clk_src",
543	.parent_data = gcc_parent_data_0,
544	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
545	.flags = CLK_SET_RATE_PARENT,
546	.ops = &clk_rcg2_ops,
547	},
548	};
549
550	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
551	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
552	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
553	F(19200000, P_BI_TCXO, 1, 0, 0),
554	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
555	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
556	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
557	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
558	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
559	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
560	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
561	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
562	{ }
563	};
564
565	static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
566	.name = "gcc_qupv3_wrap0_s0_clk_src",
567	.parent_data = gcc_parent_data_0,
568	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
569	.flags = CLK_SET_RATE_PARENT,
570	.ops = &clk_rcg2_ops,
571	};
572
573	static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
574	.cmd_rcgr = 0x17010,
575	.mnd_width = 16,
576	.hid_width = 5,
577	.parent_map = gcc_parent_map_0,
578	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
579	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
580	};
581
582	static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
583	.name = "gcc_qupv3_wrap0_s1_clk_src",
584	.parent_data = gcc_parent_data_0,
585	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
586	.flags = CLK_SET_RATE_PARENT,
587	.ops = &clk_rcg2_ops,
588	};
589
590	static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
591	.cmd_rcgr = 0x17140,
592	.mnd_width = 16,
593	.hid_width = 5,
594	.parent_map = gcc_parent_map_0,
595	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
596	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
597	};
598
599	static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
600	.name = "gcc_qupv3_wrap0_s2_clk_src",
601	.parent_data = gcc_parent_data_0,
602	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
603	.flags = CLK_SET_RATE_PARENT,
604	.ops = &clk_rcg2_ops,
605	};
606
607	static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
608	.cmd_rcgr = 0x17270,
609	.mnd_width = 16,
610	.hid_width = 5,
611	.parent_map = gcc_parent_map_0,
612	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
613	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
614	};
615
616	static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
617	.name = "gcc_qupv3_wrap0_s3_clk_src",
618	.parent_data = gcc_parent_data_0,
619	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
620	.flags = CLK_SET_RATE_PARENT,
621	.ops = &clk_rcg2_ops,
622	};
623
624	static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
625	.cmd_rcgr = 0x173a0,
626	.mnd_width = 16,
627	.hid_width = 5,
628	.parent_map = gcc_parent_map_0,
629	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
630	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
631	};
632
633	static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
634	.name = "gcc_qupv3_wrap0_s4_clk_src",
635	.parent_data = gcc_parent_data_0,
636	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
637	.flags = CLK_SET_RATE_PARENT,
638	.ops = &clk_rcg2_ops,
639	};
640
641	static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
642	.cmd_rcgr = 0x174d0,
643	.mnd_width = 16,
644	.hid_width = 5,
645	.parent_map = gcc_parent_map_0,
646	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
647	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
648	};
649
650	static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
651	.name = "gcc_qupv3_wrap0_s5_clk_src",
652	.parent_data = gcc_parent_data_0,
653	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
654	.flags = CLK_SET_RATE_PARENT,
655	.ops = &clk_rcg2_ops,
656	};
657
658	static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
659	.cmd_rcgr = 0x17600,
660	.mnd_width = 16,
661	.hid_width = 5,
662	.parent_map = gcc_parent_map_0,
663	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
664	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
665	};
666
667	static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
668	.name = "gcc_qupv3_wrap0_s6_clk_src",
669	.parent_data = gcc_parent_data_0,
670	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
671	.flags = CLK_SET_RATE_PARENT,
672	.ops = &clk_rcg2_ops,
673	};
674
675	static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
676	.cmd_rcgr = 0x17730,
677	.mnd_width = 16,
678	.hid_width = 5,
679	.parent_map = gcc_parent_map_0,
680	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
681	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
682	};
683
684	static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
685	.name = "gcc_qupv3_wrap0_s7_clk_src",
686	.parent_data = gcc_parent_data_0,
687	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
688	.flags = CLK_SET_RATE_PARENT,
689	.ops = &clk_rcg2_ops,
690	};
691
692	static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
693	.cmd_rcgr = 0x17860,
694	.mnd_width = 16,
695	.hid_width = 5,
696	.parent_map = gcc_parent_map_0,
697	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
698	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
699	};
700
701	static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
702	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
703	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
704	F(19200000, P_BI_TCXO, 1, 0, 0),
705	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
706	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
707	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
708	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
709	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
710	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
711	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
712	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
713	F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
714	F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
715	F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
716	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
717	{ }
718	};
719
720	static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
721	.name = "gcc_qupv3_wrap1_s0_clk_src",
722	.parent_data = gcc_parent_data_0,
723	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
724	.flags = CLK_SET_RATE_PARENT,
725	.ops = &clk_rcg2_ops,
726	};
727
728	static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
729	.cmd_rcgr = 0x18010,
730	.mnd_width = 16,
731	.hid_width = 5,
732	.parent_map = gcc_parent_map_0,
733	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
734	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
735	};
736
737	static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
738	.name = "gcc_qupv3_wrap1_s1_clk_src",
739	.parent_data = gcc_parent_data_0,
740	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
741	.flags = CLK_SET_RATE_PARENT,
742	.ops = &clk_rcg2_ops,
743	};
744
745	static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
746	.cmd_rcgr = 0x18140,
747	.mnd_width = 16,
748	.hid_width = 5,
749	.parent_map = gcc_parent_map_0,
750	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
751	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
752	};
753
754	static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
755	.name = "gcc_qupv3_wrap1_s2_clk_src",
756	.parent_data = gcc_parent_data_0,
757	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
758	.flags = CLK_SET_RATE_PARENT,
759	.ops = &clk_rcg2_ops,
760	};
761
762	static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
763	.cmd_rcgr = 0x18270,
764	.mnd_width = 16,
765	.hid_width = 5,
766	.parent_map = gcc_parent_map_0,
767	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
768	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
769	};
770
771	static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
772	.name = "gcc_qupv3_wrap1_s3_clk_src",
773	.parent_data = gcc_parent_data_0,
774	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
775	.flags = CLK_SET_RATE_PARENT,
776	.ops = &clk_rcg2_ops,
777	};
778
779	static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
780	.cmd_rcgr = 0x183a0,
781	.mnd_width = 16,
782	.hid_width = 5,
783	.parent_map = gcc_parent_map_0,
784	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
785	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
786	};
787
788	static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
789	.name = "gcc_qupv3_wrap1_s4_clk_src",
790	.parent_data = gcc_parent_data_0,
791	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
792	.flags = CLK_SET_RATE_PARENT,
793	.ops = &clk_rcg2_ops,
794	};
795
796	static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
797	.cmd_rcgr = 0x184d0,
798	.mnd_width = 16,
799	.hid_width = 5,
800	.parent_map = gcc_parent_map_0,
801	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
802	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
803	};
804
805	static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
806	.name = "gcc_qupv3_wrap1_s5_clk_src",
807	.parent_data = gcc_parent_data_0,
808	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
809	.flags = CLK_SET_RATE_PARENT,
810	.ops = &clk_rcg2_ops,
811	};
812
813	static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
814	.cmd_rcgr = 0x18600,
815	.mnd_width = 16,
816	.hid_width = 5,
817	.parent_map = gcc_parent_map_0,
818	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
819	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
820	};
821
822	static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
823	.name = "gcc_qupv3_wrap2_s0_clk_src",
824	.parent_data = gcc_parent_data_0,
825	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
826	.flags = CLK_SET_RATE_PARENT,
827	.ops = &clk_rcg2_ops,
828	};
829
830	static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
831	.cmd_rcgr = 0x1e010,
832	.mnd_width = 16,
833	.hid_width = 5,
834	.parent_map = gcc_parent_map_0,
835	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
836	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
837	};
838
839	static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
840	.name = "gcc_qupv3_wrap2_s1_clk_src",
841	.parent_data = gcc_parent_data_0,
842	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
843	.flags = CLK_SET_RATE_PARENT,
844	.ops = &clk_rcg2_ops,
845	};
846
847	static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
848	.cmd_rcgr = 0x1e140,
849	.mnd_width = 16,
850	.hid_width = 5,
851	.parent_map = gcc_parent_map_0,
852	.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
853	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
854	};
855
856	static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
857	.name = "gcc_qupv3_wrap2_s2_clk_src",
858	.parent_data = gcc_parent_data_0,
859	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
860	.flags = CLK_SET_RATE_PARENT,
861	.ops = &clk_rcg2_ops,
862	};
863
864	static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
865	.cmd_rcgr = 0x1e270,
866	.mnd_width = 16,
867	.hid_width = 5,
868	.parent_map = gcc_parent_map_0,
869	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
870	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
871	};
872
873	static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
874	.name = "gcc_qupv3_wrap2_s3_clk_src",
875	.parent_data = gcc_parent_data_0,
876	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
877	.flags = CLK_SET_RATE_PARENT,
878	.ops = &clk_rcg2_ops,
879	};
880
881	static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
882	.cmd_rcgr = 0x1e3a0,
883	.mnd_width = 16,
884	.hid_width = 5,
885	.parent_map = gcc_parent_map_0,
886	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
887	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
888	};
889
890	static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
891	.name = "gcc_qupv3_wrap2_s4_clk_src",
892	.parent_data = gcc_parent_data_0,
893	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
894	.flags = CLK_SET_RATE_PARENT,
895	.ops = &clk_rcg2_ops,
896	};
897
898	static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
899	.cmd_rcgr = 0x1e4d0,
900	.mnd_width = 16,
901	.hid_width = 5,
902	.parent_map = gcc_parent_map_0,
903	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
904	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
905	};
906
907	static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
908	.name = "gcc_qupv3_wrap2_s5_clk_src",
909	.parent_data = gcc_parent_data_0,
910	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
911	.flags = CLK_SET_RATE_PARENT,
912	.ops = &clk_rcg2_ops,
913	};
914
915	static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
916	.cmd_rcgr = 0x1e600,
917	.mnd_width = 16,
918	.hid_width = 5,
919	.parent_map = gcc_parent_map_0,
920	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
921	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
922	};
923
924	static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
925	F(400000, P_BI_TCXO, 12, 1, 4),
926	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
927	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
928	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
929	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
930	{ }
931	};
932
933	static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
934	.cmd_rcgr = 0x1400c,
935	.mnd_width = 8,
936	.hid_width = 5,
937	.parent_map = gcc_parent_map_6,
938	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
939	.clkr.hw.init = &(struct clk_init_data){
940	.name = "gcc_sdcc2_apps_clk_src",
941	.parent_data = gcc_parent_data_6,
942	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
943	.flags = CLK_SET_RATE_PARENT,
944	.ops = &clk_rcg2_floor_ops,
945	},
946	};
947
948	static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
949	F(400000, P_BI_TCXO, 12, 1, 4),
950	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
951	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
952	{ }
953	};
954
955	static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
956	.cmd_rcgr = 0x1600c,
957	.mnd_width = 8,
958	.hid_width = 5,
959	.parent_map = gcc_parent_map_0,
960	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
961	.clkr.hw.init = &(struct clk_init_data){
962	.name = "gcc_sdcc4_apps_clk_src",
963	.parent_data = gcc_parent_data_0,
964	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
965	.flags = CLK_SET_RATE_PARENT,
966	.ops = &clk_rcg2_floor_ops,
967	},
968	};
969
970	static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
971	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
972	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
973	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
974	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
975	{ }
976	};
977
978	static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
979	.cmd_rcgr = 0x75024,
980	.mnd_width = 8,
981	.hid_width = 5,
982	.parent_map = gcc_parent_map_0,
983	.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
984	.clkr.hw.init = &(struct clk_init_data){
985	.name = "gcc_ufs_card_axi_clk_src",
986	.parent_data = gcc_parent_data_0,
987	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
988	.flags = CLK_SET_RATE_PARENT,
989	.ops = &clk_rcg2_ops,
990	},
991	};
992
993	static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
994	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
995	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
996	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
997	{ }
998	};
999
1000	static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
1001	.cmd_rcgr = 0x7506c,
1002	.mnd_width = 0,
1003	.hid_width = 5,
1004	.parent_map = gcc_parent_map_0,
1005	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1006	.clkr.hw.init = &(struct clk_init_data){
1007	.name = "gcc_ufs_card_ice_core_clk_src",
1008	.parent_data = gcc_parent_data_0,
1009	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1010	.flags = CLK_SET_RATE_PARENT,
1011	.ops = &clk_rcg2_ops,
1012	},
1013	};
1014
1015	static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
1016	F(19200000, P_BI_TCXO, 1, 0, 0),
1017	{ }
1018	};
1019
1020	static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
1021	.cmd_rcgr = 0x750a0,
1022	.mnd_width = 0,
1023	.hid_width = 5,
1024	.parent_map = gcc_parent_map_3,
1025	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1026	.clkr.hw.init = &(struct clk_init_data){
1027	.name = "gcc_ufs_card_phy_aux_clk_src",
1028	.parent_data = gcc_parent_data_3,
1029	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1030	.flags = CLK_SET_RATE_PARENT,
1031	.ops = &clk_rcg2_ops,
1032	},
1033	};
1034
1035	static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
1036	.cmd_rcgr = 0x75084,
1037	.mnd_width = 0,
1038	.hid_width = 5,
1039	.parent_map = gcc_parent_map_0,
1040	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1041	.clkr.hw.init = &(struct clk_init_data){
1042	.name = "gcc_ufs_card_unipro_core_clk_src",
1043	.parent_data = gcc_parent_data_0,
1044	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1045	.flags = CLK_SET_RATE_PARENT,
1046	.ops = &clk_rcg2_ops,
1047	},
1048	};
1049
1050	static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1051	.cmd_rcgr = 0x77024,
1052	.mnd_width = 8,
1053	.hid_width = 5,
1054	.parent_map = gcc_parent_map_0,
1055	.freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
1056	.clkr.hw.init = &(struct clk_init_data){
1057	.name = "gcc_ufs_phy_axi_clk_src",
1058	.parent_data = gcc_parent_data_0,
1059	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1060	.flags = CLK_SET_RATE_PARENT,
1061	.ops = &clk_rcg2_ops,
1062	},
1063	};
1064
1065	static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1066	.cmd_rcgr = 0x7706c,
1067	.mnd_width = 0,
1068	.hid_width = 5,
1069	.parent_map = gcc_parent_map_0,
1070	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1071	.clkr.hw.init = &(struct clk_init_data){
1072	.name = "gcc_ufs_phy_ice_core_clk_src",
1073	.parent_data = gcc_parent_data_0,
1074	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1075	.flags = CLK_SET_RATE_PARENT,
1076	.ops = &clk_rcg2_ops,
1077	},
1078	};
1079
1080	static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1081	.cmd_rcgr = 0x770a0,
1082	.mnd_width = 0,
1083	.hid_width = 5,
1084	.parent_map = gcc_parent_map_3,
1085	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1086	.clkr.hw.init = &(struct clk_init_data){
1087	.name = "gcc_ufs_phy_phy_aux_clk_src",
1088	.parent_data = gcc_parent_data_3,
1089	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1090	.flags = CLK_SET_RATE_PARENT,
1091	.ops = &clk_rcg2_ops,
1092	},
1093	};
1094
1095	static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1096	.cmd_rcgr = 0x77084,
1097	.mnd_width = 0,
1098	.hid_width = 5,
1099	.parent_map = gcc_parent_map_0,
1100	.freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1101	.clkr.hw.init = &(struct clk_init_data){
1102	.name = "gcc_ufs_phy_unipro_core_clk_src",
1103	.parent_data = gcc_parent_data_0,
1104	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1105	.flags = CLK_SET_RATE_PARENT,
1106	.ops = &clk_rcg2_ops,
1107	},
1108	};
1109
1110	static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1111	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1112	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1113	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1114	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1115	{ }
1116	};
1117
1118	static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1119	.cmd_rcgr = 0xf020,
1120	.mnd_width = 8,
1121	.hid_width = 5,
1122	.parent_map = gcc_parent_map_0,
1123	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1124	.clkr.hw.init = &(struct clk_init_data){
1125	.name = "gcc_usb30_prim_master_clk_src",
1126	.parent_data = gcc_parent_data_0,
1127	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1128	.flags = CLK_SET_RATE_PARENT,
1129	.ops = &clk_rcg2_ops,
1130	},
1131	};
1132
1133	static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1134	.cmd_rcgr = 0xf038,
1135	.mnd_width = 0,
1136	.hid_width = 5,
1137	.parent_map = gcc_parent_map_0,
1138	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1139	.clkr.hw.init = &(struct clk_init_data){
1140	.name = "gcc_usb30_prim_mock_utmi_clk_src",
1141	.parent_data = gcc_parent_data_0,
1142	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1143	.flags = CLK_SET_RATE_PARENT,
1144	.ops = &clk_rcg2_ops,
1145	},
1146	};
1147
1148	static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1149	.cmd_rcgr = 0x10020,
1150	.mnd_width = 8,
1151	.hid_width = 5,
1152	.parent_map = gcc_parent_map_0,
1153	.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1154	.clkr.hw.init = &(struct clk_init_data){
1155	.name = "gcc_usb30_sec_master_clk_src",
1156	.parent_data = gcc_parent_data_0,
1157	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1158	.flags = CLK_SET_RATE_PARENT,
1159	.ops = &clk_rcg2_ops,
1160	},
1161	};
1162
1163	static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1164	.cmd_rcgr = 0x10038,
1165	.mnd_width = 0,
1166	.hid_width = 5,
1167	.parent_map = gcc_parent_map_0,
1168	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1169	.clkr.hw.init = &(struct clk_init_data){
1170	.name = "gcc_usb30_sec_mock_utmi_clk_src",
1171	.parent_data = gcc_parent_data_0,
1172	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1173	.flags = CLK_SET_RATE_PARENT,
1174	.ops = &clk_rcg2_ops,
1175	},
1176	};
1177
1178	static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1179	.cmd_rcgr = 0xf064,
1180	.mnd_width = 0,
1181	.hid_width = 5,
1182	.parent_map = gcc_parent_map_2,
1183	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1184	.clkr.hw.init = &(struct clk_init_data){
1185	.name = "gcc_usb3_prim_phy_aux_clk_src",
1186	.parent_data = gcc_parent_data_2,
1187	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1188	.flags = CLK_SET_RATE_PARENT,
1189	.ops = &clk_rcg2_ops,
1190	},
1191	};
1192
1193	static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1194	.cmd_rcgr = 0x10064,
1195	.mnd_width = 0,
1196	.hid_width = 5,
1197	.parent_map = gcc_parent_map_2,
1198	.freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1199	.clkr.hw.init = &(struct clk_init_data){
1200	.name = "gcc_usb3_sec_phy_aux_clk_src",
1201	.parent_data = gcc_parent_data_2,
1202	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
1203	.flags = CLK_SET_RATE_PARENT,
1204	.ops = &clk_rcg2_ops,
1205	},
1206	};
1207
1208	static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1209	.reg = 0xf050,
1210	.shift = 0,
1211	.width = 4,
1212	.clkr.hw.init = &(struct clk_init_data) {
1213	.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1214	.parent_hws = (const struct clk_hw*[]){
1215	&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1216	},
1217	.num_parents = 1,
1218	.flags = CLK_SET_RATE_PARENT,
1219	.ops = &clk_regmap_div_ro_ops,
1220	},
1221	};
1222
1223	static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1224	.reg = 0x10050,
1225	.shift = 0,
1226	.width = 4,
1227	.clkr.hw.init = &(struct clk_init_data) {
1228	.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1229	.parent_hws = (const struct clk_hw*[]){
1230	&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1231	},
1232	.num_parents = 1,
1233	.flags = CLK_SET_RATE_PARENT,
1234	.ops = &clk_regmap_div_ro_ops,
1235	},
1236	};
1237
1238	/* external clocks so add BRANCH_HALT_SKIP */
1239	static struct clk_branch gcc_aggre_noc_pcie_0_axi_clk = {
1240	.halt_reg = 0x6b080,
1241	.halt_check = BRANCH_HALT_SKIP,
1242	.clkr = {
1243	.enable_reg = 0x52000,
1244	.enable_mask = BIT(12),
1245	.hw.init = &(struct clk_init_data){
1246	.name = "gcc_aggre_noc_pcie_0_axi_clk",
1247	.ops = &clk_branch2_ops,
1248	},
1249	},
1250	};
1251
1252	/* external clocks so add BRANCH_HALT_SKIP */
1253	static struct clk_branch gcc_aggre_noc_pcie_1_axi_clk = {
1254	.halt_reg = 0x8d084,
1255	.halt_check = BRANCH_HALT_SKIP,
1256	.clkr = {
1257	.enable_reg = 0x52000,
1258	.enable_mask = BIT(11),
1259	.hw.init = &(struct clk_init_data){
1260	.name = "gcc_aggre_noc_pcie_1_axi_clk",
1261	.ops = &clk_branch2_ops,
1262	},
1263	},
1264	};
1265
1266	static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1267	.halt_reg = 0x9000c,
1268	.halt_check = BRANCH_HALT_VOTED,
1269	.hwcg_reg = 0x9000c,
1270	.hwcg_bit = 1,
1271	.clkr = {
1272	.enable_reg = 0x52000,
1273	.enable_mask = BIT(18),
1274	.hw.init = &(struct clk_init_data){
1275	.name = "gcc_aggre_noc_pcie_tbu_clk",
1276	.ops = &clk_branch2_ops,
1277	},
1278	},
1279	};
1280
1281	static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1282	.halt_reg = 0x750cc,
1283	.halt_check = BRANCH_HALT_VOTED,
1284	.hwcg_reg = 0x750cc,
1285	.hwcg_bit = 1,
1286	.clkr = {
1287	.enable_reg = 0x750cc,
1288	.enable_mask = BIT(0),
1289	.hw.init = &(struct clk_init_data){
1290	.name = "gcc_aggre_ufs_card_axi_clk",
1291	.parent_hws = (const struct clk_hw*[]){
1292	&gcc_ufs_card_axi_clk_src.clkr.hw,
1293	},
1294	.num_parents = 1,
1295	.flags = CLK_SET_RATE_PARENT,
1296	.ops = &clk_branch2_ops,
1297	},
1298	},
1299	};
1300
1301	static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1302	.halt_reg = 0x750cc,
1303	.halt_check = BRANCH_HALT_VOTED,
1304	.hwcg_reg = 0x750cc,
1305	.hwcg_bit = 1,
1306	.clkr = {
1307	.enable_reg = 0x750cc,
1308	.enable_mask = BIT(1),
1309	.hw.init = &(struct clk_init_data){
1310	.name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1311	.parent_hws = (const struct clk_hw*[]){
1312	&gcc_ufs_card_axi_clk_src.clkr.hw,
1313	},
1314	.num_parents = 1,
1315	.flags = CLK_SET_RATE_PARENT,
1316	.ops = &clk_branch2_ops,
1317	},
1318	},
1319	};
1320
1321	static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1322	.halt_reg = 0x770cc,
1323	.halt_check = BRANCH_HALT_VOTED,
1324	.hwcg_reg = 0x770cc,
1325	.hwcg_bit = 1,
1326	.clkr = {
1327	.enable_reg = 0x770cc,
1328	.enable_mask = BIT(0),
1329	.hw.init = &(struct clk_init_data){
1330	.name = "gcc_aggre_ufs_phy_axi_clk",
1331	.parent_hws = (const struct clk_hw*[]){
1332	&gcc_ufs_phy_axi_clk_src.clkr.hw,
1333	},
1334	.num_parents = 1,
1335	.flags = CLK_SET_RATE_PARENT,
1336	.ops = &clk_branch2_ops,
1337	},
1338	},
1339	};
1340
1341	static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1342	.halt_reg = 0x770cc,
1343	.halt_check = BRANCH_HALT_VOTED,
1344	.hwcg_reg = 0x770cc,
1345	.hwcg_bit = 1,
1346	.clkr = {
1347	.enable_reg = 0x770cc,
1348	.enable_mask = BIT(1),
1349	.hw.init = &(struct clk_init_data){
1350	.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1351	.parent_hws = (const struct clk_hw*[]){
1352	&gcc_ufs_phy_axi_clk_src.clkr.hw,
1353	},
1354	.num_parents = 1,
1355	.flags = CLK_SET_RATE_PARENT,
1356	.ops = &clk_branch2_ops,
1357	},
1358	},
1359	};
1360
1361	static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1362	.halt_reg = 0xf080,
1363	.halt_check = BRANCH_HALT_VOTED,
1364	.hwcg_reg = 0xf080,
1365	.hwcg_bit = 1,
1366	.clkr = {
1367	.enable_reg = 0xf080,
1368	.enable_mask = BIT(0),
1369	.hw.init = &(struct clk_init_data){
1370	.name = "gcc_aggre_usb3_prim_axi_clk",
1371	.parent_hws = (const struct clk_hw*[]){
1372	&gcc_usb30_prim_master_clk_src.clkr.hw,
1373	},
1374	.num_parents = 1,
1375	.flags = CLK_SET_RATE_PARENT,
1376	.ops = &clk_branch2_ops,
1377	},
1378	},
1379	};
1380
1381	static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1382	.halt_reg = 0x10080,
1383	.halt_check = BRANCH_HALT_VOTED,
1384	.hwcg_reg = 0x10080,
1385	.hwcg_bit = 1,
1386	.clkr = {
1387	.enable_reg = 0x10080,
1388	.enable_mask = BIT(0),
1389	.hw.init = &(struct clk_init_data){
1390	.name = "gcc_aggre_usb3_sec_axi_clk",
1391	.parent_hws = (const struct clk_hw*[]){
1392	&gcc_usb30_sec_master_clk_src.clkr.hw,
1393	},
1394	.num_parents = 1,
1395	.flags = CLK_SET_RATE_PARENT,
1396	.ops = &clk_branch2_ops,
1397	},
1398	},
1399	};
1400
1401	static struct clk_branch gcc_boot_rom_ahb_clk = {
1402	.halt_reg = 0x38004,
1403	.halt_check = BRANCH_HALT_VOTED,
1404	.hwcg_reg = 0x38004,
1405	.hwcg_bit = 1,
1406	.clkr = {
1407	.enable_reg = 0x52000,
1408	.enable_mask = BIT(10),
1409	.hw.init = &(struct clk_init_data){
1410	.name = "gcc_boot_rom_ahb_clk",
1411	.ops = &clk_branch2_ops,
1412	},
1413	},
1414	};
1415
1416	/* external clocks so add BRANCH_HALT_SKIP */
1417	static struct clk_branch gcc_camera_hf_axi_clk = {
1418	.halt_reg = 0x26010,
1419	.halt_check = BRANCH_HALT_SKIP,
1420	.hwcg_reg = 0x26010,
1421	.hwcg_bit = 1,
1422	.clkr = {
1423	.enable_reg = 0x26010,
1424	.enable_mask = BIT(0),
1425	.hw.init = &(struct clk_init_data){
1426	.name = "gcc_camera_hf_axi_clk",
1427	.ops = &clk_branch2_ops,
1428	},
1429	},
1430	};
1431
1432	/* external clocks so add BRANCH_HALT_SKIP */
1433	static struct clk_branch gcc_camera_sf_axi_clk = {
1434	.halt_reg = 0x26014,
1435	.halt_check = BRANCH_HALT_SKIP,
1436	.hwcg_reg = 0x26014,
1437	.hwcg_bit = 1,
1438	.clkr = {
1439	.enable_reg = 0x26014,
1440	.enable_mask = BIT(0),
1441	.hw.init = &(struct clk_init_data){
1442	.name = "gcc_camera_sf_axi_clk",
1443	.ops = &clk_branch2_ops,
1444	},
1445	},
1446	};
1447
1448	static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1449	.halt_reg = 0xf07c,
1450	.halt_check = BRANCH_HALT_VOTED,
1451	.hwcg_reg = 0xf07c,
1452	.hwcg_bit = 1,
1453	.clkr = {
1454	.enable_reg = 0xf07c,
1455	.enable_mask = BIT(0),
1456	.hw.init = &(struct clk_init_data){
1457	.name = "gcc_cfg_noc_usb3_prim_axi_clk",
1458	.parent_hws = (const struct clk_hw*[]){
1459	&gcc_usb30_prim_master_clk_src.clkr.hw,
1460	},
1461	.num_parents = 1,
1462	.flags = CLK_SET_RATE_PARENT,
1463	.ops = &clk_branch2_ops,
1464	},
1465	},
1466	};
1467
1468	static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1469	.halt_reg = 0x1007c,
1470	.halt_check = BRANCH_HALT_VOTED,
1471	.hwcg_reg = 0x1007c,
1472	.hwcg_bit = 1,
1473	.clkr = {
1474	.enable_reg = 0x1007c,
1475	.enable_mask = BIT(0),
1476	.hw.init = &(struct clk_init_data){
1477	.name = "gcc_cfg_noc_usb3_sec_axi_clk",
1478	.parent_hws = (const struct clk_hw*[]){
1479	&gcc_usb30_sec_master_clk_src.clkr.hw,
1480	},
1481	.num_parents = 1,
1482	.flags = CLK_SET_RATE_PARENT,
1483	.ops = &clk_branch2_ops,
1484	},
1485	},
1486	};
1487
1488	/* external clocks so add BRANCH_HALT_SKIP */
1489	static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1490	.halt_reg = 0x71154,
1491	.halt_check = BRANCH_HALT_SKIP,
1492	.hwcg_reg = 0x71154,
1493	.hwcg_bit = 1,
1494	.clkr = {
1495	.enable_reg = 0x71154,
1496	.enable_mask = BIT(0),
1497	.hw.init = &(struct clk_init_data){
1498	.name = "gcc_ddrss_gpu_axi_clk",
1499	.ops = &clk_branch2_aon_ops,
1500	},
1501	},
1502	};
1503
1504	/* external clocks so add BRANCH_HALT_SKIP */
1505	static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = {
1506	.halt_reg = 0x8d080,
1507	.halt_check = BRANCH_HALT_SKIP,
1508	.hwcg_reg = 0x8d080,
1509	.hwcg_bit = 1,
1510	.clkr = {
1511	.enable_reg = 0x52000,
1512	.enable_mask = BIT(19),
1513	.hw.init = &(struct clk_init_data){
1514	.name = "gcc_ddrss_pcie_sf_tbu_clk",
1515	.ops = &clk_branch2_ops,
1516	},
1517	},
1518	};
1519
1520	/* external clocks so add BRANCH_HALT_SKIP */
1521	static struct clk_branch gcc_disp_hf_axi_clk = {
1522	.halt_reg = 0x2700c,
1523	.halt_check = BRANCH_HALT_SKIP,
1524	.hwcg_reg = 0x2700c,
1525	.hwcg_bit = 1,
1526	.clkr = {
1527	.enable_reg = 0x2700c,
1528	.enable_mask = BIT(0),
1529	.hw.init = &(struct clk_init_data){
1530	.name = "gcc_disp_hf_axi_clk",
1531	.ops = &clk_branch2_ops,
1532	},
1533	},
1534	};
1535
1536	/* external clocks so add BRANCH_HALT_SKIP */
1537	static struct clk_branch gcc_disp_sf_axi_clk = {
1538	.halt_reg = 0x27014,
1539	.halt_check = BRANCH_HALT_SKIP,
1540	.hwcg_reg = 0x27014,
1541	.hwcg_bit = 1,
1542	.clkr = {
1543	.enable_reg = 0x27014,
1544	.enable_mask = BIT(0),
1545	.hw.init = &(struct clk_init_data){
1546	.name = "gcc_disp_sf_axi_clk",
1547	.ops = &clk_branch2_ops,
1548	},
1549	},
1550	};
1551
1552	static struct clk_branch gcc_gp1_clk = {
1553	.halt_reg = 0x64000,
1554	.halt_check = BRANCH_HALT,
1555	.clkr = {
1556	.enable_reg = 0x64000,
1557	.enable_mask = BIT(0),
1558	.hw.init = &(struct clk_init_data){
1559	.name = "gcc_gp1_clk",
1560	.parent_hws = (const struct clk_hw*[]){
1561	&gcc_gp1_clk_src.clkr.hw,
1562	},
1563	.num_parents = 1,
1564	.flags = CLK_SET_RATE_PARENT,
1565	.ops = &clk_branch2_ops,
1566	},
1567	},
1568	};
1569
1570	static struct clk_branch gcc_gp2_clk = {
1571	.halt_reg = 0x65000,
1572	.halt_check = BRANCH_HALT,
1573	.clkr = {
1574	.enable_reg = 0x65000,
1575	.enable_mask = BIT(0),
1576	.hw.init = &(struct clk_init_data){
1577	.name = "gcc_gp2_clk",
1578	.parent_hws = (const struct clk_hw*[]){
1579	&gcc_gp2_clk_src.clkr.hw,
1580	},
1581	.num_parents = 1,
1582	.flags = CLK_SET_RATE_PARENT,
1583	.ops = &clk_branch2_ops,
1584	},
1585	},
1586	};
1587
1588	static struct clk_branch gcc_gp3_clk = {
1589	.halt_reg = 0x66000,
1590	.halt_check = BRANCH_HALT,
1591	.clkr = {
1592	.enable_reg = 0x66000,
1593	.enable_mask = BIT(0),
1594	.hw.init = &(struct clk_init_data){
1595	.name = "gcc_gp3_clk",
1596	.parent_hws = (const struct clk_hw*[]){
1597	&gcc_gp3_clk_src.clkr.hw,
1598	},
1599	.num_parents = 1,
1600	.flags = CLK_SET_RATE_PARENT,
1601	.ops = &clk_branch2_ops,
1602	},
1603	},
1604	};
1605
1606	/* Clock ON depends on external parent clock, so don't poll */
1607	static struct clk_branch gcc_gpu_gpll0_clk_src = {
1608	.halt_check = BRANCH_HALT_DELAY,
1609	.clkr = {
1610	.enable_reg = 0x52000,
1611	.enable_mask = BIT(15),
1612	.hw.init = &(struct clk_init_data){
1613	.name = "gcc_gpu_gpll0_clk_src",
1614	.parent_hws = (const struct clk_hw*[]){
1615	&gcc_gpll0.clkr.hw,
1616	},
1617	.num_parents = 1,
1618	.flags = CLK_SET_RATE_PARENT,
1619	.ops = &clk_branch2_ops,
1620	},
1621	},
1622	};
1623
1624	/* Clock ON depends on external parent clock, so don't poll */
1625	static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
1626	.halt_check = BRANCH_HALT_DELAY,
1627	.clkr = {
1628	.enable_reg = 0x52000,
1629	.enable_mask = BIT(16),
1630	.hw.init = &(struct clk_init_data){
1631	.name = "gcc_gpu_gpll0_div_clk_src",
1632	.parent_hws = (const struct clk_hw*[]){
1633	&gcc_gpll0_out_even.clkr.hw,
1634	},
1635	.num_parents = 1,
1636	.flags = CLK_SET_RATE_PARENT,
1637	.ops = &clk_branch2_ops,
1638	},
1639	},
1640	};
1641
1642	static struct clk_branch gcc_gpu_iref_en = {
1643	.halt_reg = 0x8c014,
1644	.halt_check = BRANCH_HALT,
1645	.clkr = {
1646	.enable_reg = 0x8c014,
1647	.enable_mask = BIT(0),
1648	.hw.init = &(struct clk_init_data){
1649	.name = "gcc_gpu_iref_en",
1650	.ops = &clk_branch2_ops,
1651	},
1652	},
1653	};
1654
1655	static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1656	.halt_reg = 0x7100c,
1657	.halt_check = BRANCH_HALT_VOTED,
1658	.hwcg_reg = 0x7100c,
1659	.hwcg_bit = 1,
1660	.clkr = {
1661	.enable_reg = 0x7100c,
1662	.enable_mask = BIT(0),
1663	.hw.init = &(struct clk_init_data){
1664	.name = "gcc_gpu_memnoc_gfx_clk",
1665	.ops = &clk_branch2_aon_ops,
1666	},
1667	},
1668	};
1669
1670	static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1671	.halt_reg = 0x71018,
1672	.halt_check = BRANCH_HALT,
1673	.clkr = {
1674	.enable_reg = 0x71018,
1675	.enable_mask = BIT(0),
1676	.hw.init = &(struct clk_init_data){
1677	.name = "gcc_gpu_snoc_dvm_gfx_clk",
1678	.ops = &clk_branch2_aon_ops,
1679	},
1680	},
1681	};
1682
1683	static struct clk_branch gcc_pcie0_phy_rchng_clk = {
1684	.halt_reg = 0x6b038,
1685	.halt_check = BRANCH_HALT_VOTED,
1686	.clkr = {
1687	.enable_reg = 0x52000,
1688	.enable_mask = BIT(22),
1689	.hw.init = &(struct clk_init_data){
1690	.name = "gcc_pcie0_phy_rchng_clk",
1691	.parent_hws = (const struct clk_hw*[]){
1692	&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
1693	},
1694	.num_parents = 1,
1695	.flags = CLK_SET_RATE_PARENT,
1696	.ops = &clk_branch2_ops,
1697	},
1698	},
1699	};
1700
1701	static struct clk_branch gcc_pcie1_phy_rchng_clk = {
1702	.halt_reg = 0x8d038,
1703	.halt_check = BRANCH_HALT_VOTED,
1704	.clkr = {
1705	.enable_reg = 0x52000,
1706	.enable_mask = BIT(23),
1707	.hw.init = &(struct clk_init_data){
1708	.name = "gcc_pcie1_phy_rchng_clk",
1709	.parent_hws = (const struct clk_hw*[]){
1710	&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
1711	},
1712	.num_parents = 1,
1713	.flags = CLK_SET_RATE_PARENT,
1714	.ops = &clk_branch2_ops,
1715	},
1716	},
1717	};
1718
1719	static struct clk_branch gcc_pcie_0_aux_clk = {
1720	.halt_reg = 0x6b028,
1721	.halt_check = BRANCH_HALT_VOTED,
1722	.clkr = {
1723	.enable_reg = 0x52008,
1724	.enable_mask = BIT(3),
1725	.hw.init = &(struct clk_init_data){
1726	.name = "gcc_pcie_0_aux_clk",
1727	.parent_hws = (const struct clk_hw*[]){
1728	&gcc_pcie_0_aux_clk_src.clkr.hw,
1729	},
1730	.num_parents = 1,
1731	.flags = CLK_SET_RATE_PARENT,
1732	.ops = &clk_branch2_ops,
1733	},
1734	},
1735	};
1736
1737	static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1738	.halt_reg = 0x6b024,
1739	.halt_check = BRANCH_HALT_VOTED,
1740	.hwcg_reg = 0x6b024,
1741	.hwcg_bit = 1,
1742	.clkr = {
1743	.enable_reg = 0x52008,
1744	.enable_mask = BIT(2),
1745	.hw.init = &(struct clk_init_data){
1746	.name = "gcc_pcie_0_cfg_ahb_clk",
1747	.ops = &clk_branch2_ops,
1748	},
1749	},
1750	};
1751
1752	static struct clk_branch gcc_pcie_0_clkref_en = {
1753	.halt_reg = 0x8c004,
1754	.halt_check = BRANCH_HALT,
1755	.clkr = {
1756	.enable_reg = 0x8c004,
1757	.enable_mask = BIT(0),
1758	.hw.init = &(struct clk_init_data){
1759	.name = "gcc_pcie_0_clkref_en",
1760	.ops = &clk_branch2_ops,
1761	},
1762	},
1763	};
1764
1765	/* external clocks so add BRANCH_HALT_SKIP */
1766	static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1767	.halt_reg = 0x6b01c,
1768	.halt_check = BRANCH_HALT_SKIP,
1769	.hwcg_reg = 0x6b01c,
1770	.hwcg_bit = 1,
1771	.clkr = {
1772	.enable_reg = 0x52008,
1773	.enable_mask = BIT(1),
1774	.hw.init = &(struct clk_init_data){
1775	.name = "gcc_pcie_0_mstr_axi_clk",
1776	.ops = &clk_branch2_ops,
1777	},
1778	},
1779	};
1780
1781	/* external clocks so add BRANCH_HALT_SKIP */
1782	static struct clk_branch gcc_pcie_0_pipe_clk = {
1783	.halt_reg = 0x6b030,
1784	.halt_check = BRANCH_HALT_SKIP,
1785	.clkr = {
1786	.enable_reg = 0x52008,
1787	.enable_mask = BIT(4),
1788	.hw.init = &(struct clk_init_data){
1789	.name = "gcc_pcie_0_pipe_clk",
1790	.parent_hws = (const struct clk_hw*[]){
1791	&gcc_pcie_0_pipe_clk_src.clkr.hw,
1792	},
1793	.num_parents = 1,
1794	.flags = CLK_SET_RATE_PARENT,
1795	.ops = &clk_branch2_ops,
1796	},
1797	},
1798	};
1799
1800	static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1801	.halt_reg = 0x6b014,
1802	.halt_check = BRANCH_HALT_VOTED,
1803	.hwcg_reg = 0x6b014,
1804	.hwcg_bit = 1,
1805	.clkr = {
1806	.enable_reg = 0x52008,
1807	.enable_mask = BIT(0),
1808	.hw.init = &(struct clk_init_data){
1809	.name = "gcc_pcie_0_slv_axi_clk",
1810	.ops = &clk_branch2_ops,
1811	},
1812	},
1813	};
1814
1815	static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1816	.halt_reg = 0x6b010,
1817	.halt_check = BRANCH_HALT_VOTED,
1818	.clkr = {
1819	.enable_reg = 0x52008,
1820	.enable_mask = BIT(5),
1821	.hw.init = &(struct clk_init_data){
1822	.name = "gcc_pcie_0_slv_q2a_axi_clk",
1823	.ops = &clk_branch2_ops,
1824	},
1825	},
1826	};
1827
1828	static struct clk_branch gcc_pcie_1_aux_clk = {
1829	.halt_reg = 0x8d028,
1830	.halt_check = BRANCH_HALT_VOTED,
1831	.clkr = {
1832	.enable_reg = 0x52000,
1833	.enable_mask = BIT(29),
1834	.hw.init = &(struct clk_init_data){
1835	.name = "gcc_pcie_1_aux_clk",
1836	.parent_hws = (const struct clk_hw*[]){
1837	&gcc_pcie_1_aux_clk_src.clkr.hw,
1838	},
1839	.num_parents = 1,
1840	.flags = CLK_SET_RATE_PARENT,
1841	.ops = &clk_branch2_ops,
1842	},
1843	},
1844	};
1845
1846	static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1847	.halt_reg = 0x8d024,
1848	.halt_check = BRANCH_HALT_VOTED,
1849	.hwcg_reg = 0x8d024,
1850	.hwcg_bit = 1,
1851	.clkr = {
1852	.enable_reg = 0x52000,
1853	.enable_mask = BIT(28),
1854	.hw.init = &(struct clk_init_data){
1855	.name = "gcc_pcie_1_cfg_ahb_clk",
1856	.ops = &clk_branch2_ops,
1857	},
1858	},
1859	};
1860
1861	static struct clk_branch gcc_pcie_1_clkref_en = {
1862	.halt_reg = 0x8c008,
1863	.halt_check = BRANCH_HALT,
1864	.clkr = {
1865	.enable_reg = 0x8c008,
1866	.enable_mask = BIT(0),
1867	.hw.init = &(struct clk_init_data){
1868	.name = "gcc_pcie_1_clkref_en",
1869	.ops = &clk_branch2_ops,
1870	},
1871	},
1872	};
1873
1874	/* external clocks so add BRANCH_HALT_SKIP */
1875	static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1876	.halt_reg = 0x8d01c,
1877	.halt_check = BRANCH_HALT_SKIP,
1878	.hwcg_reg = 0x8d01c,
1879	.hwcg_bit = 1,
1880	.clkr = {
1881	.enable_reg = 0x52000,
1882	.enable_mask = BIT(27),
1883	.hw.init = &(struct clk_init_data){
1884	.name = "gcc_pcie_1_mstr_axi_clk",
1885	.ops = &clk_branch2_ops,
1886	},
1887	},
1888	};
1889
1890	/* external clocks so add BRANCH_HALT_SKIP */
1891	static struct clk_branch gcc_pcie_1_pipe_clk = {
1892	.halt_reg = 0x8d030,
1893	.halt_check = BRANCH_HALT_SKIP,
1894	.clkr = {
1895	.enable_reg = 0x52000,
1896	.enable_mask = BIT(30),
1897	.hw.init = &(struct clk_init_data){
1898	.name = "gcc_pcie_1_pipe_clk",
1899	.parent_hws = (const struct clk_hw*[]){
1900	&gcc_pcie_1_pipe_clk_src.clkr.hw,
1901	},
1902	.num_parents = 1,
1903	.flags = CLK_SET_RATE_PARENT,
1904	.ops = &clk_branch2_ops,
1905	},
1906	},
1907	};
1908
1909	static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1910	.halt_reg = 0x8d014,
1911	.halt_check = BRANCH_HALT_VOTED,
1912	.hwcg_reg = 0x8d014,
1913	.hwcg_bit = 1,
1914	.clkr = {
1915	.enable_reg = 0x52000,
1916	.enable_mask = BIT(26),
1917	.hw.init = &(struct clk_init_data){
1918	.name = "gcc_pcie_1_slv_axi_clk",
1919	.ops = &clk_branch2_ops,
1920	},
1921	},
1922	};
1923
1924	static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1925	.halt_reg = 0x8d010,
1926	.halt_check = BRANCH_HALT_VOTED,
1927	.clkr = {
1928	.enable_reg = 0x52000,
1929	.enable_mask = BIT(25),
1930	.hw.init = &(struct clk_init_data){
1931	.name = "gcc_pcie_1_slv_q2a_axi_clk",
1932	.ops = &clk_branch2_ops,
1933	},
1934	},
1935	};
1936
1937	static struct clk_branch gcc_pdm2_clk = {
1938	.halt_reg = 0x3300c,
1939	.halt_check = BRANCH_HALT,
1940	.clkr = {
1941	.enable_reg = 0x3300c,
1942	.enable_mask = BIT(0),
1943	.hw.init = &(struct clk_init_data){
1944	.name = "gcc_pdm2_clk",
1945	.parent_hws = (const struct clk_hw*[]){
1946	&gcc_pdm2_clk_src.clkr.hw,
1947	},
1948	.num_parents = 1,
1949	.flags = CLK_SET_RATE_PARENT,
1950	.ops = &clk_branch2_ops,
1951	},
1952	},
1953	};
1954
1955	static struct clk_branch gcc_pdm_ahb_clk = {
1956	.halt_reg = 0x33004,
1957	.halt_check = BRANCH_HALT_VOTED,
1958	.hwcg_reg = 0x33004,
1959	.hwcg_bit = 1,
1960	.clkr = {
1961	.enable_reg = 0x33004,
1962	.enable_mask = BIT(0),
1963	.hw.init = &(struct clk_init_data){
1964	.name = "gcc_pdm_ahb_clk",
1965	.ops = &clk_branch2_ops,
1966	},
1967	},
1968	};
1969
1970	static struct clk_branch gcc_pdm_xo4_clk = {
1971	.halt_reg = 0x33008,
1972	.halt_check = BRANCH_HALT,
1973	.clkr = {
1974	.enable_reg = 0x33008,
1975	.enable_mask = BIT(0),
1976	.hw.init = &(struct clk_init_data){
1977	.name = "gcc_pdm_xo4_clk",
1978	.ops = &clk_branch2_ops,
1979	},
1980	},
1981	};
1982
1983	static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
1984	.halt_reg = 0x26008,
1985	.halt_check = BRANCH_HALT_VOTED,
1986	.hwcg_reg = 0x26008,
1987	.hwcg_bit = 1,
1988	.clkr = {
1989	.enable_reg = 0x26008,
1990	.enable_mask = BIT(0),
1991	.hw.init = &(struct clk_init_data){
1992	.name = "gcc_qmip_camera_nrt_ahb_clk",
1993	.ops = &clk_branch2_ops,
1994	},
1995	},
1996	};
1997
1998	static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
1999	.halt_reg = 0x2600c,
2000	.halt_check = BRANCH_HALT_VOTED,
2001	.hwcg_reg = 0x2600c,
2002	.hwcg_bit = 1,
2003	.clkr = {
2004	.enable_reg = 0x2600c,
2005	.enable_mask = BIT(0),
2006	.hw.init = &(struct clk_init_data){
2007	.name = "gcc_qmip_camera_rt_ahb_clk",
2008	.ops = &clk_branch2_ops,
2009	},
2010	},
2011	};
2012
2013	static struct clk_branch gcc_qmip_disp_ahb_clk = {
2014	.halt_reg = 0x27008,
2015	.halt_check = BRANCH_HALT_VOTED,
2016	.hwcg_reg = 0x27008,
2017	.hwcg_bit = 1,
2018	.clkr = {
2019	.enable_reg = 0x27008,
2020	.enable_mask = BIT(0),
2021	.hw.init = &(struct clk_init_data){
2022	.name = "gcc_qmip_disp_ahb_clk",
2023	.ops = &clk_branch2_ops,
2024	},
2025	},
2026	};
2027
2028	static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2029	.halt_reg = 0x28008,
2030	.halt_check = BRANCH_HALT_VOTED,
2031	.hwcg_reg = 0x28008,
2032	.hwcg_bit = 1,
2033	.clkr = {
2034	.enable_reg = 0x28008,
2035	.enable_mask = BIT(0),
2036	.hw.init = &(struct clk_init_data){
2037	.name = "gcc_qmip_video_cvp_ahb_clk",
2038	.ops = &clk_branch2_ops,
2039	},
2040	},
2041	};
2042
2043	static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2044	.halt_reg = 0x2800c,
2045	.halt_check = BRANCH_HALT_VOTED,
2046	.hwcg_reg = 0x2800c,
2047	.hwcg_bit = 1,
2048	.clkr = {
2049	.enable_reg = 0x2800c,
2050	.enable_mask = BIT(0),
2051	.hw.init = &(struct clk_init_data){
2052	.name = "gcc_qmip_video_vcodec_ahb_clk",
2053	.ops = &clk_branch2_ops,
2054	},
2055	},
2056	};
2057
2058	static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
2059	.halt_reg = 0x23008,
2060	.halt_check = BRANCH_HALT_VOTED,
2061	.clkr = {
2062	.enable_reg = 0x52008,
2063	.enable_mask = BIT(9),
2064	.hw.init = &(struct clk_init_data){
2065	.name = "gcc_qupv3_wrap0_core_2x_clk",
2066	.ops = &clk_branch2_ops,
2067	},
2068	},
2069	};
2070
2071	static struct clk_branch gcc_qupv3_wrap0_core_clk = {
2072	.halt_reg = 0x23000,
2073	.halt_check = BRANCH_HALT_VOTED,
2074	.clkr = {
2075	.enable_reg = 0x52008,
2076	.enable_mask = BIT(8),
2077	.hw.init = &(struct clk_init_data){
2078	.name = "gcc_qupv3_wrap0_core_clk",
2079	.ops = &clk_branch2_ops,
2080	},
2081	},
2082	};
2083
2084	static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2085	.halt_reg = 0x1700c,
2086	.halt_check = BRANCH_HALT_VOTED,
2087	.clkr = {
2088	.enable_reg = 0x52008,
2089	.enable_mask = BIT(10),
2090	.hw.init = &(struct clk_init_data){
2091	.name = "gcc_qupv3_wrap0_s0_clk",
2092	.parent_hws = (const struct clk_hw*[]){
2093	&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
2094	},
2095	.num_parents = 1,
2096	.flags = CLK_SET_RATE_PARENT,
2097	.ops = &clk_branch2_ops,
2098	},
2099	},
2100	};
2101
2102	static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2103	.halt_reg = 0x1713c,
2104	.halt_check = BRANCH_HALT_VOTED,
2105	.clkr = {
2106	.enable_reg = 0x52008,
2107	.enable_mask = BIT(11),
2108	.hw.init = &(struct clk_init_data){
2109	.name = "gcc_qupv3_wrap0_s1_clk",
2110	.parent_hws = (const struct clk_hw*[]){
2111	&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
2112	},
2113	.num_parents = 1,
2114	.flags = CLK_SET_RATE_PARENT,
2115	.ops = &clk_branch2_ops,
2116	},
2117	},
2118	};
2119
2120	static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2121	.halt_reg = 0x1726c,
2122	.halt_check = BRANCH_HALT_VOTED,
2123	.clkr = {
2124	.enable_reg = 0x52008,
2125	.enable_mask = BIT(12),
2126	.hw.init = &(struct clk_init_data){
2127	.name = "gcc_qupv3_wrap0_s2_clk",
2128	.parent_hws = (const struct clk_hw*[]){
2129	&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
2130	},
2131	.num_parents = 1,
2132	.flags = CLK_SET_RATE_PARENT,
2133	.ops = &clk_branch2_ops,
2134	},
2135	},
2136	};
2137
2138	static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2139	.halt_reg = 0x1739c,
2140	.halt_check = BRANCH_HALT_VOTED,
2141	.clkr = {
2142	.enable_reg = 0x52008,
2143	.enable_mask = BIT(13),
2144	.hw.init = &(struct clk_init_data){
2145	.name = "gcc_qupv3_wrap0_s3_clk",
2146	.parent_hws = (const struct clk_hw*[]){
2147	&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
2148	},
2149	.num_parents = 1,
2150	.flags = CLK_SET_RATE_PARENT,
2151	.ops = &clk_branch2_ops,
2152	},
2153	},
2154	};
2155
2156	static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2157	.halt_reg = 0x174cc,
2158	.halt_check = BRANCH_HALT_VOTED,
2159	.clkr = {
2160	.enable_reg = 0x52008,
2161	.enable_mask = BIT(14),
2162	.hw.init = &(struct clk_init_data){
2163	.name = "gcc_qupv3_wrap0_s4_clk",
2164	.parent_hws = (const struct clk_hw*[]){
2165	&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
2166	},
2167	.num_parents = 1,
2168	.flags = CLK_SET_RATE_PARENT,
2169	.ops = &clk_branch2_ops,
2170	},
2171	},
2172	};
2173
2174	static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2175	.halt_reg = 0x175fc,
2176	.halt_check = BRANCH_HALT_VOTED,
2177	.clkr = {
2178	.enable_reg = 0x52008,
2179	.enable_mask = BIT(15),
2180	.hw.init = &(struct clk_init_data){
2181	.name = "gcc_qupv3_wrap0_s5_clk",
2182	.parent_hws = (const struct clk_hw*[]){
2183	&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
2184	},
2185	.num_parents = 1,
2186	.flags = CLK_SET_RATE_PARENT,
2187	.ops = &clk_branch2_ops,
2188	},
2189	},
2190	};
2191
2192	static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2193	.halt_reg = 0x1772c,
2194	.halt_check = BRANCH_HALT_VOTED,
2195	.clkr = {
2196	.enable_reg = 0x52008,
2197	.enable_mask = BIT(16),
2198	.hw.init = &(struct clk_init_data){
2199	.name = "gcc_qupv3_wrap0_s6_clk",
2200	.parent_hws = (const struct clk_hw*[]){
2201	&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
2202	},
2203	.num_parents = 1,
2204	.flags = CLK_SET_RATE_PARENT,
2205	.ops = &clk_branch2_ops,
2206	},
2207	},
2208	};
2209
2210	static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2211	.halt_reg = 0x1785c,
2212	.halt_check = BRANCH_HALT_VOTED,
2213	.clkr = {
2214	.enable_reg = 0x52008,
2215	.enable_mask = BIT(17),
2216	.hw.init = &(struct clk_init_data){
2217	.name = "gcc_qupv3_wrap0_s7_clk",
2218	.parent_hws = (const struct clk_hw*[]){
2219	&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
2220	},
2221	.num_parents = 1,
2222	.flags = CLK_SET_RATE_PARENT,
2223	.ops = &clk_branch2_ops,
2224	},
2225	},
2226	};
2227
2228	static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
2229	.halt_reg = 0x23140,
2230	.halt_check = BRANCH_HALT_VOTED,
2231	.clkr = {
2232	.enable_reg = 0x52008,
2233	.enable_mask = BIT(18),
2234	.hw.init = &(struct clk_init_data){
2235	.name = "gcc_qupv3_wrap1_core_2x_clk",
2236	.ops = &clk_branch2_ops,
2237	},
2238	},
2239	};
2240
2241	static struct clk_branch gcc_qupv3_wrap1_core_clk = {
2242	.halt_reg = 0x23138,
2243	.halt_check = BRANCH_HALT_VOTED,
2244	.clkr = {
2245	.enable_reg = 0x52008,
2246	.enable_mask = BIT(19),
2247	.hw.init = &(struct clk_init_data){
2248	.name = "gcc_qupv3_wrap1_core_clk",
2249	.ops = &clk_branch2_ops,
2250	},
2251	},
2252	};
2253
2254	static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2255	.halt_reg = 0x18004,
2256	.halt_check = BRANCH_HALT_VOTED,
2257	.hwcg_reg = 0x18004,
2258	.hwcg_bit = 1,
2259	.clkr = {
2260	.enable_reg = 0x52008,
2261	.enable_mask = BIT(20),
2262	.hw.init = &(struct clk_init_data){
2263	.name = "gcc_qupv3_wrap_1_m_ahb_clk",
2264	.ops = &clk_branch2_ops,
2265	},
2266	},
2267	};
2268
2269	static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2270	.halt_reg = 0x18008,
2271	.halt_check = BRANCH_HALT_VOTED,
2272	.hwcg_reg = 0x18008,
2273	.hwcg_bit = 1,
2274	.clkr = {
2275	.enable_reg = 0x52008,
2276	.enable_mask = BIT(21),
2277	.hw.init = &(struct clk_init_data){
2278	.name = "gcc_qupv3_wrap_1_s_ahb_clk",
2279	.ops = &clk_branch2_ops,
2280	},
2281	},
2282	};
2283
2284	static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2285	.halt_reg = 0x1800c,
2286	.halt_check = BRANCH_HALT_VOTED,
2287	.clkr = {
2288	.enable_reg = 0x52008,
2289	.enable_mask = BIT(22),
2290	.hw.init = &(struct clk_init_data){
2291	.name = "gcc_qupv3_wrap1_s0_clk",
2292	.parent_hws = (const struct clk_hw*[]){
2293	&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
2294	},
2295	.num_parents = 1,
2296	.flags = CLK_SET_RATE_PARENT,
2297	.ops = &clk_branch2_ops,
2298	},
2299	},
2300	};
2301
2302	static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2303	.halt_reg = 0x1813c,
2304	.halt_check = BRANCH_HALT_VOTED,
2305	.clkr = {
2306	.enable_reg = 0x52008,
2307	.enable_mask = BIT(23),
2308	.hw.init = &(struct clk_init_data){
2309	.name = "gcc_qupv3_wrap1_s1_clk",
2310	.parent_hws = (const struct clk_hw*[]){
2311	&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
2312	},
2313	.num_parents = 1,
2314	.flags = CLK_SET_RATE_PARENT,
2315	.ops = &clk_branch2_ops,
2316	},
2317	},
2318	};
2319
2320	static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2321	.halt_reg = 0x1826c,
2322	.halt_check = BRANCH_HALT_VOTED,
2323	.clkr = {
2324	.enable_reg = 0x52008,
2325	.enable_mask = BIT(24),
2326	.hw.init = &(struct clk_init_data){
2327	.name = "gcc_qupv3_wrap1_s2_clk",
2328	.parent_hws = (const struct clk_hw*[]){
2329	&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
2330	},
2331	.num_parents = 1,
2332	.flags = CLK_SET_RATE_PARENT,
2333	.ops = &clk_branch2_ops,
2334	},
2335	},
2336	};
2337
2338	static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2339	.halt_reg = 0x1839c,
2340	.halt_check = BRANCH_HALT_VOTED,
2341	.clkr = {
2342	.enable_reg = 0x52008,
2343	.enable_mask = BIT(25),
2344	.hw.init = &(struct clk_init_data){
2345	.name = "gcc_qupv3_wrap1_s3_clk",
2346	.parent_hws = (const struct clk_hw*[]){
2347	&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
2348	},
2349	.num_parents = 1,
2350	.flags = CLK_SET_RATE_PARENT,
2351	.ops = &clk_branch2_ops,
2352	},
2353	},
2354	};
2355
2356	static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2357	.halt_reg = 0x184cc,
2358	.halt_check = BRANCH_HALT_VOTED,
2359	.clkr = {
2360	.enable_reg = 0x52008,
2361	.enable_mask = BIT(26),
2362	.hw.init = &(struct clk_init_data){
2363	.name = "gcc_qupv3_wrap1_s4_clk",
2364	.parent_hws = (const struct clk_hw*[]){
2365	&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
2366	},
2367	.num_parents = 1,
2368	.flags = CLK_SET_RATE_PARENT,
2369	.ops = &clk_branch2_ops,
2370	},
2371	},
2372	};
2373
2374	static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2375	.halt_reg = 0x185fc,
2376	.halt_check = BRANCH_HALT_VOTED,
2377	.clkr = {
2378	.enable_reg = 0x52008,
2379	.enable_mask = BIT(27),
2380	.hw.init = &(struct clk_init_data){
2381	.name = "gcc_qupv3_wrap1_s5_clk",
2382	.parent_hws = (const struct clk_hw*[]){
2383	&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
2384	},
2385	.num_parents = 1,
2386	.flags = CLK_SET_RATE_PARENT,
2387	.ops = &clk_branch2_ops,
2388	},
2389	},
2390	};
2391
2392	static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
2393	.halt_reg = 0x23278,
2394	.halt_check = BRANCH_HALT_VOTED,
2395	.clkr = {
2396	.enable_reg = 0x52010,
2397	.enable_mask = BIT(3),
2398	.hw.init = &(struct clk_init_data){
2399	.name = "gcc_qupv3_wrap2_core_2x_clk",
2400	.ops = &clk_branch2_ops,
2401	},
2402	},
2403	};
2404
2405	static struct clk_branch gcc_qupv3_wrap2_core_clk = {
2406	.halt_reg = 0x23270,
2407	.halt_check = BRANCH_HALT_VOTED,
2408	.clkr = {
2409	.enable_reg = 0x52010,
2410	.enable_mask = BIT(0),
2411	.hw.init = &(struct clk_init_data){
2412	.name = "gcc_qupv3_wrap2_core_clk",
2413	.ops = &clk_branch2_ops,
2414	},
2415	},
2416	};
2417
2418	static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2419	.halt_reg = 0x1e00c,
2420	.halt_check = BRANCH_HALT_VOTED,
2421	.clkr = {
2422	.enable_reg = 0x52010,
2423	.enable_mask = BIT(4),
2424	.hw.init = &(struct clk_init_data){
2425	.name = "gcc_qupv3_wrap2_s0_clk",
2426	.parent_hws = (const struct clk_hw*[]){
2427	&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
2428	},
2429	.num_parents = 1,
2430	.flags = CLK_SET_RATE_PARENT,
2431	.ops = &clk_branch2_ops,
2432	},
2433	},
2434	};
2435
2436	static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2437	.halt_reg = 0x1e13c,
2438	.halt_check = BRANCH_HALT_VOTED,
2439	.clkr = {
2440	.enable_reg = 0x52010,
2441	.enable_mask = BIT(5),
2442	.hw.init = &(struct clk_init_data){
2443	.name = "gcc_qupv3_wrap2_s1_clk",
2444	.parent_hws = (const struct clk_hw*[]){
2445	&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
2446	},
2447	.num_parents = 1,
2448	.flags = CLK_SET_RATE_PARENT,
2449	.ops = &clk_branch2_ops,
2450	},
2451	},
2452	};
2453
2454	static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2455	.halt_reg = 0x1e26c,
2456	.halt_check = BRANCH_HALT_VOTED,
2457	.clkr = {
2458	.enable_reg = 0x52010,
2459	.enable_mask = BIT(6),
2460	.hw.init = &(struct clk_init_data){
2461	.name = "gcc_qupv3_wrap2_s2_clk",
2462	.parent_hws = (const struct clk_hw*[]){
2463	&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
2464	},
2465	.num_parents = 1,
2466	.flags = CLK_SET_RATE_PARENT,
2467	.ops = &clk_branch2_ops,
2468	},
2469	},
2470	};
2471
2472	static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2473	.halt_reg = 0x1e39c,
2474	.halt_check = BRANCH_HALT_VOTED,
2475	.clkr = {
2476	.enable_reg = 0x52010,
2477	.enable_mask = BIT(7),
2478	.hw.init = &(struct clk_init_data){
2479	.name = "gcc_qupv3_wrap2_s3_clk",
2480	.parent_hws = (const struct clk_hw*[]){
2481	&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
2482	},
2483	.num_parents = 1,
2484	.flags = CLK_SET_RATE_PARENT,
2485	.ops = &clk_branch2_ops,
2486	},
2487	},
2488	};
2489
2490	static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2491	.halt_reg = 0x1e4cc,
2492	.halt_check = BRANCH_HALT_VOTED,
2493	.clkr = {
2494	.enable_reg = 0x52010,
2495	.enable_mask = BIT(8),
2496	.hw.init = &(struct clk_init_data){
2497	.name = "gcc_qupv3_wrap2_s4_clk",
2498	.parent_hws = (const struct clk_hw*[]){
2499	&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
2500	},
2501	.num_parents = 1,
2502	.flags = CLK_SET_RATE_PARENT,
2503	.ops = &clk_branch2_ops,
2504	},
2505	},
2506	};
2507
2508	static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2509	.halt_reg = 0x1e5fc,
2510	.halt_check = BRANCH_HALT_VOTED,
2511	.clkr = {
2512	.enable_reg = 0x52010,
2513	.enable_mask = BIT(9),
2514	.hw.init = &(struct clk_init_data){
2515	.name = "gcc_qupv3_wrap2_s5_clk",
2516	.parent_hws = (const struct clk_hw*[]){
2517	&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
2518	},
2519	.num_parents = 1,
2520	.flags = CLK_SET_RATE_PARENT,
2521	.ops = &clk_branch2_ops,
2522	},
2523	},
2524	};
2525
2526	static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2527	.halt_reg = 0x17004,
2528	.halt_check = BRANCH_HALT_VOTED,
2529	.hwcg_reg = 0x17004,
2530	.hwcg_bit = 1,
2531	.clkr = {
2532	.enable_reg = 0x52008,
2533	.enable_mask = BIT(6),
2534	.hw.init = &(struct clk_init_data){
2535	.name = "gcc_qupv3_wrap_0_m_ahb_clk",
2536	.ops = &clk_branch2_ops,
2537	},
2538	},
2539	};
2540
2541	static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2542	.halt_reg = 0x17008,
2543	.halt_check = BRANCH_HALT_VOTED,
2544	.hwcg_reg = 0x17008,
2545	.hwcg_bit = 1,
2546	.clkr = {
2547	.enable_reg = 0x52008,
2548	.enable_mask = BIT(7),
2549	.hw.init = &(struct clk_init_data){
2550	.name = "gcc_qupv3_wrap_0_s_ahb_clk",
2551	.ops = &clk_branch2_ops,
2552	},
2553	},
2554	};
2555
2556	static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2557	.halt_reg = 0x1e004,
2558	.halt_check = BRANCH_HALT_VOTED,
2559	.hwcg_reg = 0x1e004,
2560	.hwcg_bit = 1,
2561	.clkr = {
2562	.enable_reg = 0x52010,
2563	.enable_mask = BIT(2),
2564	.hw.init = &(struct clk_init_data){
2565	.name = "gcc_qupv3_wrap_2_m_ahb_clk",
2566	.ops = &clk_branch2_ops,
2567	},
2568	},
2569	};
2570
2571	static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2572	.halt_reg = 0x1e008,
2573	.halt_check = BRANCH_HALT_VOTED,
2574	.hwcg_reg = 0x1e008,
2575	.hwcg_bit = 1,
2576	.clkr = {
2577	.enable_reg = 0x52010,
2578	.enable_mask = BIT(1),
2579	.hw.init = &(struct clk_init_data){
2580	.name = "gcc_qupv3_wrap_2_s_ahb_clk",
2581	.ops = &clk_branch2_ops,
2582	},
2583	},
2584	};
2585
2586	static struct clk_branch gcc_sdcc2_ahb_clk = {
2587	.halt_reg = 0x14008,
2588	.halt_check = BRANCH_HALT,
2589	.clkr = {
2590	.enable_reg = 0x14008,
2591	.enable_mask = BIT(0),
2592	.hw.init = &(struct clk_init_data){
2593	.name = "gcc_sdcc2_ahb_clk",
2594	.ops = &clk_branch2_ops,
2595	},
2596	},
2597	};
2598
2599	static struct clk_branch gcc_sdcc2_apps_clk = {
2600	.halt_reg = 0x14004,
2601	.halt_check = BRANCH_HALT,
2602	.clkr = {
2603	.enable_reg = 0x14004,
2604	.enable_mask = BIT(0),
2605	.hw.init = &(struct clk_init_data){
2606	.name = "gcc_sdcc2_apps_clk",
2607	.parent_hws = (const struct clk_hw*[]){
2608	&gcc_sdcc2_apps_clk_src.clkr.hw,
2609	},
2610	.num_parents = 1,
2611	.flags = CLK_SET_RATE_PARENT,
2612	.ops = &clk_branch2_ops,
2613	},
2614	},
2615	};
2616
2617	static struct clk_branch gcc_sdcc4_ahb_clk = {
2618	.halt_reg = 0x16008,
2619	.halt_check = BRANCH_HALT,
2620	.clkr = {
2621	.enable_reg = 0x16008,
2622	.enable_mask = BIT(0),
2623	.hw.init = &(struct clk_init_data){
2624	.name = "gcc_sdcc4_ahb_clk",
2625	.ops = &clk_branch2_ops,
2626	},
2627	},
2628	};
2629
2630	static struct clk_branch gcc_sdcc4_apps_clk = {
2631	.halt_reg = 0x16004,
2632	.halt_check = BRANCH_HALT,
2633	.clkr = {
2634	.enable_reg = 0x16004,
2635	.enable_mask = BIT(0),
2636	.hw.init = &(struct clk_init_data){
2637	.name = "gcc_sdcc4_apps_clk",
2638	.parent_hws = (const struct clk_hw*[]){
2639	&gcc_sdcc4_apps_clk_src.clkr.hw,
2640	},
2641	.num_parents = 1,
2642	.flags = CLK_SET_RATE_PARENT,
2643	.ops = &clk_branch2_ops,
2644	},
2645	},
2646	};
2647
2648	static struct clk_branch gcc_throttle_pcie_ahb_clk = {
2649	.halt_reg = 0x9044,
2650	.halt_check = BRANCH_HALT,
2651	.clkr = {
2652	.enable_reg = 0x9044,
2653	.enable_mask = BIT(0),
2654	.hw.init = &(struct clk_init_data){
2655	.name = "gcc_throttle_pcie_ahb_clk",
2656	.ops = &clk_branch2_ops,
2657	},
2658	},
2659	};
2660
2661	static struct clk_branch gcc_ufs_1_clkref_en = {
2662	.halt_reg = 0x8c000,
2663	.halt_check = BRANCH_HALT,
2664	.clkr = {
2665	.enable_reg = 0x8c000,
2666	.enable_mask = BIT(0),
2667	.hw.init = &(struct clk_init_data){
2668	.name = "gcc_ufs_1_clkref_en",
2669	.ops = &clk_branch2_ops,
2670	},
2671	},
2672	};
2673
2674	static struct clk_branch gcc_ufs_card_ahb_clk = {
2675	.halt_reg = 0x75018,
2676	.halt_check = BRANCH_HALT_VOTED,
2677	.hwcg_reg = 0x75018,
2678	.hwcg_bit = 1,
2679	.clkr = {
2680	.enable_reg = 0x75018,
2681	.enable_mask = BIT(0),
2682	.hw.init = &(struct clk_init_data){
2683	.name = "gcc_ufs_card_ahb_clk",
2684	.ops = &clk_branch2_ops,
2685	},
2686	},
2687	};
2688
2689	static struct clk_branch gcc_ufs_card_axi_clk = {
2690	.halt_reg = 0x75010,
2691	.halt_check = BRANCH_HALT_VOTED,
2692	.hwcg_reg = 0x75010,
2693	.hwcg_bit = 1,
2694	.clkr = {
2695	.enable_reg = 0x75010,
2696	.enable_mask = BIT(0),
2697	.hw.init = &(struct clk_init_data){
2698	.name = "gcc_ufs_card_axi_clk",
2699	.parent_hws = (const struct clk_hw*[]){
2700	&gcc_ufs_card_axi_clk_src.clkr.hw,
2701	},
2702	.num_parents = 1,
2703	.flags = CLK_SET_RATE_PARENT,
2704	.ops = &clk_branch2_ops,
2705	},
2706	},
2707	};
2708
2709	static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2710	.halt_reg = 0x75010,
2711	.halt_check = BRANCH_HALT_VOTED,
2712	.hwcg_reg = 0x75010,
2713	.hwcg_bit = 1,
2714	.clkr = {
2715	.enable_reg = 0x75010,
2716	.enable_mask = BIT(1),
2717	.hw.init = &(struct clk_init_data){
2718	.name = "gcc_ufs_card_axi_hw_ctl_clk",
2719	.parent_hws = (const struct clk_hw*[]){
2720	&gcc_ufs_card_axi_clk_src.clkr.hw,
2721	},
2722	.num_parents = 1,
2723	.flags = CLK_SET_RATE_PARENT,
2724	.ops = &clk_branch2_ops,
2725	},
2726	},
2727	};
2728
2729	static struct clk_branch gcc_ufs_card_ice_core_clk = {
2730	.halt_reg = 0x75064,
2731	.halt_check = BRANCH_HALT_VOTED,
2732	.hwcg_reg = 0x75064,
2733	.hwcg_bit = 1,
2734	.clkr = {
2735	.enable_reg = 0x75064,
2736	.enable_mask = BIT(0),
2737	.hw.init = &(struct clk_init_data){
2738	.name = "gcc_ufs_card_ice_core_clk",
2739	.parent_hws = (const struct clk_hw*[]){
2740	&gcc_ufs_card_ice_core_clk_src.clkr.hw,
2741	},
2742	.num_parents = 1,
2743	.flags = CLK_SET_RATE_PARENT,
2744	.ops = &clk_branch2_ops,
2745	},
2746	},
2747	};
2748
2749	static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2750	.halt_reg = 0x75064,
2751	.halt_check = BRANCH_HALT_VOTED,
2752	.hwcg_reg = 0x75064,
2753	.hwcg_bit = 1,
2754	.clkr = {
2755	.enable_reg = 0x75064,
2756	.enable_mask = BIT(1),
2757	.hw.init = &(struct clk_init_data){
2758	.name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2759	.parent_hws = (const struct clk_hw*[]){
2760	&gcc_ufs_card_ice_core_clk_src.clkr.hw,
2761	},
2762	.num_parents = 1,
2763	.flags = CLK_SET_RATE_PARENT,
2764	.ops = &clk_branch2_ops,
2765	},
2766	},
2767	};
2768
2769	static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2770	.halt_reg = 0x7509c,
2771	.halt_check = BRANCH_HALT_VOTED,
2772	.hwcg_reg = 0x7509c,
2773	.hwcg_bit = 1,
2774	.clkr = {
2775	.enable_reg = 0x7509c,
2776	.enable_mask = BIT(0),
2777	.hw.init = &(struct clk_init_data){
2778	.name = "gcc_ufs_card_phy_aux_clk",
2779	.parent_hws = (const struct clk_hw*[]){
2780	&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2781	},
2782	.num_parents = 1,
2783	.flags = CLK_SET_RATE_PARENT,
2784	.ops = &clk_branch2_ops,
2785	},
2786	},
2787	};
2788
2789	static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2790	.halt_reg = 0x7509c,
2791	.halt_check = BRANCH_HALT_VOTED,
2792	.hwcg_reg = 0x7509c,
2793	.hwcg_bit = 1,
2794	.clkr = {
2795	.enable_reg = 0x7509c,
2796	.enable_mask = BIT(1),
2797	.hw.init = &(struct clk_init_data){
2798	.name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2799	.parent_hws = (const struct clk_hw*[]){
2800	&gcc_ufs_card_phy_aux_clk_src.clkr.hw,
2801	},
2802	.num_parents = 1,
2803	.flags = CLK_SET_RATE_PARENT,
2804	.ops = &clk_branch2_ops,
2805	},
2806	},
2807	};
2808
2809	/* Clock ON depends on external parent clock, so don't poll */
2810	static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
2811	.halt_reg = 0x75020,
2812	.halt_check = BRANCH_HALT_DELAY,
2813	.clkr = {
2814	.enable_reg = 0x75020,
2815	.enable_mask = BIT(0),
2816	.hw.init = &(struct clk_init_data){
2817	.name = "gcc_ufs_card_rx_symbol_0_clk",
2818	.parent_hws = (const struct clk_hw*[]){
2819	&gcc_ufs_card_rx_symbol_0_clk_src.clkr.hw,
2820	},
2821	.num_parents = 1,
2822	.flags = CLK_SET_RATE_PARENT,
2823	.ops = &clk_branch2_ops,
2824	},
2825	},
2826	};
2827
2828	/* Clock ON depends on external parent clock, so don't poll */
2829	static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
2830	.halt_reg = 0x750b8,
2831	.halt_check = BRANCH_HALT_DELAY,
2832	.clkr = {
2833	.enable_reg = 0x750b8,
2834	.enable_mask = BIT(0),
2835	.hw.init = &(struct clk_init_data){
2836	.name = "gcc_ufs_card_rx_symbol_1_clk",
2837	.parent_hws = (const struct clk_hw*[]){
2838	&gcc_ufs_card_rx_symbol_1_clk_src.clkr.hw,
2839	},
2840	.num_parents = 1,
2841	.flags = CLK_SET_RATE_PARENT,
2842	.ops = &clk_branch2_ops,
2843	},
2844	},
2845	};
2846
2847	/* Clock ON depends on external parent clock, so don't poll */
2848	static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
2849	.halt_reg = 0x7501c,
2850	.halt_check = BRANCH_HALT_DELAY,
2851	.clkr = {
2852	.enable_reg = 0x7501c,
2853	.enable_mask = BIT(0),
2854	.hw.init = &(struct clk_init_data){
2855	.name = "gcc_ufs_card_tx_symbol_0_clk",
2856	.parent_hws = (const struct clk_hw*[]){
2857	&gcc_ufs_card_tx_symbol_0_clk_src.clkr.hw,
2858	},
2859	.num_parents = 1,
2860	.flags = CLK_SET_RATE_PARENT,
2861	.ops = &clk_branch2_ops,
2862	},
2863	},
2864	};
2865
2866	static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2867	.halt_reg = 0x7505c,
2868	.halt_check = BRANCH_HALT_VOTED,
2869	.hwcg_reg = 0x7505c,
2870	.hwcg_bit = 1,
2871	.clkr = {
2872	.enable_reg = 0x7505c,
2873	.enable_mask = BIT(0),
2874	.hw.init = &(struct clk_init_data){
2875	.name = "gcc_ufs_card_unipro_core_clk",
2876	.parent_hws = (const struct clk_hw*[]){
2877	&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2878	},
2879	.num_parents = 1,
2880	.flags = CLK_SET_RATE_PARENT,
2881	.ops = &clk_branch2_ops,
2882	},
2883	},
2884	};
2885
2886	static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2887	.halt_reg = 0x7505c,
2888	.halt_check = BRANCH_HALT_VOTED,
2889	.hwcg_reg = 0x7505c,
2890	.hwcg_bit = 1,
2891	.clkr = {
2892	.enable_reg = 0x7505c,
2893	.enable_mask = BIT(1),
2894	.hw.init = &(struct clk_init_data){
2895	.name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2896	.parent_hws = (const struct clk_hw*[]){
2897	&gcc_ufs_card_unipro_core_clk_src.clkr.hw,
2898	},
2899	.num_parents = 1,
2900	.flags = CLK_SET_RATE_PARENT,
2901	.ops = &clk_branch2_ops,
2902	},
2903	},
2904	};
2905
2906	static struct clk_branch gcc_ufs_phy_ahb_clk = {
2907	.halt_reg = 0x77018,
2908	.halt_check = BRANCH_HALT_VOTED,
2909	.hwcg_reg = 0x77018,
2910	.hwcg_bit = 1,
2911	.clkr = {
2912	.enable_reg = 0x77018,
2913	.enable_mask = BIT(0),
2914	.hw.init = &(struct clk_init_data){
2915	.name = "gcc_ufs_phy_ahb_clk",
2916	.ops = &clk_branch2_ops,
2917	},
2918	},
2919	};
2920
2921	static struct clk_branch gcc_ufs_phy_axi_clk = {
2922	.halt_reg = 0x77010,
2923	.halt_check = BRANCH_HALT_VOTED,
2924	.hwcg_reg = 0x77010,
2925	.hwcg_bit = 1,
2926	.clkr = {
2927	.enable_reg = 0x77010,
2928	.enable_mask = BIT(0),
2929	.hw.init = &(struct clk_init_data){
2930	.name = "gcc_ufs_phy_axi_clk",
2931	.parent_hws = (const struct clk_hw*[]){
2932	&gcc_ufs_phy_axi_clk_src.clkr.hw,
2933	},
2934	.num_parents = 1,
2935	.flags = CLK_SET_RATE_PARENT,
2936	.ops = &clk_branch2_ops,
2937	},
2938	},
2939	};
2940
2941	static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2942	.halt_reg = 0x77010,
2943	.halt_check = BRANCH_HALT_VOTED,
2944	.hwcg_reg = 0x77010,
2945	.hwcg_bit = 1,
2946	.clkr = {
2947	.enable_reg = 0x77010,
2948	.enable_mask = BIT(1),
2949	.hw.init = &(struct clk_init_data){
2950	.name = "gcc_ufs_phy_axi_hw_ctl_clk",
2951	.parent_hws = (const struct clk_hw*[]){
2952	&gcc_ufs_phy_axi_clk_src.clkr.hw,
2953	},
2954	.num_parents = 1,
2955	.flags = CLK_SET_RATE_PARENT,
2956	.ops = &clk_branch2_ops,
2957	},
2958	},
2959	};
2960
2961	static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2962	.halt_reg = 0x77064,
2963	.halt_check = BRANCH_HALT_VOTED,
2964	.hwcg_reg = 0x77064,
2965	.hwcg_bit = 1,
2966	.clkr = {
2967	.enable_reg = 0x77064,
2968	.enable_mask = BIT(0),
2969	.hw.init = &(struct clk_init_data){
2970	.name = "gcc_ufs_phy_ice_core_clk",
2971	.parent_hws = (const struct clk_hw*[]){
2972	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2973	},
2974	.num_parents = 1,
2975	.flags = CLK_SET_RATE_PARENT,
2976	.ops = &clk_branch2_ops,
2977	},
2978	},
2979	};
2980
2981	static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2982	.halt_reg = 0x77064,
2983	.halt_check = BRANCH_HALT_VOTED,
2984	.hwcg_reg = 0x77064,
2985	.hwcg_bit = 1,
2986	.clkr = {
2987	.enable_reg = 0x77064,
2988	.enable_mask = BIT(1),
2989	.hw.init = &(struct clk_init_data){
2990	.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2991	.parent_hws = (const struct clk_hw*[]){
2992	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
2993	},
2994	.num_parents = 1,
2995	.flags = CLK_SET_RATE_PARENT,
2996	.ops = &clk_branch2_ops,
2997	},
2998	},
2999	};
3000
3001	static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3002	.halt_reg = 0x7709c,
3003	.halt_check = BRANCH_HALT_VOTED,
3004	.hwcg_reg = 0x7709c,
3005	.hwcg_bit = 1,
3006	.clkr = {
3007	.enable_reg = 0x7709c,
3008	.enable_mask = BIT(0),
3009	.hw.init = &(struct clk_init_data){
3010	.name = "gcc_ufs_phy_phy_aux_clk",
3011	.parent_hws = (const struct clk_hw*[]){
3012	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3013	},
3014	.num_parents = 1,
3015	.flags = CLK_SET_RATE_PARENT,
3016	.ops = &clk_branch2_ops,
3017	},
3018	},
3019	};
3020
3021	static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3022	.halt_reg = 0x7709c,
3023	.halt_check = BRANCH_HALT_VOTED,
3024	.hwcg_reg = 0x7709c,
3025	.hwcg_bit = 1,
3026	.clkr = {
3027	.enable_reg = 0x7709c,
3028	.enable_mask = BIT(1),
3029	.hw.init = &(struct clk_init_data){
3030	.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
3031	.parent_hws = (const struct clk_hw*[]){
3032	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3033	},
3034	.num_parents = 1,
3035	.flags = CLK_SET_RATE_PARENT,
3036	.ops = &clk_branch2_ops,
3037	},
3038	},
3039	};
3040
3041	/* Clock ON depends on external parent clock, so don't poll */
3042	static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
3043	.halt_reg = 0x77020,
3044	.halt_check = BRANCH_HALT_DELAY,
3045	.clkr = {
3046	.enable_reg = 0x77020,
3047	.enable_mask = BIT(0),
3048	.hw.init = &(struct clk_init_data){
3049	.name = "gcc_ufs_phy_rx_symbol_0_clk",
3050	.parent_hws = (const struct clk_hw*[]){
3051	&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
3052	},
3053	.num_parents = 1,
3054	.flags = CLK_SET_RATE_PARENT,
3055	.ops = &clk_branch2_ops,
3056	},
3057	},
3058	};
3059
3060	/* Clock ON depends on external parent clock, so don't poll */
3061	static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
3062	.halt_reg = 0x770b8,
3063	.halt_check = BRANCH_HALT_DELAY,
3064	.clkr = {
3065	.enable_reg = 0x770b8,
3066	.enable_mask = BIT(0),
3067	.hw.init = &(struct clk_init_data){
3068	.name = "gcc_ufs_phy_rx_symbol_1_clk",
3069	.parent_hws = (const struct clk_hw*[]){
3070	&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
3071	},
3072	.num_parents = 1,
3073	.flags = CLK_SET_RATE_PARENT,
3074	.ops = &clk_branch2_ops,
3075	},
3076	},
3077	};
3078
3079	/* Clock ON depends on external parent clock, so don't poll */
3080	static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
3081	.halt_reg = 0x7701c,
3082	.halt_check = BRANCH_HALT_DELAY,
3083	.clkr = {
3084	.enable_reg = 0x7701c,
3085	.enable_mask = BIT(0),
3086	.hw.init = &(struct clk_init_data){
3087	.name = "gcc_ufs_phy_tx_symbol_0_clk",
3088	.parent_hws = (const struct clk_hw*[]){
3089	&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
3090	},
3091	.num_parents = 1,
3092	.flags = CLK_SET_RATE_PARENT,
3093	.ops = &clk_branch2_ops,
3094	},
3095	},
3096	};
3097
3098	static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
3099	.halt_reg = 0x7705c,
3100	.halt_check = BRANCH_HALT_VOTED,
3101	.hwcg_reg = 0x7705c,
3102	.hwcg_bit = 1,
3103	.clkr = {
3104	.enable_reg = 0x7705c,
3105	.enable_mask = BIT(0),
3106	.hw.init = &(struct clk_init_data){
3107	.name = "gcc_ufs_phy_unipro_core_clk",
3108	.parent_hws = (const struct clk_hw*[]){
3109	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3110	},
3111	.num_parents = 1,
3112	.flags = CLK_SET_RATE_PARENT,
3113	.ops = &clk_branch2_ops,
3114	},
3115	},
3116	};
3117
3118	static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3119	.halt_reg = 0x7705c,
3120	.halt_check = BRANCH_HALT_VOTED,
3121	.hwcg_reg = 0x7705c,
3122	.hwcg_bit = 1,
3123	.clkr = {
3124	.enable_reg = 0x7705c,
3125	.enable_mask = BIT(1),
3126	.hw.init = &(struct clk_init_data){
3127	.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3128	.parent_hws = (const struct clk_hw*[]){
3129	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3130	},
3131	.num_parents = 1,
3132	.flags = CLK_SET_RATE_PARENT,
3133	.ops = &clk_branch2_ops,
3134	},
3135	},
3136	};
3137
3138	static struct clk_branch gcc_usb30_prim_master_clk = {
3139	.halt_reg = 0xf010,
3140	.halt_check = BRANCH_HALT,
3141	.clkr = {
3142	.enable_reg = 0xf010,
3143	.enable_mask = BIT(0),
3144	.hw.init = &(struct clk_init_data){
3145	.name = "gcc_usb30_prim_master_clk",
3146	.parent_hws = (const struct clk_hw*[]){
3147	&gcc_usb30_prim_master_clk_src.clkr.hw,
3148	},
3149	.num_parents = 1,
3150	.flags = CLK_SET_RATE_PARENT,
3151	.ops = &clk_branch2_ops,
3152	},
3153	},
3154	};
3155
3156	static struct clk_branch gcc_usb30_prim_master_clk__force_mem_core_on = {
3157	.halt_reg = 0xf010,
3158	.halt_check = BRANCH_HALT,
3159	.clkr = {
3160	.enable_reg = 0xf010,
3161	.enable_mask = BIT(14),
3162	.hw.init = &(struct clk_init_data){
3163	.name = "gcc_usb30_prim_master_clk__force_mem_core_on",
3164	.ops = &clk_branch_simple_ops,
3165	},
3166	},
3167	};
3168
3169	static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3170	.halt_reg = 0xf01c,
3171	.halt_check = BRANCH_HALT,
3172	.clkr = {
3173	.enable_reg = 0xf01c,
3174	.enable_mask = BIT(0),
3175	.hw.init = &(struct clk_init_data){
3176	.name = "gcc_usb30_prim_mock_utmi_clk",
3177	.parent_hws = (const struct clk_hw*[]){
3178	&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
3179	},
3180	.num_parents = 1,
3181	.flags = CLK_SET_RATE_PARENT,
3182	.ops = &clk_branch2_ops,
3183	},
3184	},
3185	};
3186
3187	static struct clk_branch gcc_usb30_prim_sleep_clk = {
3188	.halt_reg = 0xf018,
3189	.halt_check = BRANCH_HALT,
3190	.clkr = {
3191	.enable_reg = 0xf018,
3192	.enable_mask = BIT(0),
3193	.hw.init = &(struct clk_init_data){
3194	.name = "gcc_usb30_prim_sleep_clk",
3195	.ops = &clk_branch2_ops,
3196	},
3197	},
3198	};
3199
3200	static struct clk_branch gcc_usb30_sec_master_clk = {
3201	.halt_reg = 0x10010,
3202	.halt_check = BRANCH_HALT,
3203	.clkr = {
3204	.enable_reg = 0x10010,
3205	.enable_mask = BIT(0),
3206	.hw.init = &(struct clk_init_data){
3207	.name = "gcc_usb30_sec_master_clk",
3208	.parent_hws = (const struct clk_hw*[]){
3209	&gcc_usb30_sec_master_clk_src.clkr.hw,
3210	},
3211	.num_parents = 1,
3212	.flags = CLK_SET_RATE_PARENT,
3213	.ops = &clk_branch2_ops,
3214	},
3215	},
3216	};
3217
3218	static struct clk_branch gcc_usb30_sec_master_clk__force_mem_core_on = {
3219	.halt_reg = 0x10010,
3220	.halt_check = BRANCH_HALT,
3221	.clkr = {
3222	.enable_reg = 0x10010,
3223	.enable_mask = BIT(14),
3224	.hw.init = &(struct clk_init_data){
3225	.name = "gcc_usb30_sec_master_clk__force_mem_core_on",
3226	.ops = &clk_branch_simple_ops,
3227	},
3228	},
3229	};
3230
3231	static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3232	.halt_reg = 0x1001c,
3233	.halt_check = BRANCH_HALT,
3234	.clkr = {
3235	.enable_reg = 0x1001c,
3236	.enable_mask = BIT(0),
3237	.hw.init = &(struct clk_init_data){
3238	.name = "gcc_usb30_sec_mock_utmi_clk",
3239	.parent_hws = (const struct clk_hw*[]){
3240	&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
3241	},
3242	.num_parents = 1,
3243	.flags = CLK_SET_RATE_PARENT,
3244	.ops = &clk_branch2_ops,
3245	},
3246	},
3247	};
3248
3249	static struct clk_branch gcc_usb30_sec_sleep_clk = {
3250	.halt_reg = 0x10018,
3251	.halt_check = BRANCH_HALT,
3252	.clkr = {
3253	.enable_reg = 0x10018,
3254	.enable_mask = BIT(0),
3255	.hw.init = &(struct clk_init_data){
3256	.name = "gcc_usb30_sec_sleep_clk",
3257	.ops = &clk_branch2_ops,
3258	},
3259	},
3260	};
3261
3262	static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3263	.halt_reg = 0xf054,
3264	.halt_check = BRANCH_HALT,
3265	.clkr = {
3266	.enable_reg = 0xf054,
3267	.enable_mask = BIT(0),
3268	.hw.init = &(struct clk_init_data){
3269	.name = "gcc_usb3_prim_phy_aux_clk",
3270	.parent_hws = (const struct clk_hw*[]){
3271	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3272	},
3273	.num_parents = 1,
3274	.flags = CLK_SET_RATE_PARENT,
3275	.ops = &clk_branch2_ops,
3276	},
3277	},
3278	};
3279
3280	static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3281	.halt_reg = 0xf058,
3282	.halt_check = BRANCH_HALT,
3283	.clkr = {
3284	.enable_reg = 0xf058,
3285	.enable_mask = BIT(0),
3286	.hw.init = &(struct clk_init_data){
3287	.name = "gcc_usb3_prim_phy_com_aux_clk",
3288	.parent_hws = (const struct clk_hw*[]){
3289	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
3290	},
3291	.num_parents = 1,
3292	.flags = CLK_SET_RATE_PARENT,
3293	.ops = &clk_branch2_ops,
3294	},
3295	},
3296	};
3297
3298	/* Clock ON depends on external parent clock, so don't poll */
3299	static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
3300	.halt_reg = 0xf05c,
3301	.halt_check = BRANCH_HALT_DELAY,
3302	.hwcg_reg = 0xf05c,
3303	.hwcg_bit = 1,
3304	.clkr = {
3305	.enable_reg = 0xf05c,
3306	.enable_mask = BIT(0),
3307	.hw.init = &(struct clk_init_data){
3308	.name = "gcc_usb3_prim_phy_pipe_clk",
3309	.parent_hws = (const struct clk_hw*[]){
3310	&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
3311	},
3312	.num_parents = 1,
3313	.flags = CLK_SET_RATE_PARENT,
3314	.ops = &clk_branch2_ops,
3315	},
3316	},
3317	};
3318
3319	static struct clk_branch gcc_usb3_sec_clkref_en = {
3320	.halt_reg = 0x8c010,
3321	.halt_check = BRANCH_HALT,
3322	.clkr = {
3323	.enable_reg = 0x8c010,
3324	.enable_mask = BIT(0),
3325	.hw.init = &(struct clk_init_data){
3326	.name = "gcc_usb3_sec_clkref_en",
3327	.ops = &clk_branch2_ops,
3328	},
3329	},
3330	};
3331
3332	static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3333	.halt_reg = 0x10054,
3334	.halt_check = BRANCH_HALT,
3335	.clkr = {
3336	.enable_reg = 0x10054,
3337	.enable_mask = BIT(0),
3338	.hw.init = &(struct clk_init_data){
3339	.name = "gcc_usb3_sec_phy_aux_clk",
3340	.parent_hws = (const struct clk_hw*[]){
3341	&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3342	},
3343	.num_parents = 1,
3344	.flags = CLK_SET_RATE_PARENT,
3345	.ops = &clk_branch2_ops,
3346	},
3347	},
3348	};
3349
3350	static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3351	.halt_reg = 0x10058,
3352	.halt_check = BRANCH_HALT,
3353	.clkr = {
3354	.enable_reg = 0x10058,
3355	.enable_mask = BIT(0),
3356	.hw.init = &(struct clk_init_data){
3357	.name = "gcc_usb3_sec_phy_com_aux_clk",
3358	.parent_hws = (const struct clk_hw*[]){
3359	&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
3360	},
3361	.num_parents = 1,
3362	.flags = CLK_SET_RATE_PARENT,
3363	.ops = &clk_branch2_ops,
3364	},
3365	},
3366	};
3367
3368	/* Clock ON depends on external parent clock, so don't poll */
3369	static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
3370	.halt_reg = 0x1005c,
3371	.halt_check = BRANCH_HALT_DELAY,
3372	.clkr = {
3373	.enable_reg = 0x1005c,
3374	.enable_mask = BIT(0),
3375	.hw.init = &(struct clk_init_data){
3376	.name = "gcc_usb3_sec_phy_pipe_clk",
3377	.parent_hws = (const struct clk_hw*[]){
3378	&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
3379	},
3380	.num_parents = 1,
3381	.flags = CLK_SET_RATE_PARENT,
3382	.ops = &clk_branch2_ops,
3383	},
3384	},
3385	};
3386
3387	/* external clocks so add BRANCH_HALT_SKIP */
3388	static struct clk_branch gcc_video_axi0_clk = {
3389	.halt_reg = 0x28010,
3390	.halt_check = BRANCH_HALT_SKIP,
3391	.hwcg_reg = 0x28010,
3392	.hwcg_bit = 1,
3393	.clkr = {
3394	.enable_reg = 0x28010,
3395	.enable_mask = BIT(0),
3396	.hw.init = &(struct clk_init_data){
3397	.name = "gcc_video_axi0_clk",
3398	.ops = &clk_branch2_ops,
3399	},
3400	},
3401	};
3402
3403	/* external clocks so add BRANCH_HALT_SKIP */
3404	static struct clk_branch gcc_video_axi1_clk = {
3405	.halt_reg = 0x28018,
3406	.halt_check = BRANCH_HALT_SKIP,
3407	.hwcg_reg = 0x28018,
3408	.hwcg_bit = 1,
3409	.clkr = {
3410	.enable_reg = 0x28018,
3411	.enable_mask = BIT(0),
3412	.hw.init = &(struct clk_init_data){
3413	.name = "gcc_video_axi1_clk",
3414	.ops = &clk_branch2_ops,
3415	},
3416	},
3417	};
3418
3419	static struct gdsc pcie_0_gdsc = {
3420	.gdscr = 0x6b004,
3421	.pd = {
3422	.name = "pcie_0_gdsc",
3423	},
3424	.pwrsts = PWRSTS_OFF_ON,
3425	};
3426
3427	static struct gdsc pcie_1_gdsc = {
3428	.gdscr = 0x8d004,
3429	.pd = {
3430	.name = "pcie_1_gdsc",
3431	},
3432	.pwrsts = PWRSTS_OFF_ON,
3433	};
3434
3435	static struct gdsc ufs_card_gdsc = {
3436	.gdscr = 0x75004,
3437	.pd = {
3438	.name = "ufs_card_gdsc",
3439	},
3440	.pwrsts = PWRSTS_OFF_ON,
3441	};
3442
3443	static struct gdsc ufs_phy_gdsc = {
3444	.gdscr = 0x77004,
3445	.pd = {
3446	.name = "ufs_phy_gdsc",
3447	},
3448	.pwrsts = PWRSTS_OFF_ON,
3449	};
3450
3451	static struct gdsc usb30_prim_gdsc = {
3452	.gdscr = 0xf004,
3453	.pd = {
3454	.name = "usb30_prim_gdsc",
3455	},
3456	.pwrsts = PWRSTS_OFF_ON,
3457	};
3458
3459	static struct gdsc usb30_sec_gdsc = {
3460	.gdscr = 0x10004,
3461	.pd = {
3462	.name = "usb30_sec_gdsc",
3463	},
3464	.pwrsts = PWRSTS_OFF_ON,
3465	};
3466
3467	static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = {
3468	.gdscr = 0x7d050,
3469	.pd = {
3470	.name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc",
3471	},
3472	.pwrsts = PWRSTS_OFF_ON,
3473	.flags = VOTABLE,
3474	};
3475
3476	static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = {
3477	.gdscr = 0x7d058,
3478	.pd = {
3479	.name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc",
3480	},
3481	.pwrsts = PWRSTS_OFF_ON,
3482	.flags = VOTABLE,
3483	};
3484
3485	static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = {
3486	.gdscr = 0x7d054,
3487	.pd = {
3488	.name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc",
3489	},
3490	.pwrsts = PWRSTS_OFF_ON,
3491	.flags = VOTABLE,
3492	};
3493
3494	static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = {
3495	.gdscr = 0x7d06c,
3496	.pd = {
3497	.name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc",
3498	},
3499	.pwrsts = PWRSTS_OFF_ON,
3500	.flags = VOTABLE,
3501	};
3502
3503	static struct clk_regmap *gcc_sm8350_clocks[] = {
3504	[GCC_AGGRE_NOC_PCIE_0_AXI_CLK] = &gcc_aggre_noc_pcie_0_axi_clk.clkr,
3505	[GCC_AGGRE_NOC_PCIE_1_AXI_CLK] = &gcc_aggre_noc_pcie_1_axi_clk.clkr,
3506	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3507	[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3508	[GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3509	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3510	[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3511	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3512	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3513	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3514	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3515	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3516	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3517	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3518	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3519	[GCC_DDRSS_PCIE_SF_TBU_CLK] = &gcc_ddrss_pcie_sf_tbu_clk.clkr,
3520	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3521	[GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3522	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3523	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3524	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3525	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3526	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3527	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3528	[GCC_GPLL0] = &gcc_gpll0.clkr,
3529	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
3530	[GCC_GPLL4] = &gcc_gpll4.clkr,
3531	[GCC_GPLL9] = &gcc_gpll9.clkr,
3532	[GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
3533	[GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
3534	[GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr,
3535	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3536	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3537	[GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
3538	[GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
3539	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3540	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3541	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3542	[GCC_PCIE_0_CLKREF_EN] = &gcc_pcie_0_clkref_en.clkr,
3543	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3544	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
3545	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3546	[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
3547	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3548	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3549	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3550	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3551	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3552	[GCC_PCIE_1_CLKREF_EN] = &gcc_pcie_1_clkref_en.clkr,
3553	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3554	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
3555	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3556	[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
3557	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3558	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3559	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3560	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3561	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3562	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3563	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3564	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3565	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3566	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3567	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3568	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
3569	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
3570	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3571	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3572	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3573	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3574	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3575	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3576	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3577	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3578	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3579	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3580	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3581	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3582	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3583	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3584	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3585	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3586	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
3587	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
3588	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3589	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3590	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3591	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3592	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3593	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3594	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3595	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3596	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3597	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3598	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3599	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3600	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
3601	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
3602	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3603	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3604	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3605	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3606	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3607	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3608	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3609	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3610	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3611	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3612	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3613	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3614	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3615	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3616	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3617	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3618	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3619	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3620	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3621	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3622	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3623	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3624	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3625	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3626	[GCC_THROTTLE_PCIE_AHB_CLK] = &gcc_throttle_pcie_ahb_clk.clkr,
3627	[GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr,
3628	[GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3629	[GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3630	[GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3631	[GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3632	[GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3633	[GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3634	[GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3635	[GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3636	[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3637	[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3638	[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
3639	[GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_rx_symbol_0_clk_src.clkr,
3640	[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
3641	[GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_card_rx_symbol_1_clk_src.clkr,
3642	[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
3643	[GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_card_tx_symbol_0_clk_src.clkr,
3644	[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3645	[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
3646	[GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3647	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3648	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3649	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3650	[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3651	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3652	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3653	[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3654	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3655	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3656	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3657	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
3658	[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
3659	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
3660	[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
3661	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
3662	[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
3663	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3664	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
3665	[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3666	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3667	[GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON] =
3668	&gcc_usb30_prim_master_clk__force_mem_core_on.clkr,
3669	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3670	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3671	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3672	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
3673	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3674	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3675	[GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON] =
3676	&gcc_usb30_sec_master_clk__force_mem_core_on.clkr,
3677	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3678	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3679	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3680	[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
3681	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3682	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3683	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3684	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3685	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
3686	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
3687	[GCC_USB3_SEC_CLKREF_EN] = &gcc_usb3_sec_clkref_en.clkr,
3688	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3689	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3690	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3691	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
3692	[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
3693	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3694	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3695	};
3696
3697	static struct gdsc *gcc_sm8350_gdscs[] = {
3698	[PCIE_0_GDSC] = &pcie_0_gdsc,
3699	[PCIE_1_GDSC] = &pcie_1_gdsc,
3700	[UFS_CARD_GDSC] = &ufs_card_gdsc,
3701	[UFS_PHY_GDSC] = &ufs_phy_gdsc,
3702	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
3703	[USB30_SEC_GDSC] = &usb30_sec_gdsc,
3704	[HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc,
3705	[HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc,
3706	[HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc,
3707	[HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC] = &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc,
3708	};
3709
3710	static const struct qcom_reset_map gcc_sm8350_resets[] = {
3711	[GCC_CAMERA_BCR] = { 0x26000 },
3712	[GCC_DISPLAY_BCR] = { 0x27000 },
3713	[GCC_GPU_BCR] = { 0x71000 },
3714	[GCC_MMSS_BCR] = { 0xb000 },
3715	[GCC_PCIE_0_BCR] = { 0x6b000 },
3716	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3717	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3718	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3719	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
3720	[GCC_PCIE_1_BCR] = { 0x8d000 },
3721	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
3722	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
3723	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3724	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e000 },
3725	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
3726	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
3727	[GCC_PDM_BCR] = { 0x33000 },
3728	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3729	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3730	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3731	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3732	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3733	[GCC_SDCC2_BCR] = { 0x14000 },
3734	[GCC_SDCC4_BCR] = { 0x16000 },
3735	[GCC_UFS_CARD_BCR] = { 0x75000 },
3736	[GCC_UFS_PHY_BCR] = { 0x77000 },
3737	[GCC_USB30_PRIM_BCR] = { 0xf000 },
3738	[GCC_USB30_SEC_BCR] = { 0x10000 },
3739	[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3740	[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
3741	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3742	[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3743	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
3744	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3745	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3746	[GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },
3747	[GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },
3748	[GCC_VIDEO_BCR] = { 0x28000 },
3749	};
3750
3751	static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
3752	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
3753	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
3754	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
3755	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
3756	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
3757	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
3758	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
3759	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
3760	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
3761	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
3762	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
3763	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
3764	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
3765	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
3766	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
3767	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
3768	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
3769	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
3770	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
3771	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
3772	};
3773
3774	static const struct regmap_config gcc_sm8350_regmap_config = {
3775	.reg_bits = 32,
3776	.reg_stride = 4,
3777	.val_bits = 32,
3778	.max_register = 0x9c100,
3779	.fast_io = true,
3780	};
3781
3782	static const struct qcom_cc_desc gcc_sm8350_desc = {
3783	.config = &gcc_sm8350_regmap_config,
3784	.clks = gcc_sm8350_clocks,
3785	.num_clks = ARRAY_SIZE(gcc_sm8350_clocks),
3786	.resets = gcc_sm8350_resets,
3787	.num_resets = ARRAY_SIZE(gcc_sm8350_resets),
3788	.gdscs = gcc_sm8350_gdscs,
3789	.num_gdscs = ARRAY_SIZE(gcc_sm8350_gdscs),
3790	};
3791
3792	static const struct of_device_id gcc_sm8350_match_table[] = {
3793	{ .compatible = "qcom,gcc-sm8350" },
3794	{ }
3795	};
3796	MODULE_DEVICE_TABLE(of, gcc_sm8350_match_table);
3797
3798	static int gcc_sm8350_probe(struct platform_device *pdev)
3799	{
3800	struct regmap *regmap;
3801	int ret;
3802
3803	regmap = qcom_cc_map(pdev, desc: &gcc_sm8350_desc);
3804	if (IS_ERR(ptr: regmap)) {
3805	dev_err(&pdev->dev, "Failed to map gcc registers\n");
3806	return PTR_ERR(ptr: regmap);
3807	}
3808
3809	/* Keep some clocks always-on */
3810	qcom_branch_set_clk_en(regmap, cbcr: 0x26004); /* GCC_CAMERA_AHB_CLK */
3811	qcom_branch_set_clk_en(regmap, cbcr: 0x26018); /* GCC_CAMERA_XO_CLK */
3812	qcom_branch_set_clk_en(regmap, cbcr: 0x27004); /* GCC_DISP_AHB_CLK */
3813	qcom_branch_set_clk_en(regmap, cbcr: 0x2701c); /* GCC_DISP_XO_CLK */
3814	qcom_branch_set_clk_en(regmap, cbcr: 0x71004); /* GCC_GPU_CFG_AHB_CLK */
3815	qcom_branch_set_clk_en(regmap, cbcr: 0x28004); /* GCC_VIDEO_AHB_CLK */
3816	qcom_branch_set_clk_en(regmap, cbcr: 0x28020); /* GCC_VIDEO_XO_CLK */
3817
3818	ret = qcom_cc_register_rcg_dfs(regmap, rcgs: gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));
3819	if (ret)
3820	return ret;
3821
3822	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
3823	regmap_update_bits(map: regmap, reg: gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
3824
3825	return qcom_cc_really_probe(dev: &pdev->dev, desc: &gcc_sm8350_desc, regmap);
3826	}
3827
3828	static struct platform_driver gcc_sm8350_driver = {
3829	.probe = gcc_sm8350_probe,
3830	.driver = {
3831	.name = "sm8350-gcc",
3832	.of_match_table = gcc_sm8350_match_table,
3833	},
3834	};
3835
3836	static int __init gcc_sm8350_init(void)
3837	{
3838	return platform_driver_register(&gcc_sm8350_driver);
3839	}
3840	subsys_initcall(gcc_sm8350_init);
3841
3842	static void __exit gcc_sm8350_exit(void)
3843	{
3844	platform_driver_unregister(&gcc_sm8350_driver);
3845	}
3846	module_exit(gcc_sm8350_exit);
3847
3848	MODULE_DESCRIPTION("QTI GCC SM8350 Driver");
3849	MODULE_LICENSE("GPL v2");
3850