1	// SPDX-License-Identifier: GPL-2.0-only
2	/*
3	* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4	*/
5
6	#include <linux/clk-provider.h>
7	#include <linux/mod_devicetable.h>
8	#include <linux/module.h>
9	#include <linux/platform_device.h>
10	#include <linux/regmap.h>
11
12	#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
13
14	#include "clk-alpha-pll.h"
15	#include "clk-branch.h"
16	#include "clk-rcg.h"
17	#include "clk-regmap.h"
18	#include "clk-regmap-divider.h"
19	#include "clk-regmap-mux.h"
20	#include "clk-regmap-phy-mux.h"
21	#include "gdsc.h"
22	#include "reset.h"
23
24	enum {
25	DT_BI_TCXO,
26	DT_SLEEP_CLK,
27	DT_PCIE_3_PIPE,
28	DT_PCIE_4_PIPE,
29	DT_PCIE_5_PIPE,
30	DT_PCIE_6A_PIPE,
31	DT_PCIE_6B_PIPE,
32	DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE,
33	DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE,
34	DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE,
35	};
36
37	enum {
38	P_BI_TCXO,
39	P_GCC_GPLL0_OUT_EVEN,
40	P_GCC_GPLL0_OUT_MAIN,
41	P_GCC_GPLL4_OUT_MAIN,
42	P_GCC_GPLL7_OUT_MAIN,
43	P_GCC_GPLL8_OUT_MAIN,
44	P_GCC_GPLL9_OUT_MAIN,
45	P_SLEEP_CLK,
46	P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
47	P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
48	P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
49	};
50
51	static struct clk_alpha_pll gcc_gpll0 = {
52	.offset = 0x0,
53	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
54	.clkr = {
55	.enable_reg = 0x52030,
56	.enable_mask = BIT(0),
57	.hw.init = &(const struct clk_init_data) {
58	.name = "gcc_gpll0",
59	.parent_data = &(const struct clk_parent_data) {
60	.index = DT_BI_TCXO,
61	},
62	.num_parents = 1,
63	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
64	},
65	},
66	};
67
68	static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
69	{ 0x1, 2 },
70	{ }
71	};
72
73	static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
74	.offset = 0x0,
75	.post_div_shift = 10,
76	.post_div_table = post_div_table_gcc_gpll0_out_even,
77	.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
78	.width = 4,
79	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
80	.clkr.hw.init = &(const struct clk_init_data) {
81	.name = "gcc_gpll0_out_even",
82	.parent_hws = (const struct clk_hw*[]) {
83	&gcc_gpll0.clkr.hw,
84	},
85	.num_parents = 1,
86	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
87	},
88	};
89
90	static struct clk_alpha_pll gcc_gpll4 = {
91	.offset = 0x4000,
92	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
93	.clkr = {
94	.enable_reg = 0x52030,
95	.enable_mask = BIT(4),
96	.hw.init = &(const struct clk_init_data) {
97	.name = "gcc_gpll4",
98	.parent_data = &(const struct clk_parent_data) {
99	.index = DT_BI_TCXO,
100	},
101	.num_parents = 1,
102	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
103	},
104	},
105	};
106
107	static struct clk_alpha_pll gcc_gpll7 = {
108	.offset = 0x7000,
109	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
110	.clkr = {
111	.enable_reg = 0x52030,
112	.enable_mask = BIT(7),
113	.hw.init = &(const struct clk_init_data) {
114	.name = "gcc_gpll7",
115	.parent_data = &(const struct clk_parent_data) {
116	.index = DT_BI_TCXO,
117	},
118	.num_parents = 1,
119	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
120	},
121	},
122	};
123
124	static struct clk_alpha_pll gcc_gpll8 = {
125	.offset = 0x8000,
126	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
127	.clkr = {
128	.enable_reg = 0x52030,
129	.enable_mask = BIT(8),
130	.hw.init = &(const struct clk_init_data) {
131	.name = "gcc_gpll8",
132	.parent_data = &(const struct clk_parent_data) {
133	.index = DT_BI_TCXO,
134	},
135	.num_parents = 1,
136	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
137	},
138	},
139	};
140
141	static struct clk_alpha_pll gcc_gpll9 = {
142	.offset = 0x9000,
143	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
144	.clkr = {
145	.enable_reg = 0x52030,
146	.enable_mask = BIT(9),
147	.hw.init = &(const struct clk_init_data) {
148	.name = "gcc_gpll9",
149	.parent_data = &(const struct clk_parent_data) {
150	.index = DT_BI_TCXO,
151	},
152	.num_parents = 1,
153	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
154	},
155	},
156	};
157
158	static const struct parent_map gcc_parent_map_0[] = {
159	{ P_BI_TCXO, 0 },
160	{ P_GCC_GPLL0_OUT_MAIN, 1 },
161	{ P_GCC_GPLL0_OUT_EVEN, 6 },
162	};
163
164	static const struct clk_parent_data gcc_parent_data_0[] = {
165	{ .index = DT_BI_TCXO },
166	{ .hw = &gcc_gpll0.clkr.hw },
167	{ .hw = &gcc_gpll0_out_even.clkr.hw },
168	};
169
170	static const struct parent_map gcc_parent_map_1[] = {
171	{ P_BI_TCXO, 0 },
172	{ P_SLEEP_CLK, 5 },
173	};
174
175	static const struct clk_parent_data gcc_parent_data_1[] = {
176	{ .index = DT_BI_TCXO },
177	{ .index = DT_SLEEP_CLK },
178	};
179
180	static const struct parent_map gcc_parent_map_2[] = {
181	{ P_BI_TCXO, 0 },
182	{ P_GCC_GPLL0_OUT_MAIN, 1 },
183	{ P_SLEEP_CLK, 5 },
184	{ P_GCC_GPLL0_OUT_EVEN, 6 },
185	};
186
187	static const struct clk_parent_data gcc_parent_data_2[] = {
188	{ .index = DT_BI_TCXO },
189	{ .hw = &gcc_gpll0.clkr.hw },
190	{ .index = DT_SLEEP_CLK },
191	{ .hw = &gcc_gpll0_out_even.clkr.hw },
192	};
193
194	static const struct parent_map gcc_parent_map_3[] = {
195	{ P_BI_TCXO, 0 },
196	};
197
198	static const struct clk_parent_data gcc_parent_data_3[] = {
199	{ .index = DT_BI_TCXO },
200	};
201
202	static const struct parent_map gcc_parent_map_4[] = {
203	{ P_BI_TCXO, 0 },
204	{ P_GCC_GPLL0_OUT_MAIN, 1 },
205	{ P_GCC_GPLL8_OUT_MAIN, 2 },
206	{ P_GCC_GPLL0_OUT_EVEN, 6 },
207	};
208
209	static const struct clk_parent_data gcc_parent_data_4[] = {
210	{ .index = DT_BI_TCXO },
211	{ .hw = &gcc_gpll0.clkr.hw },
212	{ .hw = &gcc_gpll8.clkr.hw },
213	{ .hw = &gcc_gpll0_out_even.clkr.hw },
214	};
215
216	static const struct parent_map gcc_parent_map_5[] = {
217	{ P_BI_TCXO, 0 },
218	{ P_GCC_GPLL0_OUT_MAIN, 1 },
219	{ P_GCC_GPLL7_OUT_MAIN, 2 },
220	{ P_SLEEP_CLK, 5 },
221	};
222
223	static const struct clk_parent_data gcc_parent_data_5[] = {
224	{ .index = DT_BI_TCXO },
225	{ .hw = &gcc_gpll0.clkr.hw },
226	{ .hw = &gcc_gpll7.clkr.hw },
227	{ .index = DT_SLEEP_CLK },
228	};
229
230	static const struct parent_map gcc_parent_map_6[] = {
231	{ P_BI_TCXO, 0 },
232	{ P_GCC_GPLL0_OUT_MAIN, 1 },
233	{ P_GCC_GPLL7_OUT_MAIN, 2 },
234	};
235
236	static const struct clk_parent_data gcc_parent_data_6[] = {
237	{ .index = DT_BI_TCXO },
238	{ .hw = &gcc_gpll0.clkr.hw },
239	{ .hw = &gcc_gpll7.clkr.hw },
240	};
241
242	static const struct parent_map gcc_parent_map_7[] = {
243	{ P_BI_TCXO, 0 },
244	{ P_GCC_GPLL0_OUT_MAIN, 1 },
245	{ P_GCC_GPLL4_OUT_MAIN, 5 },
246	{ P_GCC_GPLL0_OUT_EVEN, 6 },
247	};
248
249	static const struct clk_parent_data gcc_parent_data_7[] = {
250	{ .index = DT_BI_TCXO },
251	{ .hw = &gcc_gpll0.clkr.hw },
252	{ .hw = &gcc_gpll4.clkr.hw },
253	{ .hw = &gcc_gpll0_out_even.clkr.hw },
254	};
255
256	static const struct parent_map gcc_parent_map_8[] = {
257	{ P_BI_TCXO, 0 },
258	{ P_GCC_GPLL0_OUT_MAIN, 1 },
259	{ P_GCC_GPLL7_OUT_MAIN, 2 },
260	{ P_GCC_GPLL0_OUT_EVEN, 6 },
261	};
262
263	static const struct clk_parent_data gcc_parent_data_8[] = {
264	{ .index = DT_BI_TCXO },
265	{ .hw = &gcc_gpll0.clkr.hw },
266	{ .hw = &gcc_gpll7.clkr.hw },
267	{ .hw = &gcc_gpll0_out_even.clkr.hw },
268	};
269
270	static const struct parent_map gcc_parent_map_9[] = {
271	{ P_BI_TCXO, 0 },
272	{ P_GCC_GPLL0_OUT_MAIN, 1 },
273	{ P_GCC_GPLL9_OUT_MAIN, 2 },
274	{ P_GCC_GPLL4_OUT_MAIN, 5 },
275	{ P_GCC_GPLL0_OUT_EVEN, 6 },
276	};
277
278	static const struct clk_parent_data gcc_parent_data_10[] = {
279	{ .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE },
280	{ .index = DT_BI_TCXO },
281	};
282
283	static const struct parent_map gcc_parent_map_10[] = {
284	{ P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
285	{ P_BI_TCXO, 2 },
286	};
287
288	static const struct clk_parent_data gcc_parent_data_11[] = {
289	{ .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE },
290	{ .index = DT_BI_TCXO },
291	};
292
293	static const struct parent_map gcc_parent_map_11[] = {
294	{ P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
295	{ P_BI_TCXO, 2 },
296	};
297
298	static const struct clk_parent_data gcc_parent_data_12[] = {
299	{ .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE },
300	{ .index = DT_BI_TCXO },
301	};
302
303	static const struct parent_map gcc_parent_map_12[] = {
304	{ P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
305	{ P_BI_TCXO, 2 },
306	};
307
308	static const struct clk_parent_data gcc_parent_data_9[] = {
309	{ .index = DT_BI_TCXO },
310	{ .hw = &gcc_gpll0.clkr.hw },
311	{ .hw = &gcc_gpll9.clkr.hw },
312	{ .hw = &gcc_gpll4.clkr.hw },
313	{ .hw = &gcc_gpll0_out_even.clkr.hw },
314	};
315
316	static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
317	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
318	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
319	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
320	{ }
321	};
322
323	static struct clk_rcg2 gcc_gp1_clk_src = {
324	.cmd_rcgr = 0x64004,
325	.mnd_width = 16,
326	.hid_width = 5,
327	.parent_map = gcc_parent_map_2,
328	.freq_tbl = ftbl_gcc_gp1_clk_src,
329	.clkr.hw.init = &(const struct clk_init_data) {
330	.name = "gcc_gp1_clk_src",
331	.parent_data = gcc_parent_data_2,
332	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
333	.flags = CLK_SET_RATE_PARENT,
334	.ops = &clk_rcg2_shared_ops,
335	},
336	};
337
338	static struct clk_rcg2 gcc_gp2_clk_src = {
339	.cmd_rcgr = 0x65004,
340	.mnd_width = 16,
341	.hid_width = 5,
342	.parent_map = gcc_parent_map_2,
343	.freq_tbl = ftbl_gcc_gp1_clk_src,
344	.clkr.hw.init = &(const struct clk_init_data) {
345	.name = "gcc_gp2_clk_src",
346	.parent_data = gcc_parent_data_2,
347	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
348	.flags = CLK_SET_RATE_PARENT,
349	.ops = &clk_rcg2_shared_ops,
350	},
351	};
352
353	static struct clk_rcg2 gcc_gp3_clk_src = {
354	.cmd_rcgr = 0x66004,
355	.mnd_width = 16,
356	.hid_width = 5,
357	.parent_map = gcc_parent_map_2,
358	.freq_tbl = ftbl_gcc_gp1_clk_src,
359	.clkr.hw.init = &(const struct clk_init_data) {
360	.name = "gcc_gp3_clk_src",
361	.parent_data = gcc_parent_data_2,
362	.num_parents = ARRAY_SIZE(gcc_parent_data_2),
363	.flags = CLK_SET_RATE_PARENT,
364	.ops = &clk_rcg2_shared_ops,
365	},
366	};
367
368	static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
369	F(19200000, P_BI_TCXO, 1, 0, 0),
370	{ }
371	};
372
373	static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
374	.cmd_rcgr = 0xa0180,
375	.mnd_width = 16,
376	.hid_width = 5,
377	.parent_map = gcc_parent_map_1,
378	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
379	.clkr.hw.init = &(const struct clk_init_data) {
380	.name = "gcc_pcie_0_aux_clk_src",
381	.parent_data = gcc_parent_data_1,
382	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
383	.flags = CLK_SET_RATE_PARENT,
384	.ops = &clk_rcg2_shared_ops,
385	},
386	};
387
388	static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
389	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
390	{ }
391	};
392
393	static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
394	.cmd_rcgr = 0xa0054,
395	.mnd_width = 0,
396	.hid_width = 5,
397	.parent_map = gcc_parent_map_0,
398	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
399	.clkr.hw.init = &(const struct clk_init_data) {
400	.name = "gcc_pcie_0_phy_rchng_clk_src",
401	.parent_data = gcc_parent_data_0,
402	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
403	.flags = CLK_SET_RATE_PARENT,
404	.ops = &clk_rcg2_shared_ops,
405	},
406	};
407
408	static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
409	.cmd_rcgr = 0x2c180,
410	.mnd_width = 16,
411	.hid_width = 5,
412	.parent_map = gcc_parent_map_1,
413	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
414	.clkr.hw.init = &(const struct clk_init_data) {
415	.name = "gcc_pcie_1_aux_clk_src",
416	.parent_data = gcc_parent_data_1,
417	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
418	.flags = CLK_SET_RATE_PARENT,
419	.ops = &clk_rcg2_shared_ops,
420	},
421	};
422
423	static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
424	.cmd_rcgr = 0x2c054,
425	.mnd_width = 0,
426	.hid_width = 5,
427	.parent_map = gcc_parent_map_0,
428	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
429	.clkr.hw.init = &(const struct clk_init_data) {
430	.name = "gcc_pcie_1_phy_rchng_clk_src",
431	.parent_data = gcc_parent_data_0,
432	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
433	.flags = CLK_SET_RATE_PARENT,
434	.ops = &clk_rcg2_shared_ops,
435	},
436	};
437
438	static struct clk_rcg2 gcc_pcie_2_aux_clk_src = {
439	.cmd_rcgr = 0x13180,
440	.mnd_width = 16,
441	.hid_width = 5,
442	.parent_map = gcc_parent_map_1,
443	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
444	.clkr.hw.init = &(const struct clk_init_data) {
445	.name = "gcc_pcie_2_aux_clk_src",
446	.parent_data = gcc_parent_data_1,
447	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
448	.flags = CLK_SET_RATE_PARENT,
449	.ops = &clk_rcg2_shared_ops,
450	},
451	};
452
453	static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = {
454	.cmd_rcgr = 0x13054,
455	.mnd_width = 0,
456	.hid_width = 5,
457	.parent_map = gcc_parent_map_0,
458	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
459	.clkr.hw.init = &(const struct clk_init_data) {
460	.name = "gcc_pcie_2_phy_rchng_clk_src",
461	.parent_data = gcc_parent_data_0,
462	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
463	.flags = CLK_SET_RATE_PARENT,
464	.ops = &clk_rcg2_shared_ops,
465	},
466	};
467
468	static struct clk_rcg2 gcc_pcie_3_aux_clk_src = {
469	.cmd_rcgr = 0x5808c,
470	.mnd_width = 16,
471	.hid_width = 5,
472	.parent_map = gcc_parent_map_1,
473	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
474	.clkr.hw.init = &(const struct clk_init_data) {
475	.name = "gcc_pcie_3_aux_clk_src",
476	.parent_data = gcc_parent_data_1,
477	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
478	.flags = CLK_SET_RATE_PARENT,
479	.ops = &clk_rcg2_shared_ops,
480	},
481	};
482
483	static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = {
484	.cmd_rcgr = 0x58070,
485	.mnd_width = 0,
486	.hid_width = 5,
487	.parent_map = gcc_parent_map_0,
488	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
489	.clkr.hw.init = &(const struct clk_init_data) {
490	.name = "gcc_pcie_3_phy_rchng_clk_src",
491	.parent_data = gcc_parent_data_0,
492	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
493	.flags = CLK_SET_RATE_PARENT,
494	.ops = &clk_rcg2_shared_ops,
495	},
496	};
497
498	static struct clk_rcg2 gcc_pcie_4_aux_clk_src = {
499	.cmd_rcgr = 0x6b080,
500	.mnd_width = 16,
501	.hid_width = 5,
502	.parent_map = gcc_parent_map_1,
503	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
504	.clkr.hw.init = &(const struct clk_init_data) {
505	.name = "gcc_pcie_4_aux_clk_src",
506	.parent_data = gcc_parent_data_1,
507	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
508	.flags = CLK_SET_RATE_PARENT,
509	.ops = &clk_rcg2_shared_ops,
510	},
511	};
512
513	static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = {
514	.cmd_rcgr = 0x6b064,
515	.mnd_width = 0,
516	.hid_width = 5,
517	.parent_map = gcc_parent_map_0,
518	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
519	.clkr.hw.init = &(const struct clk_init_data) {
520	.name = "gcc_pcie_4_phy_rchng_clk_src",
521	.parent_data = gcc_parent_data_0,
522	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
523	.flags = CLK_SET_RATE_PARENT,
524	.ops = &clk_rcg2_shared_ops,
525	},
526	};
527
528	static struct clk_rcg2 gcc_pcie_5_aux_clk_src = {
529	.cmd_rcgr = 0x2f080,
530	.mnd_width = 16,
531	.hid_width = 5,
532	.parent_map = gcc_parent_map_1,
533	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
534	.clkr.hw.init = &(const struct clk_init_data) {
535	.name = "gcc_pcie_5_aux_clk_src",
536	.parent_data = gcc_parent_data_1,
537	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
538	.flags = CLK_SET_RATE_PARENT,
539	.ops = &clk_rcg2_shared_ops,
540	},
541	};
542
543	static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = {
544	.cmd_rcgr = 0x2f064,
545	.mnd_width = 0,
546	.hid_width = 5,
547	.parent_map = gcc_parent_map_0,
548	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
549	.clkr.hw.init = &(const struct clk_init_data) {
550	.name = "gcc_pcie_5_phy_rchng_clk_src",
551	.parent_data = gcc_parent_data_0,
552	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
553	.flags = CLK_SET_RATE_PARENT,
554	.ops = &clk_rcg2_shared_ops,
555	},
556	};
557
558	static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = {
559	.cmd_rcgr = 0x3108c,
560	.mnd_width = 16,
561	.hid_width = 5,
562	.parent_map = gcc_parent_map_1,
563	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
564	.clkr.hw.init = &(const struct clk_init_data) {
565	.name = "gcc_pcie_6a_aux_clk_src",
566	.parent_data = gcc_parent_data_1,
567	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
568	.flags = CLK_SET_RATE_PARENT,
569	.ops = &clk_rcg2_shared_ops,
570	},
571	};
572
573	static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = {
574	.cmd_rcgr = 0x31070,
575	.mnd_width = 0,
576	.hid_width = 5,
577	.parent_map = gcc_parent_map_0,
578	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
579	.clkr.hw.init = &(const struct clk_init_data) {
580	.name = "gcc_pcie_6a_phy_rchng_clk_src",
581	.parent_data = gcc_parent_data_0,
582	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
583	.flags = CLK_SET_RATE_PARENT,
584	.ops = &clk_rcg2_shared_ops,
585	},
586	};
587
588	static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = {
589	.cmd_rcgr = 0x8d08c,
590	.mnd_width = 16,
591	.hid_width = 5,
592	.parent_map = gcc_parent_map_1,
593	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
594	.clkr.hw.init = &(const struct clk_init_data) {
595	.name = "gcc_pcie_6b_aux_clk_src",
596	.parent_data = gcc_parent_data_1,
597	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
598	.flags = CLK_SET_RATE_PARENT,
599	.ops = &clk_rcg2_shared_ops,
600	},
601	};
602
603	static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = {
604	.cmd_rcgr = 0x8d070,
605	.mnd_width = 0,
606	.hid_width = 5,
607	.parent_map = gcc_parent_map_0,
608	.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
609	.clkr.hw.init = &(const struct clk_init_data) {
610	.name = "gcc_pcie_6b_phy_rchng_clk_src",
611	.parent_data = gcc_parent_data_0,
612	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
613	.flags = CLK_SET_RATE_PARENT,
614	.ops = &clk_rcg2_shared_ops,
615	},
616	};
617
618	static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = {
619	.cmd_rcgr = 0xa400c,
620	.mnd_width = 0,
621	.hid_width = 5,
622	.parent_map = gcc_parent_map_3,
623	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
624	.clkr.hw.init = &(const struct clk_init_data) {
625	.name = "gcc_pcie_rscc_xo_clk_src",
626	.parent_data = gcc_parent_data_3,
627	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
628	.flags = CLK_SET_RATE_PARENT,
629	.ops = &clk_rcg2_shared_ops,
630	},
631	};
632
633	static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
634	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
635	{ }
636	};
637
638	static struct clk_rcg2 gcc_pdm2_clk_src = {
639	.cmd_rcgr = 0x33010,
640	.mnd_width = 0,
641	.hid_width = 5,
642	.parent_map = gcc_parent_map_0,
643	.freq_tbl = ftbl_gcc_pdm2_clk_src,
644	.clkr.hw.init = &(const struct clk_init_data) {
645	.name = "gcc_pdm2_clk_src",
646	.parent_data = gcc_parent_data_0,
647	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
648	.flags = CLK_SET_RATE_PARENT,
649	.ops = &clk_rcg2_shared_ops,
650	},
651	};
652
653	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
654	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
655	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
656	F(19200000, P_BI_TCXO, 1, 0, 0),
657	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
658	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
659	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
660	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
661	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
662	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
663	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
664	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
665	{ }
666	};
667
668	static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
669	.name = "gcc_qupv3_wrap0_s0_clk_src",
670	.parent_data = gcc_parent_data_0,
671	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
672	.flags = CLK_SET_RATE_PARENT,
673	.ops = &clk_rcg2_shared_ops,
674	};
675
676	static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
677	.cmd_rcgr = 0x42010,
678	.mnd_width = 16,
679	.hid_width = 5,
680	.parent_map = gcc_parent_map_0,
681	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
682	.clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init,
683	};
684
685	static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
686	.name = "gcc_qupv3_wrap0_s1_clk_src",
687	.parent_data = gcc_parent_data_0,
688	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
689	.flags = CLK_SET_RATE_PARENT,
690	.ops = &clk_rcg2_shared_ops,
691	};
692
693	static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
694	.cmd_rcgr = 0x42148,
695	.mnd_width = 16,
696	.hid_width = 5,
697	.parent_map = gcc_parent_map_0,
698	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
699	.clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init,
700	};
701
702	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {
703	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
704	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
705	F(19200000, P_BI_TCXO, 1, 0, 0),
706	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
707	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
708	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
709	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
710	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
711	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
712	F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
713	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
714	{ }
715	};
716
717	static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
718	.name = "gcc_qupv3_wrap0_s2_clk_src",
719	.parent_data = gcc_parent_data_0,
720	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
721	.flags = CLK_SET_RATE_PARENT,
722	.ops = &clk_rcg2_shared_ops,
723	};
724
725	static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
726	.cmd_rcgr = 0x42288,
727	.mnd_width = 16,
728	.hid_width = 5,
729	.parent_map = gcc_parent_map_0,
730	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
731	.clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init,
732	};
733
734	static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
735	.name = "gcc_qupv3_wrap0_s3_clk_src",
736	.parent_data = gcc_parent_data_0,
737	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
738	.flags = CLK_SET_RATE_PARENT,
739	.ops = &clk_rcg2_shared_ops,
740	};
741
742	static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
743	.cmd_rcgr = 0x423c8,
744	.mnd_width = 16,
745	.hid_width = 5,
746	.parent_map = gcc_parent_map_0,
747	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
748	.clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init,
749	};
750
751	static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = {
752	F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
753	F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
754	F(19200000, P_BI_TCXO, 1, 0, 0),
755	F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
756	F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
757	F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
758	F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
759	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
760	F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
761	F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
762	F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
763	{ }
764	};
765
766	static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
767	.name = "gcc_qupv3_wrap0_s4_clk_src",
768	.parent_data = gcc_parent_data_0,
769	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
770	.flags = CLK_SET_RATE_PARENT,
771	.ops = &clk_rcg2_shared_ops,
772	};
773
774	static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
775	.cmd_rcgr = 0x42500,
776	.mnd_width = 16,
777	.hid_width = 5,
778	.parent_map = gcc_parent_map_0,
779	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
780	.clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init,
781	};
782
783	static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
784	.name = "gcc_qupv3_wrap0_s5_clk_src",
785	.parent_data = gcc_parent_data_0,
786	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
787	.flags = CLK_SET_RATE_PARENT,
788	.ops = &clk_rcg2_shared_ops,
789	};
790
791	static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
792	.cmd_rcgr = 0x42638,
793	.mnd_width = 16,
794	.hid_width = 5,
795	.parent_map = gcc_parent_map_0,
796	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
797	.clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init,
798	};
799
800	static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
801	.name = "gcc_qupv3_wrap0_s6_clk_src",
802	.parent_data = gcc_parent_data_0,
803	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
804	.flags = CLK_SET_RATE_PARENT,
805	.ops = &clk_rcg2_shared_ops,
806	};
807
808	static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
809	.cmd_rcgr = 0x42770,
810	.mnd_width = 16,
811	.hid_width = 5,
812	.parent_map = gcc_parent_map_0,
813	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
814	.clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init,
815	};
816
817	static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
818	.name = "gcc_qupv3_wrap0_s7_clk_src",
819	.parent_data = gcc_parent_data_0,
820	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
821	.flags = CLK_SET_RATE_PARENT,
822	.ops = &clk_rcg2_shared_ops,
823	};
824
825	static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
826	.cmd_rcgr = 0x428a8,
827	.mnd_width = 16,
828	.hid_width = 5,
829	.parent_map = gcc_parent_map_0,
830	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
831	.clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init,
832	};
833
834	static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
835	.name = "gcc_qupv3_wrap1_s0_clk_src",
836	.parent_data = gcc_parent_data_0,
837	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
838	.flags = CLK_SET_RATE_PARENT,
839	.ops = &clk_rcg2_shared_ops,
840	};
841
842	static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
843	.cmd_rcgr = 0x18010,
844	.mnd_width = 16,
845	.hid_width = 5,
846	.parent_map = gcc_parent_map_0,
847	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
848	.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
849	};
850
851	static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
852	.name = "gcc_qupv3_wrap1_s1_clk_src",
853	.parent_data = gcc_parent_data_0,
854	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
855	.flags = CLK_SET_RATE_PARENT,
856	.ops = &clk_rcg2_shared_ops,
857	};
858
859	static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
860	.cmd_rcgr = 0x18148,
861	.mnd_width = 16,
862	.hid_width = 5,
863	.parent_map = gcc_parent_map_0,
864	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
865	.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
866	};
867
868	static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
869	.name = "gcc_qupv3_wrap1_s2_clk_src",
870	.parent_data = gcc_parent_data_0,
871	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
872	.flags = CLK_SET_RATE_PARENT,
873	.ops = &clk_rcg2_shared_ops,
874	};
875
876	static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
877	.cmd_rcgr = 0x18288,
878	.mnd_width = 16,
879	.hid_width = 5,
880	.parent_map = gcc_parent_map_0,
881	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
882	.clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init,
883	};
884
885	static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
886	.name = "gcc_qupv3_wrap1_s3_clk_src",
887	.parent_data = gcc_parent_data_0,
888	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
889	.flags = CLK_SET_RATE_PARENT,
890	.ops = &clk_rcg2_shared_ops,
891	};
892
893	static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
894	.cmd_rcgr = 0x183c8,
895	.mnd_width = 16,
896	.hid_width = 5,
897	.parent_map = gcc_parent_map_0,
898	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
899	.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
900	};
901
902	static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
903	.name = "gcc_qupv3_wrap1_s4_clk_src",
904	.parent_data = gcc_parent_data_0,
905	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
906	.flags = CLK_SET_RATE_PARENT,
907	.ops = &clk_rcg2_shared_ops,
908	};
909
910	static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
911	.cmd_rcgr = 0x18500,
912	.mnd_width = 16,
913	.hid_width = 5,
914	.parent_map = gcc_parent_map_0,
915	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
916	.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
917	};
918
919	static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
920	.name = "gcc_qupv3_wrap1_s5_clk_src",
921	.parent_data = gcc_parent_data_0,
922	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
923	.flags = CLK_SET_RATE_PARENT,
924	.ops = &clk_rcg2_shared_ops,
925	};
926
927	static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
928	.cmd_rcgr = 0x18638,
929	.mnd_width = 16,
930	.hid_width = 5,
931	.parent_map = gcc_parent_map_0,
932	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
933	.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
934	};
935
936	static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
937	.name = "gcc_qupv3_wrap1_s6_clk_src",
938	.parent_data = gcc_parent_data_0,
939	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
940	.flags = CLK_SET_RATE_PARENT,
941	.ops = &clk_rcg2_shared_ops,
942	};
943
944	static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
945	.cmd_rcgr = 0x18770,
946	.mnd_width = 16,
947	.hid_width = 5,
948	.parent_map = gcc_parent_map_0,
949	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
950	.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
951	};
952
953	static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
954	.name = "gcc_qupv3_wrap1_s7_clk_src",
955	.parent_data = gcc_parent_data_0,
956	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
957	.flags = CLK_SET_RATE_PARENT,
958	.ops = &clk_rcg2_shared_ops,
959	};
960
961	static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
962	.cmd_rcgr = 0x188a8,
963	.mnd_width = 16,
964	.hid_width = 5,
965	.parent_map = gcc_parent_map_0,
966	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
967	.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
968	};
969
970	static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
971	.name = "gcc_qupv3_wrap2_s0_clk_src",
972	.parent_data = gcc_parent_data_0,
973	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
974	.flags = CLK_SET_RATE_PARENT,
975	.ops = &clk_rcg2_shared_ops,
976	};
977
978	static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
979	.cmd_rcgr = 0x1e010,
980	.mnd_width = 16,
981	.hid_width = 5,
982	.parent_map = gcc_parent_map_0,
983	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
984	.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
985	};
986
987	static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
988	.name = "gcc_qupv3_wrap2_s1_clk_src",
989	.parent_data = gcc_parent_data_0,
990	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
991	.flags = CLK_SET_RATE_PARENT,
992	.ops = &clk_rcg2_shared_ops,
993	};
994
995	static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
996	.cmd_rcgr = 0x1e148,
997	.mnd_width = 16,
998	.hid_width = 5,
999	.parent_map = gcc_parent_map_0,
1000	.freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
1001	.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
1002	};
1003
1004	static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
1005	.name = "gcc_qupv3_wrap2_s2_clk_src",
1006	.parent_data = gcc_parent_data_0,
1007	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1008	.flags = CLK_SET_RATE_PARENT,
1009	.ops = &clk_rcg2_shared_ops,
1010	};
1011
1012	static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
1013	.cmd_rcgr = 0x1e288,
1014	.mnd_width = 16,
1015	.hid_width = 5,
1016	.parent_map = gcc_parent_map_0,
1017	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1018	.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
1019	};
1020
1021	static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
1022	.name = "gcc_qupv3_wrap2_s3_clk_src",
1023	.parent_data = gcc_parent_data_0,
1024	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1025	.flags = CLK_SET_RATE_PARENT,
1026	.ops = &clk_rcg2_shared_ops,
1027	};
1028
1029	static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
1030	.cmd_rcgr = 0x1e3c8,
1031	.mnd_width = 16,
1032	.hid_width = 5,
1033	.parent_map = gcc_parent_map_0,
1034	.freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src,
1035	.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
1036	};
1037
1038	static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
1039	.name = "gcc_qupv3_wrap2_s4_clk_src",
1040	.parent_data = gcc_parent_data_0,
1041	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1042	.flags = CLK_SET_RATE_PARENT,
1043	.ops = &clk_rcg2_shared_ops,
1044	};
1045
1046	static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
1047	.cmd_rcgr = 0x1e500,
1048	.mnd_width = 16,
1049	.hid_width = 5,
1050	.parent_map = gcc_parent_map_0,
1051	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1052	.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
1053	};
1054
1055	static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
1056	.name = "gcc_qupv3_wrap2_s5_clk_src",
1057	.parent_data = gcc_parent_data_0,
1058	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1059	.flags = CLK_SET_RATE_PARENT,
1060	.ops = &clk_rcg2_shared_ops,
1061	};
1062
1063	static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
1064	.cmd_rcgr = 0x1e638,
1065	.mnd_width = 16,
1066	.hid_width = 5,
1067	.parent_map = gcc_parent_map_0,
1068	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1069	.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
1070	};
1071
1072	static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
1073	.name = "gcc_qupv3_wrap2_s6_clk_src",
1074	.parent_data = gcc_parent_data_8,
1075	.num_parents = ARRAY_SIZE(gcc_parent_data_8),
1076	.flags = CLK_SET_RATE_PARENT,
1077	.ops = &clk_rcg2_shared_ops,
1078	};
1079
1080	static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
1081	.cmd_rcgr = 0x1e770,
1082	.mnd_width = 16,
1083	.hid_width = 5,
1084	.parent_map = gcc_parent_map_8,
1085	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1086	.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
1087	};
1088
1089	static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
1090	.name = "gcc_qupv3_wrap2_s7_clk_src",
1091	.parent_data = gcc_parent_data_0,
1092	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1093	.flags = CLK_SET_RATE_PARENT,
1094	.ops = &clk_rcg2_shared_ops,
1095	};
1096
1097	static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
1098	.cmd_rcgr = 0x1e8a8,
1099	.mnd_width = 16,
1100	.hid_width = 5,
1101	.parent_map = gcc_parent_map_0,
1102	.freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src,
1103	.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
1104	};
1105
1106	static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1107	F(400000, P_BI_TCXO, 12, 1, 4),
1108	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1109	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1110	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1111	F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
1112	{ }
1113	};
1114
1115	static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
1116	.cmd_rcgr = 0x14018,
1117	.mnd_width = 8,
1118	.hid_width = 5,
1119	.parent_map = gcc_parent_map_9,
1120	.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
1121	.clkr.hw.init = &(const struct clk_init_data) {
1122	.name = "gcc_sdcc2_apps_clk_src",
1123	.parent_data = gcc_parent_data_9,
1124	.num_parents = ARRAY_SIZE(gcc_parent_data_9),
1125	.flags = CLK_SET_RATE_PARENT,
1126	.ops = &clk_rcg2_floor_ops,
1127	},
1128	};
1129
1130	static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
1131	F(400000, P_BI_TCXO, 12, 1, 4),
1132	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1133	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1134	{ }
1135	};
1136
1137	static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
1138	.cmd_rcgr = 0x16018,
1139	.mnd_width = 8,
1140	.hid_width = 5,
1141	.parent_map = gcc_parent_map_0,
1142	.freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
1143	.clkr.hw.init = &(const struct clk_init_data) {
1144	.name = "gcc_sdcc4_apps_clk_src",
1145	.parent_data = gcc_parent_data_0,
1146	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1147	.flags = CLK_SET_RATE_PARENT,
1148	.ops = &clk_rcg2_floor_ops,
1149	},
1150	};
1151
1152	static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
1153	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1154	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1155	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1156	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1157	{ }
1158	};
1159
1160	static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
1161	.cmd_rcgr = 0x77030,
1162	.mnd_width = 8,
1163	.hid_width = 5,
1164	.parent_map = gcc_parent_map_0,
1165	.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
1166	.clkr.hw.init = &(const struct clk_init_data) {
1167	.name = "gcc_ufs_phy_axi_clk_src",
1168	.parent_data = gcc_parent_data_0,
1169	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1170	.flags = CLK_SET_RATE_PARENT,
1171	.ops = &clk_rcg2_shared_ops,
1172	},
1173	};
1174
1175	static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
1176	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1177	F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
1178	F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
1179	{ }
1180	};
1181
1182	static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
1183	.cmd_rcgr = 0x77080,
1184	.mnd_width = 0,
1185	.hid_width = 5,
1186	.parent_map = gcc_parent_map_7,
1187	.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
1188	.clkr.hw.init = &(const struct clk_init_data) {
1189	.name = "gcc_ufs_phy_ice_core_clk_src",
1190	.parent_data = gcc_parent_data_7,
1191	.num_parents = ARRAY_SIZE(gcc_parent_data_7),
1192	.flags = CLK_SET_RATE_PARENT,
1193	.ops = &clk_rcg2_shared_ops,
1194	},
1195	};
1196
1197	static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
1198	.cmd_rcgr = 0x770b4,
1199	.mnd_width = 0,
1200	.hid_width = 5,
1201	.parent_map = gcc_parent_map_3,
1202	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1203	.clkr.hw.init = &(const struct clk_init_data) {
1204	.name = "gcc_ufs_phy_phy_aux_clk_src",
1205	.parent_data = gcc_parent_data_3,
1206	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1207	.flags = CLK_SET_RATE_PARENT,
1208	.ops = &clk_rcg2_shared_ops,
1209	},
1210	};
1211
1212	static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
1213	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
1214	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
1215	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
1216	{ }
1217	};
1218
1219	static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
1220	.cmd_rcgr = 0x77098,
1221	.mnd_width = 0,
1222	.hid_width = 5,
1223	.parent_map = gcc_parent_map_0,
1224	.freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src,
1225	.clkr.hw.init = &(const struct clk_init_data) {
1226	.name = "gcc_ufs_phy_unipro_core_clk_src",
1227	.parent_data = gcc_parent_data_0,
1228	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1229	.flags = CLK_SET_RATE_PARENT,
1230	.ops = &clk_rcg2_shared_ops,
1231	},
1232	};
1233
1234	static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
1235	F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
1236	F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
1237	{ }
1238	};
1239
1240	static struct clk_rcg2 gcc_usb20_master_clk_src = {
1241	.cmd_rcgr = 0x2902c,
1242	.mnd_width = 8,
1243	.hid_width = 5,
1244	.parent_map = gcc_parent_map_0,
1245	.freq_tbl = ftbl_gcc_usb20_master_clk_src,
1246	.clkr.hw.init = &(const struct clk_init_data) {
1247	.name = "gcc_usb20_master_clk_src",
1248	.parent_data = gcc_parent_data_0,
1249	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1250	.flags = CLK_SET_RATE_PARENT,
1251	.ops = &clk_rcg2_shared_ops,
1252	},
1253	};
1254
1255	static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = {
1256	.cmd_rcgr = 0x29158,
1257	.mnd_width = 0,
1258	.hid_width = 5,
1259	.parent_map = gcc_parent_map_0,
1260	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1261	.clkr.hw.init = &(const struct clk_init_data) {
1262	.name = "gcc_usb20_mock_utmi_clk_src",
1263	.parent_data = gcc_parent_data_0,
1264	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1265	.flags = CLK_SET_RATE_PARENT,
1266	.ops = &clk_rcg2_shared_ops,
1267	},
1268	};
1269
1270	static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = {
1271	F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
1272	F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
1273	F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
1274	F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
1275	{ }
1276	};
1277
1278	static struct clk_rcg2 gcc_usb30_mp_master_clk_src = {
1279	.cmd_rcgr = 0x1702c,
1280	.mnd_width = 8,
1281	.hid_width = 5,
1282	.parent_map = gcc_parent_map_0,
1283	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1284	.clkr.hw.init = &(const struct clk_init_data) {
1285	.name = "gcc_usb30_mp_master_clk_src",
1286	.parent_data = gcc_parent_data_0,
1287	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1288	.flags = CLK_SET_RATE_PARENT,
1289	.ops = &clk_rcg2_shared_ops,
1290	},
1291	};
1292
1293	static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = {
1294	.cmd_rcgr = 0x17158,
1295	.mnd_width = 0,
1296	.hid_width = 5,
1297	.parent_map = gcc_parent_map_0,
1298	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1299	.clkr.hw.init = &(const struct clk_init_data) {
1300	.name = "gcc_usb30_mp_mock_utmi_clk_src",
1301	.parent_data = gcc_parent_data_0,
1302	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1303	.flags = CLK_SET_RATE_PARENT,
1304	.ops = &clk_rcg2_shared_ops,
1305	},
1306	};
1307
1308	static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1309	.cmd_rcgr = 0x3902c,
1310	.mnd_width = 8,
1311	.hid_width = 5,
1312	.parent_map = gcc_parent_map_0,
1313	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1314	.clkr.hw.init = &(const struct clk_init_data) {
1315	.name = "gcc_usb30_prim_master_clk_src",
1316	.parent_data = gcc_parent_data_0,
1317	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1318	.flags = CLK_SET_RATE_PARENT,
1319	.ops = &clk_rcg2_shared_ops,
1320	},
1321	};
1322
1323	static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1324	.cmd_rcgr = 0x39044,
1325	.mnd_width = 0,
1326	.hid_width = 5,
1327	.parent_map = gcc_parent_map_0,
1328	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1329	.clkr.hw.init = &(const struct clk_init_data) {
1330	.name = "gcc_usb30_prim_mock_utmi_clk_src",
1331	.parent_data = gcc_parent_data_0,
1332	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1333	.flags = CLK_SET_RATE_PARENT,
1334	.ops = &clk_rcg2_shared_ops,
1335	},
1336	};
1337
1338	static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1339	.cmd_rcgr = 0xa102c,
1340	.mnd_width = 8,
1341	.hid_width = 5,
1342	.parent_map = gcc_parent_map_0,
1343	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1344	.clkr.hw.init = &(const struct clk_init_data) {
1345	.name = "gcc_usb30_sec_master_clk_src",
1346	.parent_data = gcc_parent_data_0,
1347	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1348	.flags = CLK_SET_RATE_PARENT,
1349	.ops = &clk_rcg2_shared_ops,
1350	},
1351	};
1352
1353	static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1354	.cmd_rcgr = 0xa1044,
1355	.mnd_width = 0,
1356	.hid_width = 5,
1357	.parent_map = gcc_parent_map_0,
1358	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1359	.clkr.hw.init = &(const struct clk_init_data) {
1360	.name = "gcc_usb30_sec_mock_utmi_clk_src",
1361	.parent_data = gcc_parent_data_0,
1362	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1363	.flags = CLK_SET_RATE_PARENT,
1364	.ops = &clk_rcg2_shared_ops,
1365	},
1366	};
1367
1368	static struct clk_rcg2 gcc_usb30_tert_master_clk_src = {
1369	.cmd_rcgr = 0xa202c,
1370	.mnd_width = 8,
1371	.hid_width = 5,
1372	.parent_map = gcc_parent_map_0,
1373	.freq_tbl = ftbl_gcc_usb30_mp_master_clk_src,
1374	.clkr.hw.init = &(const struct clk_init_data) {
1375	.name = "gcc_usb30_tert_master_clk_src",
1376	.parent_data = gcc_parent_data_0,
1377	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1378	.flags = CLK_SET_RATE_PARENT,
1379	.ops = &clk_rcg2_shared_ops,
1380	},
1381	};
1382
1383	static struct clk_rcg2 gcc_usb30_tert_mock_utmi_clk_src = {
1384	.cmd_rcgr = 0xa2044,
1385	.mnd_width = 0,
1386	.hid_width = 5,
1387	.parent_map = gcc_parent_map_0,
1388	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1389	.clkr.hw.init = &(const struct clk_init_data) {
1390	.name = "gcc_usb30_tert_mock_utmi_clk_src",
1391	.parent_data = gcc_parent_data_0,
1392	.num_parents = ARRAY_SIZE(gcc_parent_data_0),
1393	.flags = CLK_SET_RATE_PARENT,
1394	.ops = &clk_rcg2_shared_ops,
1395	},
1396	};
1397
1398	static struct clk_rcg2 gcc_usb3_mp_phy_aux_clk_src = {
1399	.cmd_rcgr = 0x172a0,
1400	.mnd_width = 0,
1401	.hid_width = 5,
1402	.parent_map = gcc_parent_map_1,
1403	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1404	.clkr.hw.init = &(const struct clk_init_data) {
1405	.name = "gcc_usb3_mp_phy_aux_clk_src",
1406	.parent_data = gcc_parent_data_1,
1407	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1408	.flags = CLK_SET_RATE_PARENT,
1409	.ops = &clk_rcg2_shared_ops,
1410	},
1411	};
1412
1413	static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1414	.cmd_rcgr = 0x39074,
1415	.mnd_width = 0,
1416	.hid_width = 5,
1417	.parent_map = gcc_parent_map_1,
1418	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1419	.clkr.hw.init = &(const struct clk_init_data) {
1420	.name = "gcc_usb3_prim_phy_aux_clk_src",
1421	.parent_data = gcc_parent_data_1,
1422	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1423	.flags = CLK_SET_RATE_PARENT,
1424	.ops = &clk_rcg2_shared_ops,
1425	},
1426	};
1427
1428	static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1429	.cmd_rcgr = 0xa1074,
1430	.mnd_width = 0,
1431	.hid_width = 5,
1432	.parent_map = gcc_parent_map_1,
1433	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1434	.clkr.hw.init = &(const struct clk_init_data) {
1435	.name = "gcc_usb3_sec_phy_aux_clk_src",
1436	.parent_data = gcc_parent_data_1,
1437	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1438	.flags = CLK_SET_RATE_PARENT,
1439	.ops = &clk_rcg2_shared_ops,
1440	},
1441	};
1442
1443	static struct clk_rcg2 gcc_usb3_tert_phy_aux_clk_src = {
1444	.cmd_rcgr = 0xa2074,
1445	.mnd_width = 0,
1446	.hid_width = 5,
1447	.parent_map = gcc_parent_map_1,
1448	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1449	.clkr.hw.init = &(const struct clk_init_data) {
1450	.name = "gcc_usb3_tert_phy_aux_clk_src",
1451	.parent_data = gcc_parent_data_1,
1452	.num_parents = ARRAY_SIZE(gcc_parent_data_1),
1453	.flags = CLK_SET_RATE_PARENT,
1454	.ops = &clk_rcg2_shared_ops,
1455	},
1456	};
1457
1458	static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = {
1459	F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),
1460	F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
1461	F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
1462	{ }
1463	};
1464
1465	static struct clk_rcg2 gcc_usb4_0_master_clk_src = {
1466	.cmd_rcgr = 0x9f024,
1467	.mnd_width = 8,
1468	.hid_width = 5,
1469	.parent_map = gcc_parent_map_4,
1470	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
1471	.clkr.hw.init = &(const struct clk_init_data) {
1472	.name = "gcc_usb4_0_master_clk_src",
1473	.parent_data = gcc_parent_data_4,
1474	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1475	.flags = CLK_SET_RATE_PARENT,
1476	.ops = &clk_rcg2_shared_ops,
1477	},
1478	};
1479
1480	static const struct freq_tbl ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src[] = {
1481	F(19200000, P_BI_TCXO, 1, 0, 0),
1482	F(125000000, P_GCC_GPLL7_OUT_MAIN, 8, 0, 0),
1483	F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1484	{ }
1485	};
1486
1487	static struct clk_rcg2 gcc_usb4_0_phy_pcie_pipe_clk_src = {
1488	.cmd_rcgr = 0x9f0e8,
1489	.mnd_width = 0,
1490	.hid_width = 5,
1491	.parent_map = gcc_parent_map_5,
1492	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
1493	.clkr.hw.init = &(const struct clk_init_data) {
1494	.name = "gcc_usb4_0_phy_pcie_pipe_clk_src",
1495	.parent_data = gcc_parent_data_5,
1496	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1497	.flags = CLK_SET_RATE_PARENT,
1498	.ops = &clk_rcg2_shared_ops,
1499	},
1500	};
1501
1502	static struct clk_rcg2 gcc_usb4_0_sb_if_clk_src = {
1503	.cmd_rcgr = 0x9f08c,
1504	.mnd_width = 0,
1505	.hid_width = 5,
1506	.parent_map = gcc_parent_map_3,
1507	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1508	.clkr.hw.init = &(const struct clk_init_data) {
1509	.name = "gcc_usb4_0_sb_if_clk_src",
1510	.parent_data = gcc_parent_data_3,
1511	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1512	.flags = CLK_SET_RATE_PARENT,
1513	.ops = &clk_rcg2_shared_ops,
1514	},
1515	};
1516
1517	static const struct freq_tbl ftbl_gcc_usb4_0_tmu_clk_src[] = {
1518	F(19200000, P_BI_TCXO, 1, 0, 0),
1519	F(250000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
1520	{ }
1521	};
1522
1523	static struct clk_rcg2 gcc_usb4_0_tmu_clk_src = {
1524	.cmd_rcgr = 0x9f070,
1525	.mnd_width = 0,
1526	.hid_width = 5,
1527	.parent_map = gcc_parent_map_6,
1528	.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
1529	.clkr.hw.init = &(const struct clk_init_data) {
1530	.name = "gcc_usb4_0_tmu_clk_src",
1531	.parent_data = gcc_parent_data_6,
1532	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
1533	.flags = CLK_SET_RATE_PARENT,
1534	.ops = &clk_rcg2_shared_ops,
1535	},
1536	};
1537
1538	static struct clk_rcg2 gcc_usb4_1_master_clk_src = {
1539	.cmd_rcgr = 0x2b024,
1540	.mnd_width = 8,
1541	.hid_width = 5,
1542	.parent_map = gcc_parent_map_4,
1543	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
1544	.clkr.hw.init = &(const struct clk_init_data) {
1545	.name = "gcc_usb4_1_master_clk_src",
1546	.parent_data = gcc_parent_data_4,
1547	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1548	.flags = CLK_SET_RATE_PARENT,
1549	.ops = &clk_rcg2_shared_ops,
1550	},
1551	};
1552
1553	static struct clk_rcg2 gcc_usb4_1_phy_pcie_pipe_clk_src = {
1554	.cmd_rcgr = 0x2b0e8,
1555	.mnd_width = 0,
1556	.hid_width = 5,
1557	.parent_map = gcc_parent_map_5,
1558	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
1559	.clkr.hw.init = &(const struct clk_init_data) {
1560	.name = "gcc_usb4_1_phy_pcie_pipe_clk_src",
1561	.parent_data = gcc_parent_data_5,
1562	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1563	.flags = CLK_SET_RATE_PARENT,
1564	.ops = &clk_rcg2_shared_ops,
1565	},
1566	};
1567
1568	static struct clk_rcg2 gcc_usb4_1_sb_if_clk_src = {
1569	.cmd_rcgr = 0x2b08c,
1570	.mnd_width = 0,
1571	.hid_width = 5,
1572	.parent_map = gcc_parent_map_3,
1573	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1574	.clkr.hw.init = &(const struct clk_init_data) {
1575	.name = "gcc_usb4_1_sb_if_clk_src",
1576	.parent_data = gcc_parent_data_3,
1577	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1578	.flags = CLK_SET_RATE_PARENT,
1579	.ops = &clk_rcg2_shared_ops,
1580	},
1581	};
1582
1583	static struct clk_rcg2 gcc_usb4_1_tmu_clk_src = {
1584	.cmd_rcgr = 0x2b070,
1585	.mnd_width = 0,
1586	.hid_width = 5,
1587	.parent_map = gcc_parent_map_6,
1588	.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
1589	.clkr.hw.init = &(const struct clk_init_data) {
1590	.name = "gcc_usb4_1_tmu_clk_src",
1591	.parent_data = gcc_parent_data_6,
1592	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
1593	.flags = CLK_SET_RATE_PARENT,
1594	.ops = &clk_rcg2_shared_ops,
1595	},
1596	};
1597
1598	static struct clk_rcg2 gcc_usb4_2_master_clk_src = {
1599	.cmd_rcgr = 0x11024,
1600	.mnd_width = 8,
1601	.hid_width = 5,
1602	.parent_map = gcc_parent_map_4,
1603	.freq_tbl = ftbl_gcc_usb4_0_master_clk_src,
1604	.clkr.hw.init = &(const struct clk_init_data) {
1605	.name = "gcc_usb4_2_master_clk_src",
1606	.parent_data = gcc_parent_data_4,
1607	.num_parents = ARRAY_SIZE(gcc_parent_data_4),
1608	.flags = CLK_SET_RATE_PARENT,
1609	.ops = &clk_rcg2_shared_ops,
1610	},
1611	};
1612
1613	static struct clk_rcg2 gcc_usb4_2_phy_pcie_pipe_clk_src = {
1614	.cmd_rcgr = 0x110e8,
1615	.mnd_width = 0,
1616	.hid_width = 5,
1617	.parent_map = gcc_parent_map_5,
1618	.freq_tbl = ftbl_gcc_usb4_0_phy_pcie_pipe_clk_src,
1619	.clkr.hw.init = &(const struct clk_init_data) {
1620	.name = "gcc_usb4_2_phy_pcie_pipe_clk_src",
1621	.parent_data = gcc_parent_data_5,
1622	.num_parents = ARRAY_SIZE(gcc_parent_data_5),
1623	.flags = CLK_SET_RATE_PARENT,
1624	.ops = &clk_rcg2_shared_ops,
1625	},
1626	};
1627
1628	static struct clk_rcg2 gcc_usb4_2_sb_if_clk_src = {
1629	.cmd_rcgr = 0x1108c,
1630	.mnd_width = 0,
1631	.hid_width = 5,
1632	.parent_map = gcc_parent_map_3,
1633	.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
1634	.clkr.hw.init = &(const struct clk_init_data) {
1635	.name = "gcc_usb4_2_sb_if_clk_src",
1636	.parent_data = gcc_parent_data_3,
1637	.num_parents = ARRAY_SIZE(gcc_parent_data_3),
1638	.flags = CLK_SET_RATE_PARENT,
1639	.ops = &clk_rcg2_shared_ops,
1640	},
1641	};
1642
1643	static struct clk_rcg2 gcc_usb4_2_tmu_clk_src = {
1644	.cmd_rcgr = 0x11070,
1645	.mnd_width = 0,
1646	.hid_width = 5,
1647	.parent_map = gcc_parent_map_6,
1648	.freq_tbl = ftbl_gcc_usb4_0_tmu_clk_src,
1649	.clkr.hw.init = &(const struct clk_init_data) {
1650	.name = "gcc_usb4_2_tmu_clk_src",
1651	.parent_data = gcc_parent_data_6,
1652	.num_parents = ARRAY_SIZE(gcc_parent_data_6),
1653	.flags = CLK_SET_RATE_PARENT,
1654	.ops = &clk_rcg2_shared_ops,
1655	},
1656	};
1657
1658	static struct clk_regmap_phy_mux gcc_pcie_3_pipe_clk_src = {
1659	.reg = 0x58088,
1660	.clkr = {
1661	.hw.init = &(struct clk_init_data){
1662	.name = "gcc_pcie_3_pipe_clk_src",
1663	.parent_data = &(const struct clk_parent_data){
1664	.index = DT_PCIE_3_PIPE,
1665	},
1666	.num_parents = 1,
1667	.ops = &clk_regmap_phy_mux_ops,
1668	},
1669	},
1670	};
1671
1672	static struct clk_regmap_div gcc_pcie_3_pipe_div_clk_src = {
1673	.reg = 0x5806c,
1674	.shift = 0,
1675	.width = 4,
1676	.clkr.hw.init = &(const struct clk_init_data) {
1677	.name = "gcc_pcie_3_pipe_div_clk_src",
1678	.parent_hws = (const struct clk_hw*[]) {
1679	&gcc_pcie_3_pipe_clk_src.clkr.hw,
1680	},
1681	.num_parents = 1,
1682	.ops = &clk_regmap_div_ro_ops,
1683	},
1684	};
1685
1686	static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
1687	.reg = 0x6b07c,
1688	.clkr = {
1689	.hw.init = &(struct clk_init_data){
1690	.name = "gcc_pcie_4_pipe_clk_src",
1691	.parent_data = &(const struct clk_parent_data){
1692	.index = DT_PCIE_4_PIPE,
1693	},
1694	.num_parents = 1,
1695	.ops = &clk_regmap_phy_mux_ops,
1696	},
1697	},
1698	};
1699
1700	static struct clk_regmap_div gcc_pcie_4_pipe_div_clk_src = {
1701	.reg = 0x6b060,
1702	.shift = 0,
1703	.width = 4,
1704	.clkr.hw.init = &(const struct clk_init_data) {
1705	.name = "gcc_pcie_4_pipe_div_clk_src",
1706	.parent_hws = (const struct clk_hw*[]) {
1707	&gcc_pcie_4_pipe_clk_src.clkr.hw,
1708	},
1709	.num_parents = 1,
1710	.ops = &clk_regmap_div_ro_ops,
1711	},
1712	};
1713
1714	static struct clk_regmap_phy_mux gcc_pcie_5_pipe_clk_src = {
1715	.reg = 0x2f07c,
1716	.clkr = {
1717	.hw.init = &(struct clk_init_data){
1718	.name = "gcc_pcie_5_pipe_clk_src",
1719	.parent_data = &(const struct clk_parent_data){
1720	.index = DT_PCIE_5_PIPE,
1721	},
1722	.num_parents = 1,
1723	.ops = &clk_regmap_phy_mux_ops,
1724	},
1725	},
1726	};
1727
1728	static struct clk_regmap_div gcc_pcie_5_pipe_div_clk_src = {
1729	.reg = 0x2f060,
1730	.shift = 0,
1731	.width = 4,
1732	.clkr.hw.init = &(const struct clk_init_data) {
1733	.name = "gcc_pcie_5_pipe_div_clk_src",
1734	.parent_hws = (const struct clk_hw*[]) {
1735	&gcc_pcie_5_pipe_clk_src.clkr.hw,
1736	},
1737	.num_parents = 1,
1738	.ops = &clk_regmap_div_ro_ops,
1739	},
1740	};
1741
1742	static struct clk_regmap_phy_mux gcc_pcie_6a_pipe_clk_src = {
1743	.reg = 0x31088,
1744	.clkr = {
1745	.hw.init = &(struct clk_init_data){
1746	.name = "gcc_pcie_6a_pipe_clk_src",
1747	.parent_data = &(const struct clk_parent_data){
1748	.index = DT_PCIE_6A_PIPE,
1749	},
1750	.num_parents = 1,
1751	.ops = &clk_regmap_phy_mux_ops,
1752	},
1753	},
1754	};
1755
1756	static struct clk_regmap_div gcc_pcie_6a_pipe_div_clk_src = {
1757	.reg = 0x3106c,
1758	.shift = 0,
1759	.width = 4,
1760	.clkr.hw.init = &(const struct clk_init_data) {
1761	.name = "gcc_pcie_6a_pipe_div_clk_src",
1762	.parent_hws = (const struct clk_hw*[]) {
1763	&gcc_pcie_6a_pipe_clk_src.clkr.hw,
1764	},
1765	.num_parents = 1,
1766	.ops = &clk_regmap_div_ro_ops,
1767	},
1768	};
1769
1770	static struct clk_regmap_phy_mux gcc_pcie_6b_pipe_clk_src = {
1771	.reg = 0x8d088,
1772	.clkr = {
1773	.hw.init = &(struct clk_init_data){
1774	.name = "gcc_pcie_6b_pipe_clk_src",
1775	.parent_data = &(const struct clk_parent_data){
1776	.index = DT_PCIE_6B_PIPE,
1777	},
1778	.num_parents = 1,
1779	.ops = &clk_regmap_phy_mux_ops,
1780	},
1781	},
1782	};
1783
1784	static struct clk_regmap_div gcc_pcie_6b_pipe_div_clk_src = {
1785	.reg = 0x8d06c,
1786	.shift = 0,
1787	.width = 4,
1788	.clkr.hw.init = &(const struct clk_init_data) {
1789	.name = "gcc_pcie_6b_pipe_div_clk_src",
1790	.parent_hws = (const struct clk_hw*[]) {
1791	&gcc_pcie_6b_pipe_clk_src.clkr.hw,
1792	},
1793	.num_parents = 1,
1794	.ops = &clk_regmap_div_ro_ops,
1795	},
1796	};
1797
1798	static struct clk_regmap_div gcc_qupv3_wrap0_s2_div_clk_src = {
1799	.reg = 0x42284,
1800	.shift = 0,
1801	.width = 4,
1802	.clkr.hw.init = &(const struct clk_init_data) {
1803	.name = "gcc_qupv3_wrap0_s2_div_clk_src",
1804	.parent_hws = (const struct clk_hw*[]) {
1805	&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
1806	},
1807	.num_parents = 1,
1808	.flags = CLK_SET_RATE_PARENT,
1809	.ops = &clk_regmap_div_ro_ops,
1810	},
1811	};
1812
1813	static struct clk_regmap_div gcc_qupv3_wrap0_s3_div_clk_src = {
1814	.reg = 0x423c4,
1815	.shift = 0,
1816	.width = 4,
1817	.clkr.hw.init = &(const struct clk_init_data) {
1818	.name = "gcc_qupv3_wrap0_s3_div_clk_src",
1819	.parent_hws = (const struct clk_hw*[]) {
1820	&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
1821	},
1822	.num_parents = 1,
1823	.flags = CLK_SET_RATE_PARENT,
1824	.ops = &clk_regmap_div_ro_ops,
1825	},
1826	};
1827
1828	static struct clk_regmap_div gcc_qupv3_wrap1_s2_div_clk_src = {
1829	.reg = 0x18284,
1830	.shift = 0,
1831	.width = 4,
1832	.clkr.hw.init = &(const struct clk_init_data) {
1833	.name = "gcc_qupv3_wrap1_s2_div_clk_src",
1834	.parent_hws = (const struct clk_hw*[]) {
1835	&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
1836	},
1837	.num_parents = 1,
1838	.flags = CLK_SET_RATE_PARENT,
1839	.ops = &clk_regmap_div_ro_ops,
1840	},
1841	};
1842
1843	static struct clk_regmap_div gcc_qupv3_wrap1_s3_div_clk_src = {
1844	.reg = 0x183c4,
1845	.shift = 0,
1846	.width = 4,
1847	.clkr.hw.init = &(const struct clk_init_data) {
1848	.name = "gcc_qupv3_wrap1_s3_div_clk_src",
1849	.parent_hws = (const struct clk_hw*[]) {
1850	&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
1851	},
1852	.num_parents = 1,
1853	.flags = CLK_SET_RATE_PARENT,
1854	.ops = &clk_regmap_div_ro_ops,
1855	},
1856	};
1857
1858	static struct clk_regmap_div gcc_qupv3_wrap2_s2_div_clk_src = {
1859	.reg = 0x1e284,
1860	.shift = 0,
1861	.width = 4,
1862	.clkr.hw.init = &(const struct clk_init_data) {
1863	.name = "gcc_qupv3_wrap2_s2_div_clk_src",
1864	.parent_hws = (const struct clk_hw*[]) {
1865	&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
1866	},
1867	.num_parents = 1,
1868	.flags = CLK_SET_RATE_PARENT,
1869	.ops = &clk_regmap_div_ro_ops,
1870	},
1871	};
1872
1873	static struct clk_regmap_div gcc_qupv3_wrap2_s3_div_clk_src = {
1874	.reg = 0x1e3c4,
1875	.shift = 0,
1876	.width = 4,
1877	.clkr.hw.init = &(const struct clk_init_data) {
1878	.name = "gcc_qupv3_wrap2_s3_div_clk_src",
1879	.parent_hws = (const struct clk_hw*[]) {
1880	&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
1881	},
1882	.num_parents = 1,
1883	.flags = CLK_SET_RATE_PARENT,
1884	.ops = &clk_regmap_div_ro_ops,
1885	},
1886	};
1887
1888	static struct clk_regmap_div gcc_usb20_mock_utmi_postdiv_clk_src = {
1889	.reg = 0x29284,
1890	.shift = 0,
1891	.width = 4,
1892	.clkr.hw.init = &(const struct clk_init_data) {
1893	.name = "gcc_usb20_mock_utmi_postdiv_clk_src",
1894	.parent_hws = (const struct clk_hw*[]) {
1895	&gcc_usb20_mock_utmi_clk_src.clkr.hw,
1896	},
1897	.num_parents = 1,
1898	.flags = CLK_SET_RATE_PARENT,
1899	.ops = &clk_regmap_div_ro_ops,
1900	},
1901	};
1902
1903	static struct clk_regmap_div gcc_usb30_mp_mock_utmi_postdiv_clk_src = {
1904	.reg = 0x17284,
1905	.shift = 0,
1906	.width = 4,
1907	.clkr.hw.init = &(const struct clk_init_data) {
1908	.name = "gcc_usb30_mp_mock_utmi_postdiv_clk_src",
1909	.parent_hws = (const struct clk_hw*[]) {
1910	&gcc_usb30_mp_mock_utmi_clk_src.clkr.hw,
1911	},
1912	.num_parents = 1,
1913	.flags = CLK_SET_RATE_PARENT,
1914	.ops = &clk_regmap_div_ro_ops,
1915	},
1916	};
1917
1918	static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
1919	.reg = 0x3905c,
1920	.shift = 0,
1921	.width = 4,
1922	.clkr.hw.init = &(const struct clk_init_data) {
1923	.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
1924	.parent_hws = (const struct clk_hw*[]) {
1925	&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
1926	},
1927	.num_parents = 1,
1928	.flags = CLK_SET_RATE_PARENT,
1929	.ops = &clk_regmap_div_ro_ops,
1930	},
1931	};
1932
1933	static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
1934	.reg = 0xa105c,
1935	.shift = 0,
1936	.width = 4,
1937	.clkr.hw.init = &(const struct clk_init_data) {
1938	.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
1939	.parent_hws = (const struct clk_hw*[]) {
1940	&gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
1941	},
1942	.num_parents = 1,
1943	.flags = CLK_SET_RATE_PARENT,
1944	.ops = &clk_regmap_div_ro_ops,
1945	},
1946	};
1947
1948	static struct clk_regmap_div gcc_usb30_tert_mock_utmi_postdiv_clk_src = {
1949	.reg = 0xa205c,
1950	.shift = 0,
1951	.width = 4,
1952	.clkr.hw.init = &(const struct clk_init_data) {
1953	.name = "gcc_usb30_tert_mock_utmi_postdiv_clk_src",
1954	.parent_hws = (const struct clk_hw*[]) {
1955	&gcc_usb30_tert_mock_utmi_clk_src.clkr.hw,
1956	},
1957	.num_parents = 1,
1958	.flags = CLK_SET_RATE_PARENT,
1959	.ops = &clk_regmap_div_ro_ops,
1960	},
1961	};
1962
1963	static struct clk_branch gcc_aggre_noc_usb_north_axi_clk = {
1964	.halt_reg = 0x2d17c,
1965	.halt_check = BRANCH_HALT_VOTED,
1966	.hwcg_reg = 0x2d17c,
1967	.hwcg_bit = 1,
1968	.clkr = {
1969	.enable_reg = 0x2d17c,
1970	.enable_mask = BIT(0),
1971	.hw.init = &(const struct clk_init_data) {
1972	.name = "gcc_aggre_noc_usb_north_axi_clk",
1973	.ops = &clk_branch2_ops,
1974	},
1975	},
1976	};
1977
1978	static struct clk_branch gcc_aggre_noc_usb_south_axi_clk = {
1979	.halt_reg = 0x2d174,
1980	.halt_check = BRANCH_HALT_VOTED,
1981	.hwcg_reg = 0x2d174,
1982	.hwcg_bit = 1,
1983	.clkr = {
1984	.enable_reg = 0x2d174,
1985	.enable_mask = BIT(0),
1986	.hw.init = &(const struct clk_init_data) {
1987	.name = "gcc_aggre_noc_usb_south_axi_clk",
1988	.ops = &clk_branch2_ops,
1989	},
1990	},
1991	};
1992
1993	static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1994	.halt_reg = 0x770e4,
1995	.halt_check = BRANCH_HALT_VOTED,
1996	.hwcg_reg = 0x770e4,
1997	.hwcg_bit = 1,
1998	.clkr = {
1999	.enable_reg = 0x770e4,
2000	.enable_mask = BIT(0),
2001	.hw.init = &(const struct clk_init_data) {
2002	.name = "gcc_aggre_ufs_phy_axi_clk",
2003	.parent_hws = (const struct clk_hw*[]) {
2004	&gcc_ufs_phy_axi_clk_src.clkr.hw,
2005	},
2006	.num_parents = 1,
2007	.flags = CLK_SET_RATE_PARENT,
2008	.ops = &clk_branch2_ops,
2009	},
2010	},
2011	};
2012
2013	static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
2014	.halt_reg = 0x2928c,
2015	.halt_check = BRANCH_HALT_VOTED,
2016	.hwcg_reg = 0x2928c,
2017	.hwcg_bit = 1,
2018	.clkr = {
2019	.enable_reg = 0x2928c,
2020	.enable_mask = BIT(0),
2021	.hw.init = &(const struct clk_init_data) {
2022	.name = "gcc_aggre_usb2_prim_axi_clk",
2023	.parent_hws = (const struct clk_hw*[]) {
2024	&gcc_usb20_master_clk_src.clkr.hw,
2025	},
2026	.num_parents = 1,
2027	.flags = CLK_SET_RATE_PARENT,
2028	.ops = &clk_branch2_ops,
2029	},
2030	},
2031	};
2032
2033	static struct clk_branch gcc_aggre_usb3_mp_axi_clk = {
2034	.halt_reg = 0x173d0,
2035	.halt_check = BRANCH_HALT_VOTED,
2036	.hwcg_reg = 0x173d0,
2037	.hwcg_bit = 1,
2038	.clkr = {
2039	.enable_reg = 0x173d0,
2040	.enable_mask = BIT(0),
2041	.hw.init = &(const struct clk_init_data) {
2042	.name = "gcc_aggre_usb3_mp_axi_clk",
2043	.parent_hws = (const struct clk_hw*[]) {
2044	&gcc_usb30_mp_master_clk_src.clkr.hw,
2045	},
2046	.num_parents = 1,
2047	.flags = CLK_SET_RATE_PARENT,
2048	.ops = &clk_branch2_ops,
2049	},
2050	},
2051	};
2052
2053	static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
2054	.halt_reg = 0x39090,
2055	.halt_check = BRANCH_HALT_VOTED,
2056	.hwcg_reg = 0x39090,
2057	.hwcg_bit = 1,
2058	.clkr = {
2059	.enable_reg = 0x39090,
2060	.enable_mask = BIT(0),
2061	.hw.init = &(const struct clk_init_data) {
2062	.name = "gcc_aggre_usb3_prim_axi_clk",
2063	.parent_hws = (const struct clk_hw*[]) {
2064	&gcc_usb30_prim_master_clk_src.clkr.hw,
2065	},
2066	.num_parents = 1,
2067	.flags = CLK_SET_RATE_PARENT,
2068	.ops = &clk_branch2_ops,
2069	},
2070	},
2071	};
2072
2073	static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
2074	.halt_reg = 0xa1090,
2075	.halt_check = BRANCH_HALT_VOTED,
2076	.hwcg_reg = 0xa1090,
2077	.hwcg_bit = 1,
2078	.clkr = {
2079	.enable_reg = 0xa1090,
2080	.enable_mask = BIT(0),
2081	.hw.init = &(const struct clk_init_data) {
2082	.name = "gcc_aggre_usb3_sec_axi_clk",
2083	.parent_hws = (const struct clk_hw*[]) {
2084	&gcc_usb30_sec_master_clk_src.clkr.hw,
2085	},
2086	.num_parents = 1,
2087	.flags = CLK_SET_RATE_PARENT,
2088	.ops = &clk_branch2_ops,
2089	},
2090	},
2091	};
2092
2093	static struct clk_branch gcc_aggre_usb3_tert_axi_clk = {
2094	.halt_reg = 0xa2090,
2095	.halt_check = BRANCH_HALT_VOTED,
2096	.hwcg_reg = 0xa2090,
2097	.hwcg_bit = 1,
2098	.clkr = {
2099	.enable_reg = 0xa2090,
2100	.enable_mask = BIT(0),
2101	.hw.init = &(const struct clk_init_data) {
2102	.name = "gcc_aggre_usb3_tert_axi_clk",
2103	.parent_hws = (const struct clk_hw*[]) {
2104	&gcc_usb30_tert_master_clk_src.clkr.hw,
2105	},
2106	.num_parents = 1,
2107	.flags = CLK_SET_RATE_PARENT,
2108	.ops = &clk_branch2_ops,
2109	},
2110	},
2111	};
2112
2113	static struct clk_branch gcc_aggre_usb4_0_axi_clk = {
2114	.halt_reg = 0x9f118,
2115	.halt_check = BRANCH_HALT_VOTED,
2116	.hwcg_reg = 0x9f118,
2117	.hwcg_bit = 1,
2118	.clkr = {
2119	.enable_reg = 0x9f118,
2120	.enable_mask = BIT(0),
2121	.hw.init = &(const struct clk_init_data) {
2122	.name = "gcc_aggre_usb4_0_axi_clk",
2123	.parent_hws = (const struct clk_hw*[]) {
2124	&gcc_usb4_0_master_clk_src.clkr.hw,
2125	},
2126	.num_parents = 1,
2127	.flags = CLK_SET_RATE_PARENT,
2128	.ops = &clk_branch2_ops,
2129	},
2130	},
2131	};
2132
2133	static struct clk_branch gcc_aggre_usb4_1_axi_clk = {
2134	.halt_reg = 0x2b118,
2135	.halt_check = BRANCH_HALT_VOTED,
2136	.hwcg_reg = 0x2b118,
2137	.hwcg_bit = 1,
2138	.clkr = {
2139	.enable_reg = 0x2b118,
2140	.enable_mask = BIT(0),
2141	.hw.init = &(const struct clk_init_data) {
2142	.name = "gcc_aggre_usb4_1_axi_clk",
2143	.parent_hws = (const struct clk_hw*[]) {
2144	&gcc_usb4_1_master_clk_src.clkr.hw,
2145	},
2146	.num_parents = 1,
2147	.flags = CLK_SET_RATE_PARENT,
2148	.ops = &clk_branch2_ops,
2149	},
2150	},
2151	};
2152
2153	static struct clk_branch gcc_aggre_usb4_2_axi_clk = {
2154	.halt_reg = 0x11118,
2155	.halt_check = BRANCH_HALT_VOTED,
2156	.hwcg_reg = 0x11118,
2157	.hwcg_bit = 1,
2158	.clkr = {
2159	.enable_reg = 0x11118,
2160	.enable_mask = BIT(0),
2161	.hw.init = &(const struct clk_init_data) {
2162	.name = "gcc_aggre_usb4_2_axi_clk",
2163	.parent_hws = (const struct clk_hw*[]) {
2164	&gcc_usb4_2_master_clk_src.clkr.hw,
2165	},
2166	.num_parents = 1,
2167	.flags = CLK_SET_RATE_PARENT,
2168	.ops = &clk_branch2_ops,
2169	},
2170	},
2171	};
2172
2173	static struct clk_branch gcc_aggre_usb_noc_axi_clk = {
2174	.halt_reg = 0x2d034,
2175	.halt_check = BRANCH_HALT_VOTED,
2176	.hwcg_reg = 0x2d034,
2177	.hwcg_bit = 1,
2178	.clkr = {
2179	.enable_reg = 0x2d034,
2180	.enable_mask = BIT(0),
2181	.hw.init = &(const struct clk_init_data) {
2182	.name = "gcc_aggre_usb_noc_axi_clk",
2183	.ops = &clk_branch2_ops,
2184	},
2185	},
2186	};
2187
2188	static struct clk_branch gcc_av1e_ahb_clk = {
2189	.halt_reg = 0x4a004,
2190	.halt_check = BRANCH_HALT_VOTED,
2191	.hwcg_reg = 0x4a004,
2192	.hwcg_bit = 1,
2193	.clkr = {
2194	.enable_reg = 0x4a004,
2195	.enable_mask = BIT(0),
2196	.hw.init = &(const struct clk_init_data) {
2197	.name = "gcc_av1e_ahb_clk",
2198	.ops = &clk_branch2_ops,
2199	},
2200	},
2201	};
2202
2203	static struct clk_branch gcc_av1e_axi_clk = {
2204	.halt_reg = 0x4a008,
2205	.halt_check = BRANCH_HALT_SKIP,
2206	.hwcg_reg = 0x4a008,
2207	.hwcg_bit = 1,
2208	.clkr = {
2209	.enable_reg = 0x4a008,
2210	.enable_mask = BIT(0),
2211	.hw.init = &(const struct clk_init_data) {
2212	.name = "gcc_av1e_axi_clk",
2213	.ops = &clk_branch2_ops,
2214	},
2215	},
2216	};
2217
2218	static struct clk_branch gcc_av1e_xo_clk = {
2219	.halt_reg = 0x4a014,
2220	.halt_check = BRANCH_HALT,
2221	.clkr = {
2222	.enable_reg = 0x4a014,
2223	.enable_mask = BIT(0),
2224	.hw.init = &(const struct clk_init_data) {
2225	.name = "gcc_av1e_xo_clk",
2226	.ops = &clk_branch2_ops,
2227	},
2228	},
2229	};
2230
2231	static struct clk_branch gcc_boot_rom_ahb_clk = {
2232	.halt_reg = 0x38004,
2233	.halt_check = BRANCH_HALT_VOTED,
2234	.hwcg_reg = 0x38004,
2235	.hwcg_bit = 1,
2236	.clkr = {
2237	.enable_reg = 0x52000,
2238	.enable_mask = BIT(10),
2239	.hw.init = &(const struct clk_init_data) {
2240	.name = "gcc_boot_rom_ahb_clk",
2241	.ops = &clk_branch2_ops,
2242	},
2243	},
2244	};
2245
2246	static struct clk_branch gcc_camera_hf_axi_clk = {
2247	.halt_reg = 0x26010,
2248	.halt_check = BRANCH_HALT_SKIP,
2249	.hwcg_reg = 0x26010,
2250	.hwcg_bit = 1,
2251	.clkr = {
2252	.enable_reg = 0x26010,
2253	.enable_mask = BIT(0),
2254	.hw.init = &(const struct clk_init_data) {
2255	.name = "gcc_camera_hf_axi_clk",
2256	.ops = &clk_branch2_ops,
2257	},
2258	},
2259	};
2260
2261	static struct clk_branch gcc_camera_sf_axi_clk = {
2262	.halt_reg = 0x2601c,
2263	.halt_check = BRANCH_HALT_SKIP,
2264	.hwcg_reg = 0x2601c,
2265	.hwcg_bit = 1,
2266	.clkr = {
2267	.enable_reg = 0x2601c,
2268	.enable_mask = BIT(0),
2269	.hw.init = &(const struct clk_init_data) {
2270	.name = "gcc_camera_sf_axi_clk",
2271	.ops = &clk_branch2_ops,
2272	},
2273	},
2274	};
2275
2276	static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
2277	.halt_reg = 0x10028,
2278	.halt_check = BRANCH_HALT_VOTED,
2279	.hwcg_reg = 0x10028,
2280	.hwcg_bit = 1,
2281	.clkr = {
2282	.enable_reg = 0x52028,
2283	.enable_mask = BIT(20),
2284	.hw.init = &(const struct clk_init_data) {
2285	.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
2286	.ops = &clk_branch2_ops,
2287	},
2288	},
2289	};
2290
2291	static struct clk_branch gcc_cfg_noc_pcie_anoc_north_ahb_clk = {
2292	.halt_reg = 0x1002c,
2293	.halt_check = BRANCH_HALT_VOTED,
2294	.hwcg_reg = 0x1002c,
2295	.hwcg_bit = 1,
2296	.clkr = {
2297	.enable_reg = 0x52028,
2298	.enable_mask = BIT(22),
2299	.hw.init = &(const struct clk_init_data) {
2300	.name = "gcc_cfg_noc_pcie_anoc_north_ahb_clk",
2301	.ops = &clk_branch2_ops,
2302	},
2303	},
2304	};
2305
2306	static struct clk_branch gcc_cfg_noc_pcie_anoc_south_ahb_clk = {
2307	.halt_reg = 0x10030,
2308	.halt_check = BRANCH_HALT_VOTED,
2309	.hwcg_reg = 0x10030,
2310	.hwcg_bit = 1,
2311	.clkr = {
2312	.enable_reg = 0x52000,
2313	.enable_mask = BIT(20),
2314	.hw.init = &(const struct clk_init_data) {
2315	.name = "gcc_cfg_noc_pcie_anoc_south_ahb_clk",
2316	.ops = &clk_branch2_ops,
2317	},
2318	},
2319	};
2320
2321	static struct clk_branch gcc_cfg_noc_usb2_prim_axi_clk = {
2322	.halt_reg = 0x29288,
2323	.halt_check = BRANCH_HALT_VOTED,
2324	.hwcg_reg = 0x29288,
2325	.hwcg_bit = 1,
2326	.clkr = {
2327	.enable_reg = 0x29288,
2328	.enable_mask = BIT(0),
2329	.hw.init = &(const struct clk_init_data) {
2330	.name = "gcc_cfg_noc_usb2_prim_axi_clk",
2331	.parent_hws = (const struct clk_hw*[]) {
2332	&gcc_usb20_master_clk_src.clkr.hw,
2333	},
2334	.num_parents = 1,
2335	.flags = CLK_SET_RATE_PARENT,
2336	.ops = &clk_branch2_ops,
2337	},
2338	},
2339	};
2340
2341	static struct clk_branch gcc_cfg_noc_usb3_mp_axi_clk = {
2342	.halt_reg = 0x173cc,
2343	.halt_check = BRANCH_HALT_VOTED,
2344	.hwcg_reg = 0x173cc,
2345	.hwcg_bit = 1,
2346	.clkr = {
2347	.enable_reg = 0x173cc,
2348	.enable_mask = BIT(0),
2349	.hw.init = &(const struct clk_init_data) {
2350	.name = "gcc_cfg_noc_usb3_mp_axi_clk",
2351	.parent_hws = (const struct clk_hw*[]) {
2352	&gcc_usb30_mp_master_clk_src.clkr.hw,
2353	},
2354	.num_parents = 1,
2355	.flags = CLK_SET_RATE_PARENT,
2356	.ops = &clk_branch2_ops,
2357	},
2358	},
2359	};
2360
2361	static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
2362	.halt_reg = 0x3908c,
2363	.halt_check = BRANCH_HALT_VOTED,
2364	.hwcg_reg = 0x3908c,
2365	.hwcg_bit = 1,
2366	.clkr = {
2367	.enable_reg = 0x3908c,
2368	.enable_mask = BIT(0),
2369	.hw.init = &(const struct clk_init_data) {
2370	.name = "gcc_cfg_noc_usb3_prim_axi_clk",
2371	.parent_hws = (const struct clk_hw*[]) {
2372	&gcc_usb30_prim_master_clk_src.clkr.hw,
2373	},
2374	.num_parents = 1,
2375	.flags = CLK_SET_RATE_PARENT,
2376	.ops = &clk_branch2_ops,
2377	},
2378	},
2379	};
2380
2381	static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
2382	.halt_reg = 0xa108c,
2383	.halt_check = BRANCH_HALT_VOTED,
2384	.hwcg_reg = 0xa108c,
2385	.hwcg_bit = 1,
2386	.clkr = {
2387	.enable_reg = 0xa108c,
2388	.enable_mask = BIT(0),
2389	.hw.init = &(const struct clk_init_data) {
2390	.name = "gcc_cfg_noc_usb3_sec_axi_clk",
2391	.parent_hws = (const struct clk_hw*[]) {
2392	&gcc_usb30_sec_master_clk_src.clkr.hw,
2393	},
2394	.num_parents = 1,
2395	.flags = CLK_SET_RATE_PARENT,
2396	.ops = &clk_branch2_ops,
2397	},
2398	},
2399	};
2400
2401	static struct clk_branch gcc_cfg_noc_usb3_tert_axi_clk = {
2402	.halt_reg = 0xa208c,
2403	.halt_check = BRANCH_HALT_VOTED,
2404	.hwcg_reg = 0xa208c,
2405	.hwcg_bit = 1,
2406	.clkr = {
2407	.enable_reg = 0xa208c,
2408	.enable_mask = BIT(0),
2409	.hw.init = &(const struct clk_init_data) {
2410	.name = "gcc_cfg_noc_usb3_tert_axi_clk",
2411	.parent_hws = (const struct clk_hw*[]) {
2412	&gcc_usb30_tert_master_clk_src.clkr.hw,
2413	},
2414	.num_parents = 1,
2415	.flags = CLK_SET_RATE_PARENT,
2416	.ops = &clk_branch2_ops,
2417	},
2418	},
2419	};
2420
2421	static struct clk_branch gcc_cfg_noc_usb_anoc_ahb_clk = {
2422	.halt_reg = 0x2d024,
2423	.halt_check = BRANCH_HALT_VOTED,
2424	.hwcg_reg = 0x2d024,
2425	.hwcg_bit = 1,
2426	.clkr = {
2427	.enable_reg = 0x52028,
2428	.enable_mask = BIT(21),
2429	.hw.init = &(const struct clk_init_data) {
2430	.name = "gcc_cfg_noc_usb_anoc_ahb_clk",
2431	.ops = &clk_branch2_ops,
2432	},
2433	},
2434	};
2435
2436	static struct clk_branch gcc_cfg_noc_usb_anoc_north_ahb_clk = {
2437	.halt_reg = 0x2d028,
2438	.halt_check = BRANCH_HALT_VOTED,
2439	.hwcg_reg = 0x2d028,
2440	.hwcg_bit = 1,
2441	.clkr = {
2442	.enable_reg = 0x52028,
2443	.enable_mask = BIT(23),
2444	.hw.init = &(const struct clk_init_data) {
2445	.name = "gcc_cfg_noc_usb_anoc_north_ahb_clk",
2446	.ops = &clk_branch2_ops,
2447	},
2448	},
2449	};
2450
2451	static struct clk_branch gcc_cfg_noc_usb_anoc_south_ahb_clk = {
2452	.halt_reg = 0x2d02c,
2453	.halt_check = BRANCH_HALT_VOTED,
2454	.hwcg_reg = 0x2d02c,
2455	.hwcg_bit = 1,
2456	.clkr = {
2457	.enable_reg = 0x52018,
2458	.enable_mask = BIT(7),
2459	.hw.init = &(const struct clk_init_data) {
2460	.name = "gcc_cfg_noc_usb_anoc_south_ahb_clk",
2461	.ops = &clk_branch2_ops,
2462	},
2463	},
2464	};
2465
2466	static struct clk_branch gcc_cnoc_pcie1_tunnel_clk = {
2467	.halt_reg = 0x2c2b4,
2468	.halt_check = BRANCH_HALT_VOTED,
2469	.clkr = {
2470	.enable_reg = 0x52010,
2471	.enable_mask = BIT(30),
2472	.hw.init = &(const struct clk_init_data) {
2473	.name = "gcc_cnoc_pcie1_tunnel_clk",
2474	.ops = &clk_branch2_ops,
2475	},
2476	},
2477	};
2478
2479	static struct clk_branch gcc_cnoc_pcie2_tunnel_clk = {
2480	.halt_reg = 0x132b4,
2481	.halt_check = BRANCH_HALT_VOTED,
2482	.clkr = {
2483	.enable_reg = 0x52010,
2484	.enable_mask = BIT(31),
2485	.hw.init = &(const struct clk_init_data) {
2486	.name = "gcc_cnoc_pcie2_tunnel_clk",
2487	.ops = &clk_branch2_ops,
2488	},
2489	},
2490	};
2491
2492	static struct clk_branch gcc_cnoc_pcie_north_sf_axi_clk = {
2493	.halt_reg = 0x10014,
2494	.halt_check = BRANCH_HALT_VOTED,
2495	.hwcg_reg = 0x10014,
2496	.hwcg_bit = 1,
2497	.clkr = {
2498	.enable_reg = 0x52008,
2499	.enable_mask = BIT(6),
2500	.hw.init = &(const struct clk_init_data) {
2501	.name = "gcc_cnoc_pcie_north_sf_axi_clk",
2502	.ops = &clk_branch2_ops,
2503	},
2504	},
2505	};
2506
2507	static struct clk_branch gcc_cnoc_pcie_south_sf_axi_clk = {
2508	.halt_reg = 0x10018,
2509	.halt_check = BRANCH_HALT_VOTED,
2510	.hwcg_reg = 0x10018,
2511	.hwcg_bit = 1,
2512	.clkr = {
2513	.enable_reg = 0x52028,
2514	.enable_mask = BIT(12),
2515	.hw.init = &(const struct clk_init_data) {
2516	.name = "gcc_cnoc_pcie_south_sf_axi_clk",
2517	.ops = &clk_branch2_ops,
2518	},
2519	},
2520	};
2521
2522	static struct clk_branch gcc_cnoc_pcie_tunnel_clk = {
2523	.halt_reg = 0xa02b4,
2524	.halt_check = BRANCH_HALT_VOTED,
2525	.hwcg_reg = 0xa02b4,
2526	.hwcg_bit = 1,
2527	.clkr = {
2528	.enable_reg = 0x52010,
2529	.enable_mask = BIT(29),
2530	.hw.init = &(const struct clk_init_data) {
2531	.name = "gcc_cnoc_pcie_tunnel_clk",
2532	.ops = &clk_branch2_ops,
2533	},
2534	},
2535	};
2536
2537	static struct clk_branch gcc_ddrss_gpu_axi_clk = {
2538	.halt_reg = 0x7115c,
2539	.halt_check = BRANCH_HALT_SKIP,
2540	.hwcg_reg = 0x7115c,
2541	.hwcg_bit = 1,
2542	.clkr = {
2543	.enable_reg = 0x7115c,
2544	.enable_mask = BIT(0),
2545	.hw.init = &(const struct clk_init_data) {
2546	.name = "gcc_ddrss_gpu_axi_clk",
2547	.ops = &clk_branch2_ops,
2548	},
2549	},
2550	};
2551
2552	static struct clk_branch gcc_disp_hf_axi_clk = {
2553	.halt_reg = 0x2700c,
2554	.halt_check = BRANCH_HALT_SKIP,
2555	.hwcg_reg = 0x2700c,
2556	.hwcg_bit = 1,
2557	.clkr = {
2558	.enable_reg = 0x2700c,
2559	.enable_mask = BIT(0),
2560	.hw.init = &(const struct clk_init_data) {
2561	.name = "gcc_disp_hf_axi_clk",
2562	.ops = &clk_branch2_ops,
2563	},
2564	},
2565	};
2566
2567	static struct clk_branch gcc_disp_xo_clk = {
2568	.halt_reg = 0x27018,
2569	.halt_check = BRANCH_HALT,
2570	.clkr = {
2571	.enable_reg = 0x27018,
2572	.enable_mask = BIT(0),
2573	.hw.init = &(const struct clk_init_data) {
2574	.name = "gcc_disp_xo_clk",
2575	.ops = &clk_branch2_ops,
2576	},
2577	},
2578	};
2579
2580	static struct clk_branch gcc_gp1_clk = {
2581	.halt_reg = 0x64000,
2582	.halt_check = BRANCH_HALT,
2583	.clkr = {
2584	.enable_reg = 0x64000,
2585	.enable_mask = BIT(0),
2586	.hw.init = &(const struct clk_init_data) {
2587	.name = "gcc_gp1_clk",
2588	.parent_hws = (const struct clk_hw*[]) {
2589	&gcc_gp1_clk_src.clkr.hw,
2590	},
2591	.num_parents = 1,
2592	.flags = CLK_SET_RATE_PARENT,
2593	.ops = &clk_branch2_ops,
2594	},
2595	},
2596	};
2597
2598	static struct clk_branch gcc_gp2_clk = {
2599	.halt_reg = 0x65000,
2600	.halt_check = BRANCH_HALT,
2601	.clkr = {
2602	.enable_reg = 0x65000,
2603	.enable_mask = BIT(0),
2604	.hw.init = &(const struct clk_init_data) {
2605	.name = "gcc_gp2_clk",
2606	.parent_hws = (const struct clk_hw*[]) {
2607	&gcc_gp2_clk_src.clkr.hw,
2608	},
2609	.num_parents = 1,
2610	.flags = CLK_SET_RATE_PARENT,
2611	.ops = &clk_branch2_ops,
2612	},
2613	},
2614	};
2615
2616	static struct clk_branch gcc_gp3_clk = {
2617	.halt_reg = 0x66000,
2618	.halt_check = BRANCH_HALT,
2619	.clkr = {
2620	.enable_reg = 0x66000,
2621	.enable_mask = BIT(0),
2622	.hw.init = &(const struct clk_init_data) {
2623	.name = "gcc_gp3_clk",
2624	.parent_hws = (const struct clk_hw*[]) {
2625	&gcc_gp3_clk_src.clkr.hw,
2626	},
2627	.num_parents = 1,
2628	.flags = CLK_SET_RATE_PARENT,
2629	.ops = &clk_branch2_ops,
2630	},
2631	},
2632	};
2633
2634	static struct clk_branch gcc_gpu_cfg_ahb_clk = {
2635	.halt_reg = 0x71004,
2636	.halt_check = BRANCH_HALT_VOTED,
2637	.hwcg_reg = 0x71004,
2638	.hwcg_bit = 1,
2639	.clkr = {
2640	.enable_reg = 0x71004,
2641	.enable_mask = BIT(0),
2642	.hw.init = &(const struct clk_init_data) {
2643	.name = "gcc_gpu_cfg_ahb_clk",
2644	.ops = &clk_branch2_ops,
2645	},
2646	},
2647	};
2648
2649	static struct clk_branch gcc_gpu_gpll0_cph_clk_src = {
2650	.halt_check = BRANCH_HALT_DELAY,
2651	.clkr = {
2652	.enable_reg = 0x52000,
2653	.enable_mask = BIT(15),
2654	.hw.init = &(const struct clk_init_data) {
2655	.name = "gcc_gpu_gpll0_cph_clk_src",
2656	.parent_hws = (const struct clk_hw*[]) {
2657	&gcc_gpll0.clkr.hw,
2658	},
2659	.num_parents = 1,
2660	.flags = CLK_SET_RATE_PARENT,
2661	.ops = &clk_branch2_ops,
2662	},
2663	},
2664	};
2665
2666	static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = {
2667	.halt_check = BRANCH_HALT_DELAY,
2668	.clkr = {
2669	.enable_reg = 0x52000,
2670	.enable_mask = BIT(16),
2671	.hw.init = &(const struct clk_init_data) {
2672	.name = "gcc_gpu_gpll0_div_cph_clk_src",
2673	.parent_hws = (const struct clk_hw*[]) {
2674	&gcc_gpll0_out_even.clkr.hw,
2675	},
2676	.num_parents = 1,
2677	.flags = CLK_SET_RATE_PARENT,
2678	.ops = &clk_branch2_ops,
2679	},
2680	},
2681	};
2682
2683	static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
2684	.halt_reg = 0x71010,
2685	.halt_check = BRANCH_HALT_VOTED,
2686	.hwcg_reg = 0x71010,
2687	.hwcg_bit = 1,
2688	.clkr = {
2689	.enable_reg = 0x71010,
2690	.enable_mask = BIT(0),
2691	.hw.init = &(const struct clk_init_data) {
2692	.name = "gcc_gpu_memnoc_gfx_clk",
2693	.ops = &clk_branch2_ops,
2694	},
2695	},
2696	};
2697
2698	static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
2699	.halt_reg = 0x71018,
2700	.halt_check = BRANCH_HALT,
2701	.clkr = {
2702	.enable_reg = 0x71018,
2703	.enable_mask = BIT(0),
2704	.hw.init = &(const struct clk_init_data) {
2705	.name = "gcc_gpu_snoc_dvm_gfx_clk",
2706	.ops = &clk_branch2_ops,
2707	},
2708	},
2709	};
2710
2711	static struct clk_branch gcc_pcie0_phy_rchng_clk = {
2712	.halt_reg = 0xa0050,
2713	.halt_check = BRANCH_HALT_VOTED,
2714	.clkr = {
2715	.enable_reg = 0x52010,
2716	.enable_mask = BIT(26),
2717	.hw.init = &(const struct clk_init_data) {
2718	.name = "gcc_pcie0_phy_rchng_clk",
2719	.parent_hws = (const struct clk_hw*[]) {
2720	&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
2721	},
2722	.num_parents = 1,
2723	.flags = CLK_SET_RATE_PARENT,
2724	.ops = &clk_branch2_ops,
2725	},
2726	},
2727	};
2728
2729	static struct clk_branch gcc_pcie1_phy_rchng_clk = {
2730	.halt_reg = 0x2c050,
2731	.halt_check = BRANCH_HALT_VOTED,
2732	.clkr = {
2733	.enable_reg = 0x52020,
2734	.enable_mask = BIT(31),
2735	.hw.init = &(const struct clk_init_data) {
2736	.name = "gcc_pcie1_phy_rchng_clk",
2737	.parent_hws = (const struct clk_hw*[]) {
2738	&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
2739	},
2740	.num_parents = 1,
2741	.flags = CLK_SET_RATE_PARENT,
2742	.ops = &clk_branch2_ops,
2743	},
2744	},
2745	};
2746
2747	static struct clk_branch gcc_pcie2_phy_rchng_clk = {
2748	.halt_reg = 0x13050,
2749	.halt_check = BRANCH_HALT_VOTED,
2750	.clkr = {
2751	.enable_reg = 0x52020,
2752	.enable_mask = BIT(24),
2753	.hw.init = &(const struct clk_init_data) {
2754	.name = "gcc_pcie2_phy_rchng_clk",
2755	.parent_hws = (const struct clk_hw*[]) {
2756	&gcc_pcie_2_phy_rchng_clk_src.clkr.hw,
2757	},
2758	.num_parents = 1,
2759	.flags = CLK_SET_RATE_PARENT,
2760	.ops = &clk_branch2_ops,
2761	},
2762	},
2763	};
2764
2765	static struct clk_branch gcc_pcie_0_aux_clk = {
2766	.halt_reg = 0xa0038,
2767	.halt_check = BRANCH_HALT_VOTED,
2768	.clkr = {
2769	.enable_reg = 0x52010,
2770	.enable_mask = BIT(24),
2771	.hw.init = &(const struct clk_init_data) {
2772	.name = "gcc_pcie_0_aux_clk",
2773	.parent_hws = (const struct clk_hw*[]) {
2774	&gcc_pcie_0_aux_clk_src.clkr.hw,
2775	},
2776	.num_parents = 1,
2777	.flags = CLK_SET_RATE_PARENT,
2778	.ops = &clk_branch2_ops,
2779	},
2780	},
2781	};
2782
2783	static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2784	.halt_reg = 0xa0034,
2785	.halt_check = BRANCH_HALT_VOTED,
2786	.hwcg_reg = 0xa0034,
2787	.hwcg_bit = 1,
2788	.clkr = {
2789	.enable_reg = 0x52010,
2790	.enable_mask = BIT(23),
2791	.hw.init = &(const struct clk_init_data) {
2792	.name = "gcc_pcie_0_cfg_ahb_clk",
2793	.ops = &clk_branch2_ops,
2794	},
2795	},
2796	};
2797
2798	static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2799	.halt_reg = 0xa0028,
2800	.halt_check = BRANCH_HALT_SKIP,
2801	.hwcg_reg = 0xa0028,
2802	.hwcg_bit = 1,
2803	.clkr = {
2804	.enable_reg = 0x52010,
2805	.enable_mask = BIT(22),
2806	.hw.init = &(const struct clk_init_data) {
2807	.name = "gcc_pcie_0_mstr_axi_clk",
2808	.ops = &clk_branch2_ops,
2809	},
2810	},
2811	};
2812
2813	static struct clk_branch gcc_pcie_0_pipe_clk = {
2814	.halt_reg = 0xa0044,
2815	.halt_check = BRANCH_HALT_VOTED,
2816	.clkr = {
2817	.enable_reg = 0x52010,
2818	.enable_mask = BIT(25),
2819	.hw.init = &(const struct clk_init_data) {
2820	.name = "gcc_pcie_0_pipe_clk",
2821	.ops = &clk_branch2_ops,
2822	},
2823	},
2824	};
2825
2826	static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2827	.halt_reg = 0xa001c,
2828	.halt_check = BRANCH_HALT_VOTED,
2829	.hwcg_reg = 0xa001c,
2830	.hwcg_bit = 1,
2831	.clkr = {
2832	.enable_reg = 0x52010,
2833	.enable_mask = BIT(21),
2834	.hw.init = &(const struct clk_init_data) {
2835	.name = "gcc_pcie_0_slv_axi_clk",
2836	.ops = &clk_branch2_ops,
2837	},
2838	},
2839	};
2840
2841	static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
2842	.halt_reg = 0xa0018,
2843	.halt_check = BRANCH_HALT_VOTED,
2844	.clkr = {
2845	.enable_reg = 0x52010,
2846	.enable_mask = BIT(20),
2847	.hw.init = &(const struct clk_init_data) {
2848	.name = "gcc_pcie_0_slv_q2a_axi_clk",
2849	.ops = &clk_branch2_ops,
2850	},
2851	},
2852	};
2853
2854	static struct clk_branch gcc_pcie_1_aux_clk = {
2855	.halt_reg = 0x2c038,
2856	.halt_check = BRANCH_HALT_VOTED,
2857	.clkr = {
2858	.enable_reg = 0x52020,
2859	.enable_mask = BIT(29),
2860	.hw.init = &(const struct clk_init_data) {
2861	.name = "gcc_pcie_1_aux_clk",
2862	.parent_hws = (const struct clk_hw*[]) {
2863	&gcc_pcie_1_aux_clk_src.clkr.hw,
2864	},
2865	.num_parents = 1,
2866	.flags = CLK_SET_RATE_PARENT,
2867	.ops = &clk_branch2_ops,
2868	},
2869	},
2870	};
2871
2872	static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
2873	.halt_reg = 0x2c034,
2874	.halt_check = BRANCH_HALT_VOTED,
2875	.hwcg_reg = 0x2c034,
2876	.hwcg_bit = 1,
2877	.clkr = {
2878	.enable_reg = 0x52020,
2879	.enable_mask = BIT(28),
2880	.hw.init = &(const struct clk_init_data) {
2881	.name = "gcc_pcie_1_cfg_ahb_clk",
2882	.ops = &clk_branch2_ops,
2883	},
2884	},
2885	};
2886
2887	static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
2888	.halt_reg = 0x2c028,
2889	.halt_check = BRANCH_HALT_SKIP,
2890	.hwcg_reg = 0x2c028,
2891	.hwcg_bit = 1,
2892	.clkr = {
2893	.enable_reg = 0x52020,
2894	.enable_mask = BIT(27),
2895	.hw.init = &(const struct clk_init_data) {
2896	.name = "gcc_pcie_1_mstr_axi_clk",
2897	.ops = &clk_branch2_ops,
2898	},
2899	},
2900	};
2901
2902	static struct clk_branch gcc_pcie_1_pipe_clk = {
2903	.halt_reg = 0x2c044,
2904	.halt_check = BRANCH_HALT_VOTED,
2905	.clkr = {
2906	.enable_reg = 0x52020,
2907	.enable_mask = BIT(30),
2908	.hw.init = &(const struct clk_init_data) {
2909	.name = "gcc_pcie_1_pipe_clk",
2910	.ops = &clk_branch2_ops,
2911	},
2912	},
2913	};
2914
2915	static struct clk_branch gcc_pcie_1_slv_axi_clk = {
2916	.halt_reg = 0x2c01c,
2917	.halt_check = BRANCH_HALT_VOTED,
2918	.hwcg_reg = 0x2c01c,
2919	.hwcg_bit = 1,
2920	.clkr = {
2921	.enable_reg = 0x52020,
2922	.enable_mask = BIT(26),
2923	.hw.init = &(const struct clk_init_data) {
2924	.name = "gcc_pcie_1_slv_axi_clk",
2925	.ops = &clk_branch2_ops,
2926	},
2927	},
2928	};
2929
2930	static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
2931	.halt_reg = 0x2c018,
2932	.halt_check = BRANCH_HALT_VOTED,
2933	.clkr = {
2934	.enable_reg = 0x52020,
2935	.enable_mask = BIT(25),
2936	.hw.init = &(const struct clk_init_data) {
2937	.name = "gcc_pcie_1_slv_q2a_axi_clk",
2938	.ops = &clk_branch2_ops,
2939	},
2940	},
2941	};
2942
2943	static struct clk_branch gcc_pcie_2_aux_clk = {
2944	.halt_reg = 0x13038,
2945	.halt_check = BRANCH_HALT_VOTED,
2946	.clkr = {
2947	.enable_reg = 0x52020,
2948	.enable_mask = BIT(22),
2949	.hw.init = &(const struct clk_init_data) {
2950	.name = "gcc_pcie_2_aux_clk",
2951	.parent_hws = (const struct clk_hw*[]) {
2952	&gcc_pcie_2_aux_clk_src.clkr.hw,
2953	},
2954	.num_parents = 1,
2955	.flags = CLK_SET_RATE_PARENT,
2956	.ops = &clk_branch2_ops,
2957	},
2958	},
2959	};
2960
2961	static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
2962	.halt_reg = 0x13034,
2963	.halt_check = BRANCH_HALT_VOTED,
2964	.hwcg_reg = 0x13034,
2965	.hwcg_bit = 1,
2966	.clkr = {
2967	.enable_reg = 0x52020,
2968	.enable_mask = BIT(21),
2969	.hw.init = &(const struct clk_init_data) {
2970	.name = "gcc_pcie_2_cfg_ahb_clk",
2971	.ops = &clk_branch2_ops,
2972	},
2973	},
2974	};
2975
2976	static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
2977	.halt_reg = 0x13028,
2978	.halt_check = BRANCH_HALT_SKIP,
2979	.hwcg_reg = 0x13028,
2980	.hwcg_bit = 1,
2981	.clkr = {
2982	.enable_reg = 0x52020,
2983	.enable_mask = BIT(20),
2984	.hw.init = &(const struct clk_init_data) {
2985	.name = "gcc_pcie_2_mstr_axi_clk",
2986	.ops = &clk_branch2_ops,
2987	},
2988	},
2989	};
2990
2991	static struct clk_branch gcc_pcie_2_pipe_clk = {
2992	.halt_reg = 0x13044,
2993	.halt_check = BRANCH_HALT_VOTED,
2994	.clkr = {
2995	.enable_reg = 0x52020,
2996	.enable_mask = BIT(23),
2997	.hw.init = &(const struct clk_init_data) {
2998	.name = "gcc_pcie_2_pipe_clk",
2999	.ops = &clk_branch2_ops,
3000	},
3001	},
3002	};
3003
3004	static struct clk_branch gcc_pcie_2_slv_axi_clk = {
3005	.halt_reg = 0x1301c,
3006	.halt_check = BRANCH_HALT_VOTED,
3007	.hwcg_reg = 0x1301c,
3008	.hwcg_bit = 1,
3009	.clkr = {
3010	.enable_reg = 0x52020,
3011	.enable_mask = BIT(19),
3012	.hw.init = &(const struct clk_init_data) {
3013	.name = "gcc_pcie_2_slv_axi_clk",
3014	.ops = &clk_branch2_ops,
3015	},
3016	},
3017	};
3018
3019	static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = {
3020	.halt_reg = 0x13018,
3021	.halt_check = BRANCH_HALT_VOTED,
3022	.clkr = {
3023	.enable_reg = 0x52020,
3024	.enable_mask = BIT(18),
3025	.hw.init = &(const struct clk_init_data) {
3026	.name = "gcc_pcie_2_slv_q2a_axi_clk",
3027	.ops = &clk_branch2_ops,
3028	},
3029	},
3030	};
3031
3032	static struct clk_branch gcc_pcie_3_aux_clk = {
3033	.halt_reg = 0x58038,
3034	.halt_check = BRANCH_HALT_VOTED,
3035	.clkr = {
3036	.enable_reg = 0x52020,
3037	.enable_mask = BIT(1),
3038	.hw.init = &(const struct clk_init_data) {
3039	.name = "gcc_pcie_3_aux_clk",
3040	.parent_hws = (const struct clk_hw*[]) {
3041	&gcc_pcie_3_aux_clk_src.clkr.hw,
3042	},
3043	.num_parents = 1,
3044	.flags = CLK_SET_RATE_PARENT,
3045	.ops = &clk_branch2_ops,
3046	},
3047	},
3048	};
3049
3050	static struct clk_branch gcc_pcie_3_cfg_ahb_clk = {
3051	.halt_reg = 0x58034,
3052	.halt_check = BRANCH_HALT_VOTED,
3053	.hwcg_reg = 0x58034,
3054	.hwcg_bit = 1,
3055	.clkr = {
3056	.enable_reg = 0x52020,
3057	.enable_mask = BIT(0),
3058	.hw.init = &(const struct clk_init_data) {
3059	.name = "gcc_pcie_3_cfg_ahb_clk",
3060	.ops = &clk_branch2_ops,
3061	},
3062	},
3063	};
3064
3065	static struct clk_branch gcc_pcie_3_mstr_axi_clk = {
3066	.halt_reg = 0x58028,
3067	.halt_check = BRANCH_HALT_SKIP,
3068	.hwcg_reg = 0x58028,
3069	.hwcg_bit = 1,
3070	.clkr = {
3071	.enable_reg = 0x52018,
3072	.enable_mask = BIT(31),
3073	.hw.init = &(const struct clk_init_data) {
3074	.name = "gcc_pcie_3_mstr_axi_clk",
3075	.ops = &clk_branch2_ops,
3076	},
3077	},
3078	};
3079
3080	static struct clk_branch gcc_pcie_3_phy_aux_clk = {
3081	.halt_reg = 0x58044,
3082	.halt_check = BRANCH_HALT_VOTED,
3083	.clkr = {
3084	.enable_reg = 0x52020,
3085	.enable_mask = BIT(2),
3086	.hw.init = &(const struct clk_init_data) {
3087	.name = "gcc_pcie_3_phy_aux_clk",
3088	.ops = &clk_branch2_ops,
3089	},
3090	},
3091	};
3092
3093	static struct clk_branch gcc_pcie_3_phy_rchng_clk = {
3094	.halt_reg = 0x5805c,
3095	.halt_check = BRANCH_HALT_VOTED,
3096	.clkr = {
3097	.enable_reg = 0x52020,
3098	.enable_mask = BIT(4),
3099	.hw.init = &(const struct clk_init_data) {
3100	.name = "gcc_pcie_3_phy_rchng_clk",
3101	.parent_hws = (const struct clk_hw*[]) {
3102	&gcc_pcie_3_phy_rchng_clk_src.clkr.hw,
3103	},
3104	.num_parents = 1,
3105	.flags = CLK_SET_RATE_PARENT,
3106	.ops = &clk_branch2_ops,
3107	},
3108	},
3109	};
3110
3111	static struct clk_branch gcc_pcie_3_pipe_clk = {
3112	.halt_reg = 0x58050,
3113	.halt_check = BRANCH_HALT_VOTED,
3114	.clkr = {
3115	.enable_reg = 0x52020,
3116	.enable_mask = BIT(3),
3117	.hw.init = &(const struct clk_init_data) {
3118	.name = "gcc_pcie_3_pipe_clk",
3119	.ops = &clk_branch2_ops,
3120	},
3121	},
3122	};
3123
3124	static struct clk_branch gcc_pcie_3_pipediv2_clk = {
3125	.halt_reg = 0x58060,
3126	.halt_check = BRANCH_HALT_VOTED,
3127	.clkr = {
3128	.enable_reg = 0x52020,
3129	.enable_mask = BIT(5),
3130	.hw.init = &(const struct clk_init_data) {
3131	.name = "gcc_pcie_3_pipediv2_clk",
3132	.parent_hws = (const struct clk_hw*[]) {
3133	&gcc_pcie_3_pipe_div_clk_src.clkr.hw,
3134	},
3135	.num_parents = 1,
3136	.flags = CLK_SET_RATE_PARENT,
3137	.ops = &clk_branch2_ops,
3138	},
3139	},
3140	};
3141
3142	static struct clk_branch gcc_pcie_3_slv_axi_clk = {
3143	.halt_reg = 0x5801c,
3144	.halt_check = BRANCH_HALT_VOTED,
3145	.hwcg_reg = 0x5801c,
3146	.hwcg_bit = 1,
3147	.clkr = {
3148	.enable_reg = 0x52018,
3149	.enable_mask = BIT(30),
3150	.hw.init = &(const struct clk_init_data) {
3151	.name = "gcc_pcie_3_slv_axi_clk",
3152	.ops = &clk_branch2_ops,
3153	},
3154	},
3155	};
3156
3157	static struct clk_branch gcc_pcie_3_slv_q2a_axi_clk = {
3158	.halt_reg = 0x58018,
3159	.halt_check = BRANCH_HALT_VOTED,
3160	.clkr = {
3161	.enable_reg = 0x52018,
3162	.enable_mask = BIT(29),
3163	.hw.init = &(const struct clk_init_data) {
3164	.name = "gcc_pcie_3_slv_q2a_axi_clk",
3165	.ops = &clk_branch2_ops,
3166	},
3167	},
3168	};
3169
3170	static struct clk_branch gcc_pcie_4_aux_clk = {
3171	.halt_reg = 0x6b038,
3172	.halt_check = BRANCH_HALT_VOTED,
3173	.clkr = {
3174	.enable_reg = 0x52008,
3175	.enable_mask = BIT(3),
3176	.hw.init = &(const struct clk_init_data) {
3177	.name = "gcc_pcie_4_aux_clk",
3178	.parent_hws = (const struct clk_hw*[]) {
3179	&gcc_pcie_4_aux_clk_src.clkr.hw,
3180	},
3181	.num_parents = 1,
3182	.flags = CLK_SET_RATE_PARENT,
3183	.ops = &clk_branch2_ops,
3184	},
3185	},
3186	};
3187
3188	static struct clk_branch gcc_pcie_4_cfg_ahb_clk = {
3189	.halt_reg = 0x6b034,
3190	.halt_check = BRANCH_HALT_VOTED,
3191	.hwcg_reg = 0x6b034,
3192	.hwcg_bit = 1,
3193	.clkr = {
3194	.enable_reg = 0x52008,
3195	.enable_mask = BIT(2),
3196	.hw.init = &(const struct clk_init_data) {
3197	.name = "gcc_pcie_4_cfg_ahb_clk",
3198	.ops = &clk_branch2_ops,
3199	},
3200	},
3201	};
3202
3203	static struct clk_branch gcc_pcie_4_mstr_axi_clk = {
3204	.halt_reg = 0x6b028,
3205	.halt_check = BRANCH_HALT_SKIP,
3206	.hwcg_reg = 0x6b028,
3207	.hwcg_bit = 1,
3208	.clkr = {
3209	.enable_reg = 0x52008,
3210	.enable_mask = BIT(1),
3211	.hw.init = &(const struct clk_init_data) {
3212	.name = "gcc_pcie_4_mstr_axi_clk",
3213	.ops = &clk_branch2_ops,
3214	},
3215	},
3216	};
3217
3218	static struct clk_branch gcc_pcie_4_phy_rchng_clk = {
3219	.halt_reg = 0x6b050,
3220	.halt_check = BRANCH_HALT_VOTED,
3221	.clkr = {
3222	.enable_reg = 0x52000,
3223	.enable_mask = BIT(22),
3224	.hw.init = &(const struct clk_init_data) {
3225	.name = "gcc_pcie_4_phy_rchng_clk",
3226	.parent_hws = (const struct clk_hw*[]) {
3227	&gcc_pcie_4_phy_rchng_clk_src.clkr.hw,
3228	},
3229	.num_parents = 1,
3230	.flags = CLK_SET_RATE_PARENT,
3231	.ops = &clk_branch2_ops,
3232	},
3233	},
3234	};
3235
3236	static struct clk_branch gcc_pcie_4_pipe_clk = {
3237	.halt_reg = 0x6b044,
3238	.halt_check = BRANCH_HALT_VOTED,
3239	.clkr = {
3240	.enable_reg = 0x52008,
3241	.enable_mask = BIT(4),
3242	.hw.init = &(const struct clk_init_data) {
3243	.name = "gcc_pcie_4_pipe_clk",
3244	.ops = &clk_branch2_ops,
3245	},
3246	},
3247	};
3248
3249	static struct clk_branch gcc_pcie_4_pipediv2_clk = {
3250	.halt_reg = 0x6b054,
3251	.halt_check = BRANCH_HALT_VOTED,
3252	.clkr = {
3253	.enable_reg = 0x52010,
3254	.enable_mask = BIT(27),
3255	.hw.init = &(const struct clk_init_data) {
3256	.name = "gcc_pcie_4_pipediv2_clk",
3257	.parent_hws = (const struct clk_hw*[]) {
3258	&gcc_pcie_4_pipe_div_clk_src.clkr.hw,
3259	},
3260	.num_parents = 1,
3261	.flags = CLK_SET_RATE_PARENT,
3262	.ops = &clk_branch2_ops,
3263	},
3264	},
3265	};
3266
3267	static struct clk_branch gcc_pcie_4_slv_axi_clk = {
3268	.halt_reg = 0x6b01c,
3269	.halt_check = BRANCH_HALT_VOTED,
3270	.hwcg_reg = 0x6b01c,
3271	.hwcg_bit = 1,
3272	.clkr = {
3273	.enable_reg = 0x52008,
3274	.enable_mask = BIT(0),
3275	.hw.init = &(const struct clk_init_data) {
3276	.name = "gcc_pcie_4_slv_axi_clk",
3277	.ops = &clk_branch2_ops,
3278	},
3279	},
3280	};
3281
3282	static struct clk_branch gcc_pcie_4_slv_q2a_axi_clk = {
3283	.halt_reg = 0x6b018,
3284	.halt_check = BRANCH_HALT_VOTED,
3285	.clkr = {
3286	.enable_reg = 0x52008,
3287	.enable_mask = BIT(5),
3288	.hw.init = &(const struct clk_init_data) {
3289	.name = "gcc_pcie_4_slv_q2a_axi_clk",
3290	.ops = &clk_branch2_ops,
3291	},
3292	},
3293	};
3294
3295	static struct clk_branch gcc_pcie_5_aux_clk = {
3296	.halt_reg = 0x2f038,
3297	.halt_check = BRANCH_HALT_VOTED,
3298	.clkr = {
3299	.enable_reg = 0x52018,
3300	.enable_mask = BIT(16),
3301	.hw.init = &(const struct clk_init_data) {
3302	.name = "gcc_pcie_5_aux_clk",
3303	.parent_hws = (const struct clk_hw*[]) {
3304	&gcc_pcie_5_aux_clk_src.clkr.hw,
3305	},
3306	.num_parents = 1,
3307	.flags = CLK_SET_RATE_PARENT,
3308	.ops = &clk_branch2_ops,
3309	},
3310	},
3311	};
3312
3313	static struct clk_branch gcc_pcie_5_cfg_ahb_clk = {
3314	.halt_reg = 0x2f034,
3315	.halt_check = BRANCH_HALT_VOTED,
3316	.hwcg_reg = 0x2f034,
3317	.hwcg_bit = 1,
3318	.clkr = {
3319	.enable_reg = 0x52018,
3320	.enable_mask = BIT(15),
3321	.hw.init = &(const struct clk_init_data) {
3322	.name = "gcc_pcie_5_cfg_ahb_clk",
3323	.ops = &clk_branch2_ops,
3324	},
3325	},
3326	};
3327
3328	static struct clk_branch gcc_pcie_5_mstr_axi_clk = {
3329	.halt_reg = 0x2f028,
3330	.halt_check = BRANCH_HALT_SKIP,
3331	.hwcg_reg = 0x2f028,
3332	.hwcg_bit = 1,
3333	.clkr = {
3334	.enable_reg = 0x52018,
3335	.enable_mask = BIT(14),
3336	.hw.init = &(const struct clk_init_data) {
3337	.name = "gcc_pcie_5_mstr_axi_clk",
3338	.ops = &clk_branch2_ops,
3339	},
3340	},
3341	};
3342
3343	static struct clk_branch gcc_pcie_5_phy_rchng_clk = {
3344	.halt_reg = 0x2f050,
3345	.halt_check = BRANCH_HALT_VOTED,
3346	.clkr = {
3347	.enable_reg = 0x52018,
3348	.enable_mask = BIT(18),
3349	.hw.init = &(const struct clk_init_data) {
3350	.name = "gcc_pcie_5_phy_rchng_clk",
3351	.parent_hws = (const struct clk_hw*[]) {
3352	&gcc_pcie_5_phy_rchng_clk_src.clkr.hw,
3353	},
3354	.num_parents = 1,
3355	.flags = CLK_SET_RATE_PARENT,
3356	.ops = &clk_branch2_ops,
3357	},
3358	},
3359	};
3360
3361	static struct clk_branch gcc_pcie_5_pipe_clk = {
3362	.halt_reg = 0x2f044,
3363	.halt_check = BRANCH_HALT_VOTED,
3364	.clkr = {
3365	.enable_reg = 0x52018,
3366	.enable_mask = BIT(17),
3367	.hw.init = &(const struct clk_init_data) {
3368	.name = "gcc_pcie_5_pipe_clk",
3369	.ops = &clk_branch2_ops,
3370	},
3371	},
3372	};
3373
3374	static struct clk_branch gcc_pcie_5_pipediv2_clk = {
3375	.halt_reg = 0x2f054,
3376	.halt_check = BRANCH_HALT_VOTED,
3377	.clkr = {
3378	.enable_reg = 0x52018,
3379	.enable_mask = BIT(19),
3380	.hw.init = &(const struct clk_init_data) {
3381	.name = "gcc_pcie_5_pipediv2_clk",
3382	.parent_hws = (const struct clk_hw*[]) {
3383	&gcc_pcie_5_pipe_div_clk_src.clkr.hw,
3384	},
3385	.num_parents = 1,
3386	.flags = CLK_SET_RATE_PARENT,
3387	.ops = &clk_branch2_ops,
3388	},
3389	},
3390	};
3391
3392	static struct clk_branch gcc_pcie_5_slv_axi_clk = {
3393	.halt_reg = 0x2f01c,
3394	.halt_check = BRANCH_HALT_VOTED,
3395	.hwcg_reg = 0x2f01c,
3396	.hwcg_bit = 1,
3397	.clkr = {
3398	.enable_reg = 0x52018,
3399	.enable_mask = BIT(13),
3400	.hw.init = &(const struct clk_init_data) {
3401	.name = "gcc_pcie_5_slv_axi_clk",
3402	.ops = &clk_branch2_ops,
3403	},
3404	},
3405	};
3406
3407	static struct clk_branch gcc_pcie_5_slv_q2a_axi_clk = {
3408	.halt_reg = 0x2f018,
3409	.halt_check = BRANCH_HALT_VOTED,
3410	.clkr = {
3411	.enable_reg = 0x52018,
3412	.enable_mask = BIT(12),
3413	.hw.init = &(const struct clk_init_data) {
3414	.name = "gcc_pcie_5_slv_q2a_axi_clk",
3415	.ops = &clk_branch2_ops,
3416	},
3417	},
3418	};
3419
3420	static struct clk_branch gcc_pcie_6a_aux_clk = {
3421	.halt_reg = 0x31038,
3422	.halt_check = BRANCH_HALT_VOTED,
3423	.clkr = {
3424	.enable_reg = 0x52018,
3425	.enable_mask = BIT(24),
3426	.hw.init = &(const struct clk_init_data) {
3427	.name = "gcc_pcie_6a_aux_clk",
3428	.parent_hws = (const struct clk_hw*[]) {
3429	&gcc_pcie_6a_aux_clk_src.clkr.hw,
3430	},
3431	.num_parents = 1,
3432	.flags = CLK_SET_RATE_PARENT,
3433	.ops = &clk_branch2_ops,
3434	},
3435	},
3436	};
3437
3438	static struct clk_branch gcc_pcie_6a_cfg_ahb_clk = {
3439	.halt_reg = 0x31034,
3440	.halt_check = BRANCH_HALT_VOTED,
3441	.hwcg_reg = 0x31034,
3442	.hwcg_bit = 1,
3443	.clkr = {
3444	.enable_reg = 0x52018,
3445	.enable_mask = BIT(23),
3446	.hw.init = &(const struct clk_init_data) {
3447	.name = "gcc_pcie_6a_cfg_ahb_clk",
3448	.ops = &clk_branch2_ops,
3449	},
3450	},
3451	};
3452
3453	static struct clk_branch gcc_pcie_6a_mstr_axi_clk = {
3454	.halt_reg = 0x31028,
3455	.halt_check = BRANCH_HALT_SKIP,
3456	.hwcg_reg = 0x31028,
3457	.hwcg_bit = 1,
3458	.clkr = {
3459	.enable_reg = 0x52018,
3460	.enable_mask = BIT(22),
3461	.hw.init = &(const struct clk_init_data) {
3462	.name = "gcc_pcie_6a_mstr_axi_clk",
3463	.ops = &clk_branch2_ops,
3464	},
3465	},
3466	};
3467
3468	static struct clk_branch gcc_pcie_6a_phy_aux_clk = {
3469	.halt_reg = 0x31044,
3470	.halt_check = BRANCH_HALT_VOTED,
3471	.clkr = {
3472	.enable_reg = 0x52018,
3473	.enable_mask = BIT(25),
3474	.hw.init = &(const struct clk_init_data) {
3475	.name = "gcc_pcie_6a_phy_aux_clk",
3476	.ops = &clk_branch2_ops,
3477	},
3478	},
3479	};
3480
3481	static struct clk_branch gcc_pcie_6a_phy_rchng_clk = {
3482	.halt_reg = 0x3105c,
3483	.halt_check = BRANCH_HALT_VOTED,
3484	.clkr = {
3485	.enable_reg = 0x52018,
3486	.enable_mask = BIT(27),
3487	.hw.init = &(const struct clk_init_data) {
3488	.name = "gcc_pcie_6a_phy_rchng_clk",
3489	.parent_hws = (const struct clk_hw*[]) {
3490	&gcc_pcie_6a_phy_rchng_clk_src.clkr.hw,
3491	},
3492	.num_parents = 1,
3493	.flags = CLK_SET_RATE_PARENT,
3494	.ops = &clk_branch2_ops,
3495	},
3496	},
3497	};
3498
3499	static struct clk_branch gcc_pcie_6a_pipe_clk = {
3500	.halt_reg = 0x31050,
3501	.halt_check = BRANCH_HALT_VOTED,
3502	.clkr = {
3503	.enable_reg = 0x52018,
3504	.enable_mask = BIT(26),
3505	.hw.init = &(const struct clk_init_data) {
3506	.name = "gcc_pcie_6a_pipe_clk",
3507	.ops = &clk_branch2_ops,
3508	},
3509	},
3510	};
3511
3512	static struct clk_branch gcc_pcie_6a_pipediv2_clk = {
3513	.halt_reg = 0x31060,
3514	.halt_check = BRANCH_HALT_VOTED,
3515	.clkr = {
3516	.enable_reg = 0x52018,
3517	.enable_mask = BIT(28),
3518	.hw.init = &(const struct clk_init_data) {
3519	.name = "gcc_pcie_6a_pipediv2_clk",
3520	.parent_hws = (const struct clk_hw*[]) {
3521	&gcc_pcie_6a_pipe_div_clk_src.clkr.hw,
3522	},
3523	.num_parents = 1,
3524	.flags = CLK_SET_RATE_PARENT,
3525	.ops = &clk_branch2_ops,
3526	},
3527	},
3528	};
3529
3530	static struct clk_branch gcc_pcie_6a_slv_axi_clk = {
3531	.halt_reg = 0x3101c,
3532	.halt_check = BRANCH_HALT_VOTED,
3533	.hwcg_reg = 0x3101c,
3534	.hwcg_bit = 1,
3535	.clkr = {
3536	.enable_reg = 0x52018,
3537	.enable_mask = BIT(21),
3538	.hw.init = &(const struct clk_init_data) {
3539	.name = "gcc_pcie_6a_slv_axi_clk",
3540	.ops = &clk_branch2_ops,
3541	},
3542	},
3543	};
3544
3545	static struct clk_branch gcc_pcie_6a_slv_q2a_axi_clk = {
3546	.halt_reg = 0x31018,
3547	.halt_check = BRANCH_HALT_VOTED,
3548	.clkr = {
3549	.enable_reg = 0x52018,
3550	.enable_mask = BIT(20),
3551	.hw.init = &(const struct clk_init_data) {
3552	.name = "gcc_pcie_6a_slv_q2a_axi_clk",
3553	.ops = &clk_branch2_ops,
3554	},
3555	},
3556	};
3557
3558	static struct clk_branch gcc_pcie_6b_aux_clk = {
3559	.halt_reg = 0x8d038,
3560	.halt_check = BRANCH_HALT_VOTED,
3561	.clkr = {
3562	.enable_reg = 0x52000,
3563	.enable_mask = BIT(29),
3564	.hw.init = &(const struct clk_init_data) {
3565	.name = "gcc_pcie_6b_aux_clk",
3566	.parent_hws = (const struct clk_hw*[]) {
3567	&gcc_pcie_6b_aux_clk_src.clkr.hw,
3568	},
3569	.num_parents = 1,
3570	.flags = CLK_SET_RATE_PARENT,
3571	.ops = &clk_branch2_ops,
3572	},
3573	},
3574	};
3575
3576	static struct clk_branch gcc_pcie_6b_cfg_ahb_clk = {
3577	.halt_reg = 0x8d034,
3578	.halt_check = BRANCH_HALT_VOTED,
3579	.hwcg_reg = 0x8d034,
3580	.hwcg_bit = 1,
3581	.clkr = {
3582	.enable_reg = 0x52000,
3583	.enable_mask = BIT(28),
3584	.hw.init = &(const struct clk_init_data) {
3585	.name = "gcc_pcie_6b_cfg_ahb_clk",
3586	.ops = &clk_branch2_ops,
3587	},
3588	},
3589	};
3590
3591	static struct clk_branch gcc_pcie_6b_mstr_axi_clk = {
3592	.halt_reg = 0x8d028,
3593	.halt_check = BRANCH_HALT_SKIP,
3594	.hwcg_reg = 0x8d028,
3595	.hwcg_bit = 1,
3596	.clkr = {
3597	.enable_reg = 0x52000,
3598	.enable_mask = BIT(27),
3599	.hw.init = &(const struct clk_init_data) {
3600	.name = "gcc_pcie_6b_mstr_axi_clk",
3601	.ops = &clk_branch2_ops,
3602	},
3603	},
3604	};
3605
3606	static struct clk_branch gcc_pcie_6b_phy_aux_clk = {
3607	.halt_reg = 0x8d044,
3608	.halt_check = BRANCH_HALT_VOTED,
3609	.clkr = {
3610	.enable_reg = 0x52000,
3611	.enable_mask = BIT(24),
3612	.hw.init = &(const struct clk_init_data) {
3613	.name = "gcc_pcie_6b_phy_aux_clk",
3614	.ops = &clk_branch2_ops,
3615	},
3616	},
3617	};
3618
3619	static struct clk_branch gcc_pcie_6b_phy_rchng_clk = {
3620	.halt_reg = 0x8d05c,
3621	.halt_check = BRANCH_HALT_VOTED,
3622	.clkr = {
3623	.enable_reg = 0x52000,
3624	.enable_mask = BIT(23),
3625	.hw.init = &(const struct clk_init_data) {
3626	.name = "gcc_pcie_6b_phy_rchng_clk",
3627	.parent_hws = (const struct clk_hw*[]) {
3628	&gcc_pcie_6b_phy_rchng_clk_src.clkr.hw,
3629	},
3630	.num_parents = 1,
3631	.flags = CLK_SET_RATE_PARENT,
3632	.ops = &clk_branch2_ops,
3633	},
3634	},
3635	};
3636
3637	static struct clk_branch gcc_pcie_6b_pipe_clk = {
3638	.halt_reg = 0x8d050,
3639	.halt_check = BRANCH_HALT_VOTED,
3640	.clkr = {
3641	.enable_reg = 0x52000,
3642	.enable_mask = BIT(30),
3643	.hw.init = &(const struct clk_init_data) {
3644	.name = "gcc_pcie_6b_pipe_clk",
3645	.ops = &clk_branch2_ops,
3646	},
3647	},
3648	};
3649
3650	static struct clk_branch gcc_pcie_6b_pipediv2_clk = {
3651	.halt_reg = 0x8d060,
3652	.halt_check = BRANCH_HALT_VOTED,
3653	.clkr = {
3654	.enable_reg = 0x52010,
3655	.enable_mask = BIT(28),
3656	.hw.init = &(const struct clk_init_data) {
3657	.name = "gcc_pcie_6b_pipediv2_clk",
3658	.parent_hws = (const struct clk_hw*[]) {
3659	&gcc_pcie_6b_pipe_div_clk_src.clkr.hw,
3660	},
3661	.num_parents = 1,
3662	.flags = CLK_SET_RATE_PARENT,
3663	.ops = &clk_branch2_ops,
3664	},
3665	},
3666	};
3667
3668	static struct clk_branch gcc_pcie_6b_slv_axi_clk = {
3669	.halt_reg = 0x8d01c,
3670	.halt_check = BRANCH_HALT_VOTED,
3671	.hwcg_reg = 0x8d01c,
3672	.hwcg_bit = 1,
3673	.clkr = {
3674	.enable_reg = 0x52000,
3675	.enable_mask = BIT(26),
3676	.hw.init = &(const struct clk_init_data) {
3677	.name = "gcc_pcie_6b_slv_axi_clk",
3678	.ops = &clk_branch2_ops,
3679	},
3680	},
3681	};
3682
3683	static struct clk_branch gcc_pcie_6b_slv_q2a_axi_clk = {
3684	.halt_reg = 0x8d018,
3685	.halt_check = BRANCH_HALT_VOTED,
3686	.clkr = {
3687	.enable_reg = 0x52000,
3688	.enable_mask = BIT(25),
3689	.hw.init = &(const struct clk_init_data) {
3690	.name = "gcc_pcie_6b_slv_q2a_axi_clk",
3691	.ops = &clk_branch2_ops,
3692	},
3693	},
3694	};
3695
3696	static struct clk_branch gcc_pcie_rscc_ahb_clk = {
3697	.halt_reg = 0xa4008,
3698	.halt_check = BRANCH_HALT_VOTED,
3699	.hwcg_reg = 0xa4008,
3700	.hwcg_bit = 1,
3701	.clkr = {
3702	.enable_reg = 0x52028,
3703	.enable_mask = BIT(18),
3704	.hw.init = &(const struct clk_init_data) {
3705	.name = "gcc_pcie_rscc_ahb_clk",
3706	.ops = &clk_branch2_ops,
3707	},
3708	},
3709	};
3710
3711	static struct clk_branch gcc_pcie_rscc_xo_clk = {
3712	.halt_reg = 0xa4004,
3713	.halt_check = BRANCH_HALT_VOTED,
3714	.clkr = {
3715	.enable_reg = 0x52028,
3716	.enable_mask = BIT(17),
3717	.hw.init = &(const struct clk_init_data) {
3718	.name = "gcc_pcie_rscc_xo_clk",
3719	.parent_hws = (const struct clk_hw*[]) {
3720	&gcc_pcie_rscc_xo_clk_src.clkr.hw,
3721	},
3722	.num_parents = 1,
3723	.flags = CLK_SET_RATE_PARENT,
3724	.ops = &clk_branch2_ops,
3725	},
3726	},
3727	};
3728
3729	static struct clk_branch gcc_pdm2_clk = {
3730	.halt_reg = 0x3300c,
3731	.halt_check = BRANCH_HALT,
3732	.clkr = {
3733	.enable_reg = 0x3300c,
3734	.enable_mask = BIT(0),
3735	.hw.init = &(const struct clk_init_data) {
3736	.name = "gcc_pdm2_clk",
3737	.parent_hws = (const struct clk_hw*[]) {
3738	&gcc_pdm2_clk_src.clkr.hw,
3739	},
3740	.num_parents = 1,
3741	.flags = CLK_SET_RATE_PARENT,
3742	.ops = &clk_branch2_ops,
3743	},
3744	},
3745	};
3746
3747	static struct clk_branch gcc_pdm_ahb_clk = {
3748	.halt_reg = 0x33004,
3749	.halt_check = BRANCH_HALT_VOTED,
3750	.hwcg_reg = 0x33004,
3751	.hwcg_bit = 1,
3752	.clkr = {
3753	.enable_reg = 0x33004,
3754	.enable_mask = BIT(0),
3755	.hw.init = &(const struct clk_init_data) {
3756	.name = "gcc_pdm_ahb_clk",
3757	.ops = &clk_branch2_ops,
3758	},
3759	},
3760	};
3761
3762	static struct clk_branch gcc_pdm_xo4_clk = {
3763	.halt_reg = 0x33008,
3764	.halt_check = BRANCH_HALT,
3765	.clkr = {
3766	.enable_reg = 0x33008,
3767	.enable_mask = BIT(0),
3768	.hw.init = &(const struct clk_init_data) {
3769	.name = "gcc_pdm_xo4_clk",
3770	.ops = &clk_branch2_ops,
3771	},
3772	},
3773	};
3774
3775	static struct clk_branch gcc_qmip_av1e_ahb_clk = {
3776	.halt_reg = 0x4a018,
3777	.halt_check = BRANCH_HALT_VOTED,
3778	.hwcg_reg = 0x4a018,
3779	.hwcg_bit = 1,
3780	.clkr = {
3781	.enable_reg = 0x4a018,
3782	.enable_mask = BIT(0),
3783	.hw.init = &(const struct clk_init_data) {
3784	.name = "gcc_qmip_av1e_ahb_clk",
3785	.ops = &clk_branch2_ops,
3786	},
3787	},
3788	};
3789
3790	static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
3791	.halt_reg = 0x26008,
3792	.halt_check = BRANCH_HALT_VOTED,
3793	.hwcg_reg = 0x26008,
3794	.hwcg_bit = 1,
3795	.clkr = {
3796	.enable_reg = 0x26008,
3797	.enable_mask = BIT(0),
3798	.hw.init = &(const struct clk_init_data) {
3799	.name = "gcc_qmip_camera_nrt_ahb_clk",
3800	.ops = &clk_branch2_ops,
3801	},
3802	},
3803	};
3804
3805	static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
3806	.halt_reg = 0x2600c,
3807	.halt_check = BRANCH_HALT_VOTED,
3808	.hwcg_reg = 0x2600c,
3809	.hwcg_bit = 1,
3810	.clkr = {
3811	.enable_reg = 0x2600c,
3812	.enable_mask = BIT(0),
3813	.hw.init = &(const struct clk_init_data) {
3814	.name = "gcc_qmip_camera_rt_ahb_clk",
3815	.ops = &clk_branch2_ops,
3816	},
3817	},
3818	};
3819
3820	static struct clk_branch gcc_qmip_disp_ahb_clk = {
3821	.halt_reg = 0x27008,
3822	.halt_check = BRANCH_HALT_VOTED,
3823	.hwcg_reg = 0x27008,
3824	.hwcg_bit = 1,
3825	.clkr = {
3826	.enable_reg = 0x27008,
3827	.enable_mask = BIT(0),
3828	.hw.init = &(const struct clk_init_data) {
3829	.name = "gcc_qmip_disp_ahb_clk",
3830	.ops = &clk_branch2_ops,
3831	},
3832	},
3833	};
3834
3835	static struct clk_branch gcc_qmip_gpu_ahb_clk = {
3836	.halt_reg = 0x71008,
3837	.halt_check = BRANCH_HALT_VOTED,
3838	.hwcg_reg = 0x71008,
3839	.hwcg_bit = 1,
3840	.clkr = {
3841	.enable_reg = 0x71008,
3842	.enable_mask = BIT(0),
3843	.hw.init = &(const struct clk_init_data) {
3844	.name = "gcc_qmip_gpu_ahb_clk",
3845	.ops = &clk_branch2_ops,
3846	},
3847	},
3848	};
3849
3850	static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = {
3851	.halt_reg = 0x32014,
3852	.halt_check = BRANCH_HALT_VOTED,
3853	.hwcg_reg = 0x32014,
3854	.hwcg_bit = 1,
3855	.clkr = {
3856	.enable_reg = 0x32014,
3857	.enable_mask = BIT(0),
3858	.hw.init = &(const struct clk_init_data) {
3859	.name = "gcc_qmip_video_cv_cpu_ahb_clk",
3860	.ops = &clk_branch2_ops,
3861	},
3862	},
3863	};
3864
3865	static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
3866	.halt_reg = 0x32008,
3867	.halt_check = BRANCH_HALT_VOTED,
3868	.hwcg_reg = 0x32008,
3869	.hwcg_bit = 1,
3870	.clkr = {
3871	.enable_reg = 0x32008,
3872	.enable_mask = BIT(0),
3873	.hw.init = &(const struct clk_init_data) {
3874	.name = "gcc_qmip_video_cvp_ahb_clk",
3875	.ops = &clk_branch2_ops,
3876	},
3877	},
3878	};
3879
3880	static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
3881	.halt_reg = 0x32010,
3882	.halt_check = BRANCH_HALT_VOTED,
3883	.hwcg_reg = 0x32010,
3884	.hwcg_bit = 1,
3885	.clkr = {
3886	.enable_reg = 0x32010,
3887	.enable_mask = BIT(0),
3888	.hw.init = &(const struct clk_init_data) {
3889	.name = "gcc_qmip_video_v_cpu_ahb_clk",
3890	.ops = &clk_branch2_ops,
3891	},
3892	},
3893	};
3894
3895	static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
3896	.halt_reg = 0x3200c,
3897	.halt_check = BRANCH_HALT_VOTED,
3898	.hwcg_reg = 0x3200c,
3899	.hwcg_bit = 1,
3900	.clkr = {
3901	.enable_reg = 0x3200c,
3902	.enable_mask = BIT(0),
3903	.hw.init = &(const struct clk_init_data) {
3904	.name = "gcc_qmip_video_vcodec_ahb_clk",
3905	.ops = &clk_branch2_ops,
3906	},
3907	},
3908	};
3909
3910	static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = {
3911	.halt_reg = 0x23018,
3912	.halt_check = BRANCH_HALT_VOTED,
3913	.clkr = {
3914	.enable_reg = 0x52020,
3915	.enable_mask = BIT(9),
3916	.hw.init = &(const struct clk_init_data) {
3917	.name = "gcc_qupv3_wrap0_core_2x_clk",
3918	.ops = &clk_branch2_ops,
3919	},
3920	},
3921	};
3922
3923	static struct clk_branch gcc_qupv3_wrap0_core_clk = {
3924	.halt_reg = 0x23008,
3925	.halt_check = BRANCH_HALT_VOTED,
3926	.clkr = {
3927	.enable_reg = 0x52020,
3928	.enable_mask = BIT(8),
3929	.hw.init = &(const struct clk_init_data) {
3930	.name = "gcc_qupv3_wrap0_core_clk",
3931	.ops = &clk_branch2_ops,
3932	},
3933	},
3934	};
3935
3936	static struct clk_branch gcc_qupv3_wrap0_qspi_s2_clk = {
3937	.halt_reg = 0x42280,
3938	.halt_check = BRANCH_HALT_VOTED,
3939	.clkr = {
3940	.enable_reg = 0x52028,
3941	.enable_mask = BIT(2),
3942	.hw.init = &(const struct clk_init_data) {
3943	.name = "gcc_qupv3_wrap0_qspi_s2_clk",
3944	.parent_hws = (const struct clk_hw*[]) {
3945	&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
3946	},
3947	.num_parents = 1,
3948	.flags = CLK_SET_RATE_PARENT,
3949	.ops = &clk_branch2_ops,
3950	},
3951	},
3952	};
3953
3954	static struct clk_branch gcc_qupv3_wrap0_qspi_s3_clk = {
3955	.halt_reg = 0x423c0,
3956	.halt_check = BRANCH_HALT_VOTED,
3957	.clkr = {
3958	.enable_reg = 0x52028,
3959	.enable_mask = BIT(3),
3960	.hw.init = &(const struct clk_init_data) {
3961	.name = "gcc_qupv3_wrap0_qspi_s3_clk",
3962	.parent_hws = (const struct clk_hw*[]) {
3963	&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
3964	},
3965	.num_parents = 1,
3966	.flags = CLK_SET_RATE_PARENT,
3967	.ops = &clk_branch2_ops,
3968	},
3969	},
3970	};
3971
3972	static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
3973	.halt_reg = 0x42004,
3974	.halt_check = BRANCH_HALT_VOTED,
3975	.clkr = {
3976	.enable_reg = 0x52020,
3977	.enable_mask = BIT(10),
3978	.hw.init = &(const struct clk_init_data) {
3979	.name = "gcc_qupv3_wrap0_s0_clk",
3980	.parent_hws = (const struct clk_hw*[]) {
3981	&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
3982	},
3983	.num_parents = 1,
3984	.flags = CLK_SET_RATE_PARENT,
3985	.ops = &clk_branch2_ops,
3986	},
3987	},
3988	};
3989
3990	static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
3991	.halt_reg = 0x4213c,
3992	.halt_check = BRANCH_HALT_VOTED,
3993	.clkr = {
3994	.enable_reg = 0x52020,
3995	.enable_mask = BIT(11),
3996	.hw.init = &(const struct clk_init_data) {
3997	.name = "gcc_qupv3_wrap0_s1_clk",
3998	.parent_hws = (const struct clk_hw*[]) {
3999	&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
4000	},
4001	.num_parents = 1,
4002	.flags = CLK_SET_RATE_PARENT,
4003	.ops = &clk_branch2_ops,
4004	},
4005	},
4006	};
4007
4008	static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
4009	.halt_reg = 0x42274,
4010	.halt_check = BRANCH_HALT_VOTED,
4011	.clkr = {
4012	.enable_reg = 0x52020,
4013	.enable_mask = BIT(12),
4014	.hw.init = &(const struct clk_init_data) {
4015	.name = "gcc_qupv3_wrap0_s2_clk",
4016	.parent_hws = (const struct clk_hw*[]) {
4017	&gcc_qupv3_wrap0_s2_div_clk_src.clkr.hw,
4018	},
4019	.num_parents = 1,
4020	.flags = CLK_SET_RATE_PARENT,
4021	.ops = &clk_branch2_ops,
4022	},
4023	},
4024	};
4025
4026	static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
4027	.halt_reg = 0x423b4,
4028	.halt_check = BRANCH_HALT_VOTED,
4029	.clkr = {
4030	.enable_reg = 0x52020,
4031	.enable_mask = BIT(13),
4032	.hw.init = &(const struct clk_init_data) {
4033	.name = "gcc_qupv3_wrap0_s3_clk",
4034	.parent_hws = (const struct clk_hw*[]) {
4035	&gcc_qupv3_wrap0_s3_div_clk_src.clkr.hw,
4036	},
4037	.num_parents = 1,
4038	.flags = CLK_SET_RATE_PARENT,
4039	.ops = &clk_branch2_ops,
4040	},
4041	},
4042	};
4043
4044	static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
4045	.halt_reg = 0x424f4,
4046	.halt_check = BRANCH_HALT_VOTED,
4047	.clkr = {
4048	.enable_reg = 0x52020,
4049	.enable_mask = BIT(14),
4050	.hw.init = &(const struct clk_init_data) {
4051	.name = "gcc_qupv3_wrap0_s4_clk",
4052	.parent_hws = (const struct clk_hw*[]) {
4053	&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
4054	},
4055	.num_parents = 1,
4056	.flags = CLK_SET_RATE_PARENT,
4057	.ops = &clk_branch2_ops,
4058	},
4059	},
4060	};
4061
4062	static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
4063	.halt_reg = 0x4262c,
4064	.halt_check = BRANCH_HALT_VOTED,
4065	.clkr = {
4066	.enable_reg = 0x52020,
4067	.enable_mask = BIT(15),
4068	.hw.init = &(const struct clk_init_data) {
4069	.name = "gcc_qupv3_wrap0_s5_clk",
4070	.parent_hws = (const struct clk_hw*[]) {
4071	&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
4072	},
4073	.num_parents = 1,
4074	.flags = CLK_SET_RATE_PARENT,
4075	.ops = &clk_branch2_ops,
4076	},
4077	},
4078	};
4079
4080	static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
4081	.halt_reg = 0x42764,
4082	.halt_check = BRANCH_HALT_VOTED,
4083	.clkr = {
4084	.enable_reg = 0x52020,
4085	.enable_mask = BIT(16),
4086	.hw.init = &(const struct clk_init_data) {
4087	.name = "gcc_qupv3_wrap0_s6_clk",
4088	.parent_hws = (const struct clk_hw*[]) {
4089	&gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
4090	},
4091	.num_parents = 1,
4092	.flags = CLK_SET_RATE_PARENT,
4093	.ops = &clk_branch2_ops,
4094	},
4095	},
4096	};
4097
4098	static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
4099	.halt_reg = 0x4289c,
4100	.halt_check = BRANCH_HALT_VOTED,
4101	.clkr = {
4102	.enable_reg = 0x52020,
4103	.enable_mask = BIT(17),
4104	.hw.init = &(const struct clk_init_data) {
4105	.name = "gcc_qupv3_wrap0_s7_clk",
4106	.parent_hws = (const struct clk_hw*[]) {
4107	&gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
4108	},
4109	.num_parents = 1,
4110	.flags = CLK_SET_RATE_PARENT,
4111	.ops = &clk_branch2_ops,
4112	},
4113	},
4114	};
4115
4116	static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
4117	.halt_reg = 0x23168,
4118	.halt_check = BRANCH_HALT_VOTED,
4119	.clkr = {
4120	.enable_reg = 0x52008,
4121	.enable_mask = BIT(18),
4122	.hw.init = &(const struct clk_init_data) {
4123	.name = "gcc_qupv3_wrap1_core_2x_clk",
4124	.ops = &clk_branch2_ops,
4125	},
4126	},
4127	};
4128
4129	static struct clk_branch gcc_qupv3_wrap1_core_clk = {
4130	.halt_reg = 0x23158,
4131	.halt_check = BRANCH_HALT_VOTED,
4132	.clkr = {
4133	.enable_reg = 0x52008,
4134	.enable_mask = BIT(19),
4135	.hw.init = &(const struct clk_init_data) {
4136	.name = "gcc_qupv3_wrap1_core_clk",
4137	.ops = &clk_branch2_ops,
4138	},
4139	},
4140	};
4141
4142	static struct clk_branch gcc_qupv3_wrap1_qspi_s2_clk = {
4143	.halt_reg = 0x18280,
4144	.halt_check = BRANCH_HALT_VOTED,
4145	.clkr = {
4146	.enable_reg = 0x52028,
4147	.enable_mask = BIT(4),
4148	.hw.init = &(const struct clk_init_data) {
4149	.name = "gcc_qupv3_wrap1_qspi_s2_clk",
4150	.parent_hws = (const struct clk_hw*[]) {
4151	&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
4152	},
4153	.num_parents = 1,
4154	.flags = CLK_SET_RATE_PARENT,
4155	.ops = &clk_branch2_ops,
4156	},
4157	},
4158	};
4159
4160	static struct clk_branch gcc_qupv3_wrap1_qspi_s3_clk = {
4161	.halt_reg = 0x183c0,
4162	.halt_check = BRANCH_HALT_VOTED,
4163	.clkr = {
4164	.enable_reg = 0x52028,
4165	.enable_mask = BIT(5),
4166	.hw.init = &(const struct clk_init_data) {
4167	.name = "gcc_qupv3_wrap1_qspi_s3_clk",
4168	.parent_hws = (const struct clk_hw*[]) {
4169	&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
4170	},
4171	.num_parents = 1,
4172	.flags = CLK_SET_RATE_PARENT,
4173	.ops = &clk_branch2_ops,
4174	},
4175	},
4176	};
4177
4178	static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
4179	.halt_reg = 0x18004,
4180	.halt_check = BRANCH_HALT_VOTED,
4181	.clkr = {
4182	.enable_reg = 0x52008,
4183	.enable_mask = BIT(22),
4184	.hw.init = &(const struct clk_init_data) {
4185	.name = "gcc_qupv3_wrap1_s0_clk",
4186	.parent_hws = (const struct clk_hw*[]) {
4187	&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
4188	},
4189	.num_parents = 1,
4190	.flags = CLK_SET_RATE_PARENT,
4191	.ops = &clk_branch2_ops,
4192	},
4193	},
4194	};
4195
4196	static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
4197	.halt_reg = 0x1813c,
4198	.halt_check = BRANCH_HALT_VOTED,
4199	.clkr = {
4200	.enable_reg = 0x52008,
4201	.enable_mask = BIT(23),
4202	.hw.init = &(const struct clk_init_data) {
4203	.name = "gcc_qupv3_wrap1_s1_clk",
4204	.parent_hws = (const struct clk_hw*[]) {
4205	&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
4206	},
4207	.num_parents = 1,
4208	.flags = CLK_SET_RATE_PARENT,
4209	.ops = &clk_branch2_ops,
4210	},
4211	},
4212	};
4213
4214	static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
4215	.halt_reg = 0x18274,
4216	.halt_check = BRANCH_HALT_VOTED,
4217	.clkr = {
4218	.enable_reg = 0x52008,
4219	.enable_mask = BIT(24),
4220	.hw.init = &(const struct clk_init_data) {
4221	.name = "gcc_qupv3_wrap1_s2_clk",
4222	.parent_hws = (const struct clk_hw*[]) {
4223	&gcc_qupv3_wrap1_s2_div_clk_src.clkr.hw,
4224	},
4225	.num_parents = 1,
4226	.flags = CLK_SET_RATE_PARENT,
4227	.ops = &clk_branch2_ops,
4228	},
4229	},
4230	};
4231
4232	static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
4233	.halt_reg = 0x183b4,
4234	.halt_check = BRANCH_HALT_VOTED,
4235	.clkr = {
4236	.enable_reg = 0x52008,
4237	.enable_mask = BIT(25),
4238	.hw.init = &(const struct clk_init_data) {
4239	.name = "gcc_qupv3_wrap1_s3_clk",
4240	.parent_hws = (const struct clk_hw*[]) {
4241	&gcc_qupv3_wrap1_s3_div_clk_src.clkr.hw,
4242	},
4243	.num_parents = 1,
4244	.flags = CLK_SET_RATE_PARENT,
4245	.ops = &clk_branch2_ops,
4246	},
4247	},
4248	};
4249
4250	static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
4251	.halt_reg = 0x184f4,
4252	.halt_check = BRANCH_HALT_VOTED,
4253	.clkr = {
4254	.enable_reg = 0x52008,
4255	.enable_mask = BIT(26),
4256	.hw.init = &(const struct clk_init_data) {
4257	.name = "gcc_qupv3_wrap1_s4_clk",
4258	.parent_hws = (const struct clk_hw*[]) {
4259	&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
4260	},
4261	.num_parents = 1,
4262	.flags = CLK_SET_RATE_PARENT,
4263	.ops = &clk_branch2_ops,
4264	},
4265	},
4266	};
4267
4268	static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
4269	.halt_reg = 0x1862c,
4270	.halt_check = BRANCH_HALT_VOTED,
4271	.clkr = {
4272	.enable_reg = 0x52008,
4273	.enable_mask = BIT(27),
4274	.hw.init = &(const struct clk_init_data) {
4275	.name = "gcc_qupv3_wrap1_s5_clk",
4276	.parent_hws = (const struct clk_hw*[]) {
4277	&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
4278	},
4279	.num_parents = 1,
4280	.flags = CLK_SET_RATE_PARENT,
4281	.ops = &clk_branch2_ops,
4282	},
4283	},
4284	};
4285
4286	static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
4287	.halt_reg = 0x18764,
4288	.halt_check = BRANCH_HALT_VOTED,
4289	.clkr = {
4290	.enable_reg = 0x52008,
4291	.enable_mask = BIT(28),
4292	.hw.init = &(const struct clk_init_data) {
4293	.name = "gcc_qupv3_wrap1_s6_clk",
4294	.parent_hws = (const struct clk_hw*[]) {
4295	&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
4296	},
4297	.num_parents = 1,
4298	.flags = CLK_SET_RATE_PARENT,
4299	.ops = &clk_branch2_ops,
4300	},
4301	},
4302	};
4303
4304	static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
4305	.halt_reg = 0x1889c,
4306	.halt_check = BRANCH_HALT_VOTED,
4307	.clkr = {
4308	.enable_reg = 0x52010,
4309	.enable_mask = BIT(16),
4310	.hw.init = &(const struct clk_init_data) {
4311	.name = "gcc_qupv3_wrap1_s7_clk",
4312	.parent_hws = (const struct clk_hw*[]) {
4313	&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
4314	},
4315	.num_parents = 1,
4316	.flags = CLK_SET_RATE_PARENT,
4317	.ops = &clk_branch2_ops,
4318	},
4319	},
4320	};
4321
4322	static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
4323	.halt_reg = 0x232b8,
4324	.halt_check = BRANCH_HALT_VOTED,
4325	.clkr = {
4326	.enable_reg = 0x52010,
4327	.enable_mask = BIT(3),
4328	.hw.init = &(const struct clk_init_data) {
4329	.name = "gcc_qupv3_wrap2_core_2x_clk",
4330	.ops = &clk_branch2_ops,
4331	},
4332	},
4333	};
4334
4335	static struct clk_branch gcc_qupv3_wrap2_core_clk = {
4336	.halt_reg = 0x232a8,
4337	.halt_check = BRANCH_HALT_VOTED,
4338	.clkr = {
4339	.enable_reg = 0x52010,
4340	.enable_mask = BIT(0),
4341	.hw.init = &(const struct clk_init_data) {
4342	.name = "gcc_qupv3_wrap2_core_clk",
4343	.ops = &clk_branch2_ops,
4344	},
4345	},
4346	};
4347
4348	static struct clk_branch gcc_qupv3_wrap2_qspi_s2_clk = {
4349	.halt_reg = 0x1e280,
4350	.halt_check = BRANCH_HALT_VOTED,
4351	.clkr = {
4352	.enable_reg = 0x52028,
4353	.enable_mask = BIT(6),
4354	.hw.init = &(const struct clk_init_data) {
4355	.name = "gcc_qupv3_wrap2_qspi_s2_clk",
4356	.parent_hws = (const struct clk_hw*[]) {
4357	&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
4358	},
4359	.num_parents = 1,
4360	.flags = CLK_SET_RATE_PARENT,
4361	.ops = &clk_branch2_ops,
4362	},
4363	},
4364	};
4365
4366	static struct clk_branch gcc_qupv3_wrap2_qspi_s3_clk = {
4367	.halt_reg = 0x1e3c0,
4368	.halt_check = BRANCH_HALT_VOTED,
4369	.clkr = {
4370	.enable_reg = 0x52028,
4371	.enable_mask = BIT(7),
4372	.hw.init = &(const struct clk_init_data) {
4373	.name = "gcc_qupv3_wrap2_qspi_s3_clk",
4374	.parent_hws = (const struct clk_hw*[]) {
4375	&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
4376	},
4377	.num_parents = 1,
4378	.flags = CLK_SET_RATE_PARENT,
4379	.ops = &clk_branch2_ops,
4380	},
4381	},
4382	};
4383
4384	static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
4385	.halt_reg = 0x1e004,
4386	.halt_check = BRANCH_HALT_VOTED,
4387	.clkr = {
4388	.enable_reg = 0x52010,
4389	.enable_mask = BIT(4),
4390	.hw.init = &(const struct clk_init_data) {
4391	.name = "gcc_qupv3_wrap2_s0_clk",
4392	.parent_hws = (const struct clk_hw*[]) {
4393	&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
4394	},
4395	.num_parents = 1,
4396	.flags = CLK_SET_RATE_PARENT,
4397	.ops = &clk_branch2_ops,
4398	},
4399	},
4400	};
4401
4402	static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
4403	.halt_reg = 0x1e13c,
4404	.halt_check = BRANCH_HALT_VOTED,
4405	.clkr = {
4406	.enable_reg = 0x52010,
4407	.enable_mask = BIT(5),
4408	.hw.init = &(const struct clk_init_data) {
4409	.name = "gcc_qupv3_wrap2_s1_clk",
4410	.parent_hws = (const struct clk_hw*[]) {
4411	&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
4412	},
4413	.num_parents = 1,
4414	.flags = CLK_SET_RATE_PARENT,
4415	.ops = &clk_branch2_ops,
4416	},
4417	},
4418	};
4419
4420	static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
4421	.halt_reg = 0x1e274,
4422	.halt_check = BRANCH_HALT_VOTED,
4423	.clkr = {
4424	.enable_reg = 0x52010,
4425	.enable_mask = BIT(6),
4426	.hw.init = &(const struct clk_init_data) {
4427	.name = "gcc_qupv3_wrap2_s2_clk",
4428	.parent_hws = (const struct clk_hw*[]) {
4429	&gcc_qupv3_wrap2_s2_div_clk_src.clkr.hw,
4430	},
4431	.num_parents = 1,
4432	.flags = CLK_SET_RATE_PARENT,
4433	.ops = &clk_branch2_ops,
4434	},
4435	},
4436	};
4437
4438	static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
4439	.halt_reg = 0x1e3b4,
4440	.halt_check = BRANCH_HALT_VOTED,
4441	.clkr = {
4442	.enable_reg = 0x52010,
4443	.enable_mask = BIT(7),
4444	.hw.init = &(const struct clk_init_data) {
4445	.name = "gcc_qupv3_wrap2_s3_clk",
4446	.parent_hws = (const struct clk_hw*[]) {
4447	&gcc_qupv3_wrap2_s3_div_clk_src.clkr.hw,
4448	},
4449	.num_parents = 1,
4450	.flags = CLK_SET_RATE_PARENT,
4451	.ops = &clk_branch2_ops,
4452	},
4453	},
4454	};
4455
4456	static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
4457	.halt_reg = 0x1e4f4,
4458	.halt_check = BRANCH_HALT_VOTED,
4459	.clkr = {
4460	.enable_reg = 0x52010,
4461	.enable_mask = BIT(8),
4462	.hw.init = &(const struct clk_init_data) {
4463	.name = "gcc_qupv3_wrap2_s4_clk",
4464	.parent_hws = (const struct clk_hw*[]) {
4465	&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
4466	},
4467	.num_parents = 1,
4468	.flags = CLK_SET_RATE_PARENT,
4469	.ops = &clk_branch2_ops,
4470	},
4471	},
4472	};
4473
4474	static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
4475	.halt_reg = 0x1e62c,
4476	.halt_check = BRANCH_HALT_VOTED,
4477	.clkr = {
4478	.enable_reg = 0x52010,
4479	.enable_mask = BIT(9),
4480	.hw.init = &(const struct clk_init_data) {
4481	.name = "gcc_qupv3_wrap2_s5_clk",
4482	.parent_hws = (const struct clk_hw*[]) {
4483	&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
4484	},
4485	.num_parents = 1,
4486	.flags = CLK_SET_RATE_PARENT,
4487	.ops = &clk_branch2_ops,
4488	},
4489	},
4490	};
4491
4492	static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
4493	.halt_reg = 0x1e764,
4494	.halt_check = BRANCH_HALT_VOTED,
4495	.clkr = {
4496	.enable_reg = 0x52010,
4497	.enable_mask = BIT(10),
4498	.hw.init = &(const struct clk_init_data) {
4499	.name = "gcc_qupv3_wrap2_s6_clk",
4500	.parent_hws = (const struct clk_hw*[]) {
4501	&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
4502	},
4503	.num_parents = 1,
4504	.flags = CLK_SET_RATE_PARENT,
4505	.ops = &clk_branch2_ops,
4506	},
4507	},
4508	};
4509
4510	static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
4511	.halt_reg = 0x1e89c,
4512	.halt_check = BRANCH_HALT_VOTED,
4513	.clkr = {
4514	.enable_reg = 0x52010,
4515	.enable_mask = BIT(17),
4516	.hw.init = &(const struct clk_init_data) {
4517	.name = "gcc_qupv3_wrap2_s7_clk",
4518	.parent_hws = (const struct clk_hw*[]) {
4519	&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
4520	},
4521	.num_parents = 1,
4522	.flags = CLK_SET_RATE_PARENT,
4523	.ops = &clk_branch2_ops,
4524	},
4525	},
4526	};
4527
4528	static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
4529	.halt_reg = 0x23000,
4530	.halt_check = BRANCH_HALT_VOTED,
4531	.hwcg_reg = 0x23000,
4532	.hwcg_bit = 1,
4533	.clkr = {
4534	.enable_reg = 0x52020,
4535	.enable_mask = BIT(6),
4536	.hw.init = &(const struct clk_init_data) {
4537	.name = "gcc_qupv3_wrap_0_m_ahb_clk",
4538	.ops = &clk_branch2_ops,
4539	},
4540	},
4541	};
4542
4543	static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
4544	.halt_reg = 0x23004,
4545	.halt_check = BRANCH_HALT_VOTED,
4546	.hwcg_reg = 0x23004,
4547	.hwcg_bit = 1,
4548	.clkr = {
4549	.enable_reg = 0x52020,
4550	.enable_mask = BIT(7),
4551	.hw.init = &(const struct clk_init_data) {
4552	.name = "gcc_qupv3_wrap_0_s_ahb_clk",
4553	.ops = &clk_branch2_ops,
4554	},
4555	},
4556	};
4557
4558	static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
4559	.halt_reg = 0x23150,
4560	.halt_check = BRANCH_HALT_VOTED,
4561	.hwcg_reg = 0x23150,
4562	.hwcg_bit = 1,
4563	.clkr = {
4564	.enable_reg = 0x52008,
4565	.enable_mask = BIT(20),
4566	.hw.init = &(const struct clk_init_data) {
4567	.name = "gcc_qupv3_wrap_1_m_ahb_clk",
4568	.ops = &clk_branch2_ops,
4569	},
4570	},
4571	};
4572
4573	static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
4574	.halt_reg = 0x23154,
4575	.halt_check = BRANCH_HALT_VOTED,
4576	.hwcg_reg = 0x23154,
4577	.hwcg_bit = 1,
4578	.clkr = {
4579	.enable_reg = 0x52008,
4580	.enable_mask = BIT(21),
4581	.hw.init = &(const struct clk_init_data) {
4582	.name = "gcc_qupv3_wrap_1_s_ahb_clk",
4583	.ops = &clk_branch2_ops,
4584	},
4585	},
4586	};
4587
4588	static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
4589	.halt_reg = 0x232a0,
4590	.halt_check = BRANCH_HALT_VOTED,
4591	.hwcg_reg = 0x232a0,
4592	.hwcg_bit = 1,
4593	.clkr = {
4594	.enable_reg = 0x52010,
4595	.enable_mask = BIT(2),
4596	.hw.init = &(const struct clk_init_data) {
4597	.name = "gcc_qupv3_wrap_2_m_ahb_clk",
4598	.ops = &clk_branch2_ops,
4599	},
4600	},
4601	};
4602
4603	static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
4604	.halt_reg = 0x232a4,
4605	.halt_check = BRANCH_HALT_VOTED,
4606	.hwcg_reg = 0x232a4,
4607	.hwcg_bit = 1,
4608	.clkr = {
4609	.enable_reg = 0x52010,
4610	.enable_mask = BIT(1),
4611	.hw.init = &(const struct clk_init_data) {
4612	.name = "gcc_qupv3_wrap_2_s_ahb_clk",
4613	.ops = &clk_branch2_ops,
4614	},
4615	},
4616	};
4617
4618	static struct clk_branch gcc_sdcc2_ahb_clk = {
4619	.halt_reg = 0x14010,
4620	.halt_check = BRANCH_HALT,
4621	.clkr = {
4622	.enable_reg = 0x14010,
4623	.enable_mask = BIT(0),
4624	.hw.init = &(const struct clk_init_data) {
4625	.name = "gcc_sdcc2_ahb_clk",
4626	.ops = &clk_branch2_ops,
4627	},
4628	},
4629	};
4630
4631	static struct clk_branch gcc_sdcc2_apps_clk = {
4632	.halt_reg = 0x14004,
4633	.halt_check = BRANCH_HALT,
4634	.clkr = {
4635	.enable_reg = 0x14004,
4636	.enable_mask = BIT(0),
4637	.hw.init = &(const struct clk_init_data) {
4638	.name = "gcc_sdcc2_apps_clk",
4639	.parent_hws = (const struct clk_hw*[]) {
4640	&gcc_sdcc2_apps_clk_src.clkr.hw,
4641	},
4642	.num_parents = 1,
4643	.flags = CLK_SET_RATE_PARENT,
4644	.ops = &clk_branch2_ops,
4645	},
4646	},
4647	};
4648
4649	static struct clk_branch gcc_sdcc4_ahb_clk = {
4650	.halt_reg = 0x16010,
4651	.halt_check = BRANCH_HALT,
4652	.clkr = {
4653	.enable_reg = 0x16010,
4654	.enable_mask = BIT(0),
4655	.hw.init = &(const struct clk_init_data) {
4656	.name = "gcc_sdcc4_ahb_clk",
4657	.ops = &clk_branch2_ops,
4658	},
4659	},
4660	};
4661
4662	static struct clk_branch gcc_sdcc4_apps_clk = {
4663	.halt_reg = 0x16004,
4664	.halt_check = BRANCH_HALT,
4665	.clkr = {
4666	.enable_reg = 0x16004,
4667	.enable_mask = BIT(0),
4668	.hw.init = &(const struct clk_init_data) {
4669	.name = "gcc_sdcc4_apps_clk",
4670	.parent_hws = (const struct clk_hw*[]) {
4671	&gcc_sdcc4_apps_clk_src.clkr.hw,
4672	},
4673	.num_parents = 1,
4674	.flags = CLK_SET_RATE_PARENT,
4675	.ops = &clk_branch2_ops,
4676	},
4677	},
4678	};
4679
4680	static struct clk_branch gcc_sys_noc_usb_axi_clk = {
4681	.halt_reg = 0x2d014,
4682	.halt_check = BRANCH_HALT_VOTED,
4683	.hwcg_reg = 0x2d014,
4684	.hwcg_bit = 1,
4685	.clkr = {
4686	.enable_reg = 0x2d014,
4687	.enable_mask = BIT(0),
4688	.hw.init = &(const struct clk_init_data) {
4689	.name = "gcc_sys_noc_usb_axi_clk",
4690	.ops = &clk_branch2_ops,
4691	},
4692	},
4693	};
4694
4695	static struct clk_branch gcc_ufs_phy_ahb_clk = {
4696	.halt_reg = 0x77024,
4697	.halt_check = BRANCH_HALT_VOTED,
4698	.hwcg_reg = 0x77024,
4699	.hwcg_bit = 1,
4700	.clkr = {
4701	.enable_reg = 0x77024,
4702	.enable_mask = BIT(0),
4703	.hw.init = &(const struct clk_init_data) {
4704	.name = "gcc_ufs_phy_ahb_clk",
4705	.ops = &clk_branch2_ops,
4706	},
4707	},
4708	};
4709
4710	static struct clk_branch gcc_ufs_phy_axi_clk = {
4711	.halt_reg = 0x77018,
4712	.halt_check = BRANCH_HALT_VOTED,
4713	.hwcg_reg = 0x77018,
4714	.hwcg_bit = 1,
4715	.clkr = {
4716	.enable_reg = 0x77018,
4717	.enable_mask = BIT(0),
4718	.hw.init = &(const struct clk_init_data) {
4719	.name = "gcc_ufs_phy_axi_clk",
4720	.parent_hws = (const struct clk_hw*[]) {
4721	&gcc_ufs_phy_axi_clk_src.clkr.hw,
4722	},
4723	.num_parents = 1,
4724	.flags = CLK_SET_RATE_PARENT,
4725	.ops = &clk_branch2_ops,
4726	},
4727	},
4728	};
4729
4730	static struct clk_branch gcc_ufs_phy_ice_core_clk = {
4731	.halt_reg = 0x77074,
4732	.halt_check = BRANCH_HALT_VOTED,
4733	.hwcg_reg = 0x77074,
4734	.hwcg_bit = 1,
4735	.clkr = {
4736	.enable_reg = 0x77074,
4737	.enable_mask = BIT(0),
4738	.hw.init = &(const struct clk_init_data) {
4739	.name = "gcc_ufs_phy_ice_core_clk",
4740	.parent_hws = (const struct clk_hw*[]) {
4741	&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
4742	},
4743	.num_parents = 1,
4744	.flags = CLK_SET_RATE_PARENT,
4745	.ops = &clk_branch2_ops,
4746	},
4747	},
4748	};
4749
4750	static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
4751	.halt_reg = 0x770b0,
4752	.halt_check = BRANCH_HALT_VOTED,
4753	.hwcg_reg = 0x770b0,
4754	.hwcg_bit = 1,
4755	.clkr = {
4756	.enable_reg = 0x770b0,
4757	.enable_mask = BIT(0),
4758	.hw.init = &(const struct clk_init_data) {
4759	.name = "gcc_ufs_phy_phy_aux_clk",
4760	.parent_hws = (const struct clk_hw*[]) {
4761	&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
4762	},
4763	.num_parents = 1,
4764	.flags = CLK_SET_RATE_PARENT,
4765	.ops = &clk_branch2_ops,
4766	},
4767	},
4768	};
4769
4770	static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
4771	.halt_reg = 0x7702c,
4772	.halt_check = BRANCH_HALT,
4773	.clkr = {
4774	.enable_reg = 0x7702c,
4775	.enable_mask = BIT(0),
4776	.hw.init = &(const struct clk_init_data) {
4777	.name = "gcc_ufs_phy_rx_symbol_0_clk",
4778	.ops = &clk_branch2_ops,
4779	},
4780	},
4781	};
4782
4783	static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
4784	.halt_reg = 0x770cc,
4785	.halt_check = BRANCH_HALT,
4786	.clkr = {
4787	.enable_reg = 0x770cc,
4788	.enable_mask = BIT(0),
4789	.hw.init = &(const struct clk_init_data) {
4790	.name = "gcc_ufs_phy_rx_symbol_1_clk",
4791	.ops = &clk_branch2_ops,
4792	},
4793	},
4794	};
4795
4796	static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
4797	.halt_reg = 0x77028,
4798	.halt_check = BRANCH_HALT,
4799	.clkr = {
4800	.enable_reg = 0x77028,
4801	.enable_mask = BIT(0),
4802	.hw.init = &(const struct clk_init_data) {
4803	.name = "gcc_ufs_phy_tx_symbol_0_clk",
4804	.ops = &clk_branch2_ops,
4805	},
4806	},
4807	};
4808
4809	static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
4810	.halt_reg = 0x77068,
4811	.halt_check = BRANCH_HALT_VOTED,
4812	.hwcg_reg = 0x77068,
4813	.hwcg_bit = 1,
4814	.clkr = {
4815	.enable_reg = 0x77068,
4816	.enable_mask = BIT(0),
4817	.hw.init = &(const struct clk_init_data) {
4818	.name = "gcc_ufs_phy_unipro_core_clk",
4819	.parent_hws = (const struct clk_hw*[]) {
4820	&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
4821	},
4822	.num_parents = 1,
4823	.flags = CLK_SET_RATE_PARENT,
4824	.ops = &clk_branch2_ops,
4825	},
4826	},
4827	};
4828
4829	static struct clk_branch gcc_usb20_master_clk = {
4830	.halt_reg = 0x29018,
4831	.halt_check = BRANCH_HALT,
4832	.clkr = {
4833	.enable_reg = 0x29018,
4834	.enable_mask = BIT(0),
4835	.hw.init = &(const struct clk_init_data) {
4836	.name = "gcc_usb20_master_clk",
4837	.parent_hws = (const struct clk_hw*[]) {
4838	&gcc_usb20_master_clk_src.clkr.hw,
4839	},
4840	.num_parents = 1,
4841	.flags = CLK_SET_RATE_PARENT,
4842	.ops = &clk_branch2_ops,
4843	},
4844	},
4845	};
4846
4847	static struct clk_branch gcc_usb20_mock_utmi_clk = {
4848	.halt_reg = 0x29028,
4849	.halt_check = BRANCH_HALT,
4850	.clkr = {
4851	.enable_reg = 0x29028,
4852	.enable_mask = BIT(0),
4853	.hw.init = &(const struct clk_init_data) {
4854	.name = "gcc_usb20_mock_utmi_clk",
4855	.parent_hws = (const struct clk_hw*[]) {
4856	&gcc_usb20_mock_utmi_postdiv_clk_src.clkr.hw,
4857	},
4858	.num_parents = 1,
4859	.flags = CLK_SET_RATE_PARENT,
4860	.ops = &clk_branch2_ops,
4861	},
4862	},
4863	};
4864
4865	static struct clk_branch gcc_usb20_sleep_clk = {
4866	.halt_reg = 0x29024,
4867	.halt_check = BRANCH_HALT,
4868	.clkr = {
4869	.enable_reg = 0x29024,
4870	.enable_mask = BIT(0),
4871	.hw.init = &(const struct clk_init_data) {
4872	.name = "gcc_usb20_sleep_clk",
4873	.ops = &clk_branch2_ops,
4874	},
4875	},
4876	};
4877
4878	static struct clk_branch gcc_usb30_mp_master_clk = {
4879	.halt_reg = 0x17018,
4880	.halt_check = BRANCH_HALT,
4881	.clkr = {
4882	.enable_reg = 0x17018,
4883	.enable_mask = BIT(0),
4884	.hw.init = &(const struct clk_init_data) {
4885	.name = "gcc_usb30_mp_master_clk",
4886	.parent_hws = (const struct clk_hw*[]) {
4887	&gcc_usb30_mp_master_clk_src.clkr.hw,
4888	},
4889	.num_parents = 1,
4890	.flags = CLK_SET_RATE_PARENT,
4891	.ops = &clk_branch2_ops,
4892	},
4893	},
4894	};
4895
4896	static struct clk_branch gcc_usb30_mp_mock_utmi_clk = {
4897	.halt_reg = 0x17028,
4898	.halt_check = BRANCH_HALT,
4899	.clkr = {
4900	.enable_reg = 0x17028,
4901	.enable_mask = BIT(0),
4902	.hw.init = &(const struct clk_init_data) {
4903	.name = "gcc_usb30_mp_mock_utmi_clk",
4904	.parent_hws = (const struct clk_hw*[]) {
4905	&gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr.hw,
4906	},
4907	.num_parents = 1,
4908	.flags = CLK_SET_RATE_PARENT,
4909	.ops = &clk_branch2_ops,
4910	},
4911	},
4912	};
4913
4914	static struct clk_branch gcc_usb30_mp_sleep_clk = {
4915	.halt_reg = 0x17024,
4916	.halt_check = BRANCH_HALT,
4917	.clkr = {
4918	.enable_reg = 0x17024,
4919	.enable_mask = BIT(0),
4920	.hw.init = &(const struct clk_init_data) {
4921	.name = "gcc_usb30_mp_sleep_clk",
4922	.ops = &clk_branch2_ops,
4923	},
4924	},
4925	};
4926
4927	static struct clk_branch gcc_usb30_prim_master_clk = {
4928	.halt_reg = 0x39018,
4929	.halt_check = BRANCH_HALT,
4930	.clkr = {
4931	.enable_reg = 0x39018,
4932	.enable_mask = BIT(0),
4933	.hw.init = &(const struct clk_init_data) {
4934	.name = "gcc_usb30_prim_master_clk",
4935	.parent_hws = (const struct clk_hw*[]) {
4936	&gcc_usb30_prim_master_clk_src.clkr.hw,
4937	},
4938	.num_parents = 1,
4939	.flags = CLK_SET_RATE_PARENT,
4940	.ops = &clk_branch2_ops,
4941	},
4942	},
4943	};
4944
4945	static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
4946	.halt_reg = 0x39028,
4947	.halt_check = BRANCH_HALT,
4948	.clkr = {
4949	.enable_reg = 0x39028,
4950	.enable_mask = BIT(0),
4951	.hw.init = &(const struct clk_init_data) {
4952	.name = "gcc_usb30_prim_mock_utmi_clk",
4953	.parent_hws = (const struct clk_hw*[]) {
4954	&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
4955	},
4956	.num_parents = 1,
4957	.flags = CLK_SET_RATE_PARENT,
4958	.ops = &clk_branch2_ops,
4959	},
4960	},
4961	};
4962
4963	static struct clk_branch gcc_usb30_prim_sleep_clk = {
4964	.halt_reg = 0x39024,
4965	.halt_check = BRANCH_HALT,
4966	.clkr = {
4967	.enable_reg = 0x39024,
4968	.enable_mask = BIT(0),
4969	.hw.init = &(const struct clk_init_data) {
4970	.name = "gcc_usb30_prim_sleep_clk",
4971	.ops = &clk_branch2_ops,
4972	},
4973	},
4974	};
4975
4976	static struct clk_branch gcc_usb30_sec_master_clk = {
4977	.halt_reg = 0xa1018,
4978	.halt_check = BRANCH_HALT,
4979	.clkr = {
4980	.enable_reg = 0xa1018,
4981	.enable_mask = BIT(0),
4982	.hw.init = &(const struct clk_init_data) {
4983	.name = "gcc_usb30_sec_master_clk",
4984	.parent_hws = (const struct clk_hw*[]) {
4985	&gcc_usb30_sec_master_clk_src.clkr.hw,
4986	},
4987	.num_parents = 1,
4988	.flags = CLK_SET_RATE_PARENT,
4989	.ops = &clk_branch2_ops,
4990	},
4991	},
4992	};
4993
4994	static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
4995	.halt_reg = 0xa1028,
4996	.halt_check = BRANCH_HALT,
4997	.clkr = {
4998	.enable_reg = 0xa1028,
4999	.enable_mask = BIT(0),
5000	.hw.init = &(const struct clk_init_data) {
5001	.name = "gcc_usb30_sec_mock_utmi_clk",
5002	.parent_hws = (const struct clk_hw*[]) {
5003	&gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw,
5004	},
5005	.num_parents = 1,
5006	.flags = CLK_SET_RATE_PARENT,
5007	.ops = &clk_branch2_ops,
5008	},
5009	},
5010	};
5011
5012	static struct clk_branch gcc_usb30_sec_sleep_clk = {
5013	.halt_reg = 0xa1024,
5014	.halt_check = BRANCH_HALT,
5015	.clkr = {
5016	.enable_reg = 0xa1024,
5017	.enable_mask = BIT(0),
5018	.hw.init = &(const struct clk_init_data) {
5019	.name = "gcc_usb30_sec_sleep_clk",
5020	.ops = &clk_branch2_ops,
5021	},
5022	},
5023	};
5024
5025	static struct clk_branch gcc_usb30_tert_master_clk = {
5026	.halt_reg = 0xa2018,
5027	.halt_check = BRANCH_HALT,
5028	.clkr = {
5029	.enable_reg = 0xa2018,
5030	.enable_mask = BIT(0),
5031	.hw.init = &(const struct clk_init_data) {
5032	.name = "gcc_usb30_tert_master_clk",
5033	.parent_hws = (const struct clk_hw*[]) {
5034	&gcc_usb30_tert_master_clk_src.clkr.hw,
5035	},
5036	.num_parents = 1,
5037	.flags = CLK_SET_RATE_PARENT,
5038	.ops = &clk_branch2_ops,
5039	},
5040	},
5041	};
5042
5043	static struct clk_branch gcc_usb30_tert_mock_utmi_clk = {
5044	.halt_reg = 0xa2028,
5045	.halt_check = BRANCH_HALT,
5046	.clkr = {
5047	.enable_reg = 0xa2028,
5048	.enable_mask = BIT(0),
5049	.hw.init = &(const struct clk_init_data) {
5050	.name = "gcc_usb30_tert_mock_utmi_clk",
5051	.parent_hws = (const struct clk_hw*[]) {
5052	&gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr.hw,
5053	},
5054	.num_parents = 1,
5055	.flags = CLK_SET_RATE_PARENT,
5056	.ops = &clk_branch2_ops,
5057	},
5058	},
5059	};
5060
5061	static struct clk_branch gcc_usb30_tert_sleep_clk = {
5062	.halt_reg = 0xa2024,
5063	.halt_check = BRANCH_HALT,
5064	.clkr = {
5065	.enable_reg = 0xa2024,
5066	.enable_mask = BIT(0),
5067	.hw.init = &(const struct clk_init_data) {
5068	.name = "gcc_usb30_tert_sleep_clk",
5069	.ops = &clk_branch2_ops,
5070	},
5071	},
5072	};
5073
5074	static struct clk_branch gcc_usb3_mp_phy_aux_clk = {
5075	.halt_reg = 0x17288,
5076	.halt_check = BRANCH_HALT,
5077	.clkr = {
5078	.enable_reg = 0x17288,
5079	.enable_mask = BIT(0),
5080	.hw.init = &(const struct clk_init_data) {
5081	.name = "gcc_usb3_mp_phy_aux_clk",
5082	.parent_hws = (const struct clk_hw*[]) {
5083	&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
5084	},
5085	.num_parents = 1,
5086	.flags = CLK_SET_RATE_PARENT,
5087	.ops = &clk_branch2_ops,
5088	},
5089	},
5090	};
5091
5092	static struct clk_branch gcc_usb3_mp_phy_com_aux_clk = {
5093	.halt_reg = 0x1728c,
5094	.halt_check = BRANCH_HALT,
5095	.clkr = {
5096	.enable_reg = 0x1728c,
5097	.enable_mask = BIT(0),
5098	.hw.init = &(const struct clk_init_data) {
5099	.name = "gcc_usb3_mp_phy_com_aux_clk",
5100	.parent_hws = (const struct clk_hw*[]) {
5101	&gcc_usb3_mp_phy_aux_clk_src.clkr.hw,
5102	},
5103	.num_parents = 1,
5104	.flags = CLK_SET_RATE_PARENT,
5105	.ops = &clk_branch2_ops,
5106	},
5107	},
5108	};
5109
5110	static struct clk_branch gcc_usb3_mp_phy_pipe_0_clk = {
5111	.halt_reg = 0x17290,
5112	.halt_check = BRANCH_HALT,
5113	.clkr = {
5114	.enable_reg = 0x17290,
5115	.enable_mask = BIT(0),
5116	.hw.init = &(const struct clk_init_data) {
5117	.name = "gcc_usb3_mp_phy_pipe_0_clk",
5118	.ops = &clk_branch2_ops,
5119	},
5120	},
5121	};
5122
5123	static struct clk_branch gcc_usb3_mp_phy_pipe_1_clk = {
5124	.halt_reg = 0x17298,
5125	.halt_check = BRANCH_HALT,
5126	.clkr = {
5127	.enable_reg = 0x17298,
5128	.enable_mask = BIT(0),
5129	.hw.init = &(const struct clk_init_data) {
5130	.name = "gcc_usb3_mp_phy_pipe_1_clk",
5131	.ops = &clk_branch2_ops,
5132	},
5133	},
5134	};
5135
5136	static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
5137	.halt_reg = 0x39060,
5138	.halt_check = BRANCH_HALT,
5139	.clkr = {
5140	.enable_reg = 0x39060,
5141	.enable_mask = BIT(0),
5142	.hw.init = &(const struct clk_init_data) {
5143	.name = "gcc_usb3_prim_phy_aux_clk",
5144	.parent_hws = (const struct clk_hw*[]) {
5145	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
5146	},
5147	.num_parents = 1,
5148	.flags = CLK_SET_RATE_PARENT,
5149	.ops = &clk_branch2_ops,
5150	},
5151	},
5152	};
5153
5154	static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
5155	.halt_reg = 0x39064,
5156	.halt_check = BRANCH_HALT,
5157	.clkr = {
5158	.enable_reg = 0x39064,
5159	.enable_mask = BIT(0),
5160	.hw.init = &(const struct clk_init_data) {
5161	.name = "gcc_usb3_prim_phy_com_aux_clk",
5162	.parent_hws = (const struct clk_hw*[]) {
5163	&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
5164	},
5165	.num_parents = 1,
5166	.flags = CLK_SET_RATE_PARENT,
5167	.ops = &clk_branch2_ops,
5168	},
5169	},
5170	};
5171
5172	static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
5173	.reg = 0x3906c,
5174	.shift = 0,
5175	.width = 2,
5176	.parent_map = gcc_parent_map_10,
5177	.clkr = {
5178	.hw.init = &(struct clk_init_data){
5179	.name = "gcc_usb3_prim_phy_pipe_clk_src",
5180	.parent_data = gcc_parent_data_10,
5181	.num_parents = ARRAY_SIZE(gcc_parent_data_10),
5182	.ops = &clk_regmap_mux_closest_ops,
5183	},
5184	},
5185	};
5186
5187	static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
5188	.halt_reg = 0x39068,
5189	.halt_check = BRANCH_HALT_VOTED,
5190	.hwcg_reg = 0x39068,
5191	.hwcg_bit = 1,
5192	.clkr = {
5193	.enable_reg = 0x39068,
5194	.enable_mask = BIT(0),
5195	.hw.init = &(const struct clk_init_data) {
5196	.name = "gcc_usb3_prim_phy_pipe_clk",
5197	.parent_hws = (const struct clk_hw*[]) {
5198	&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
5199	},
5200	.num_parents = 1,
5201	.flags = CLK_SET_RATE_PARENT,
5202	.ops = &clk_branch2_ops,
5203	},
5204	},
5205	};
5206
5207	static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
5208	.halt_reg = 0xa1060,
5209	.halt_check = BRANCH_HALT,
5210	.clkr = {
5211	.enable_reg = 0xa1060,
5212	.enable_mask = BIT(0),
5213	.hw.init = &(const struct clk_init_data) {
5214	.name = "gcc_usb3_sec_phy_aux_clk",
5215	.parent_hws = (const struct clk_hw*[]) {
5216	&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
5217	},
5218	.num_parents = 1,
5219	.flags = CLK_SET_RATE_PARENT,
5220	.ops = &clk_branch2_ops,
5221	},
5222	},
5223	};
5224
5225	static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
5226	.halt_reg = 0xa1064,
5227	.halt_check = BRANCH_HALT,
5228	.clkr = {
5229	.enable_reg = 0xa1064,
5230	.enable_mask = BIT(0),
5231	.hw.init = &(const struct clk_init_data) {
5232	.name = "gcc_usb3_sec_phy_com_aux_clk",
5233	.parent_hws = (const struct clk_hw*[]) {
5234	&gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
5235	},
5236	.num_parents = 1,
5237	.flags = CLK_SET_RATE_PARENT,
5238	.ops = &clk_branch2_ops,
5239	},
5240	},
5241	};
5242
5243	static struct clk_regmap_mux gcc_usb3_sec_phy_pipe_clk_src = {
5244	.reg = 0xa106c,
5245	.shift = 0,
5246	.width = 2,
5247	.parent_map = gcc_parent_map_11,
5248	.clkr = {
5249	.hw.init = &(struct clk_init_data){
5250	.name = "gcc_usb3_sec_phy_pipe_clk_src",
5251	.parent_data = gcc_parent_data_11,
5252	.num_parents = ARRAY_SIZE(gcc_parent_data_11),
5253	.ops = &clk_regmap_mux_closest_ops,
5254	},
5255	},
5256	};
5257
5258	static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
5259	.halt_reg = 0xa1068,
5260	.halt_check = BRANCH_HALT_VOTED,
5261	.hwcg_reg = 0xa1068,
5262	.hwcg_bit = 1,
5263	.clkr = {
5264	.enable_reg = 0xa1068,
5265	.enable_mask = BIT(0),
5266	.hw.init = &(const struct clk_init_data) {
5267	.name = "gcc_usb3_sec_phy_pipe_clk",
5268	.parent_hws = (const struct clk_hw*[]) {
5269	&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
5270	},
5271	.num_parents = 1,
5272	.ops = &clk_branch2_ops,
5273	},
5274	},
5275	};
5276
5277	static struct clk_branch gcc_usb3_tert_phy_aux_clk = {
5278	.halt_reg = 0xa2060,
5279	.halt_check = BRANCH_HALT,
5280	.clkr = {
5281	.enable_reg = 0xa2060,
5282	.enable_mask = BIT(0),
5283	.hw.init = &(const struct clk_init_data) {
5284	.name = "gcc_usb3_tert_phy_aux_clk",
5285	.parent_hws = (const struct clk_hw*[]) {
5286	&gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
5287	},
5288	.num_parents = 1,
5289	.flags = CLK_SET_RATE_PARENT,
5290	.ops = &clk_branch2_ops,
5291	},
5292	},
5293	};
5294
5295	static struct clk_branch gcc_usb3_tert_phy_com_aux_clk = {
5296	.halt_reg = 0xa2064,
5297	.halt_check = BRANCH_HALT,
5298	.clkr = {
5299	.enable_reg = 0xa2064,
5300	.enable_mask = BIT(0),
5301	.hw.init = &(const struct clk_init_data) {
5302	.name = "gcc_usb3_tert_phy_com_aux_clk",
5303	.parent_hws = (const struct clk_hw*[]) {
5304	&gcc_usb3_tert_phy_aux_clk_src.clkr.hw,
5305	},
5306	.num_parents = 1,
5307	.flags = CLK_SET_RATE_PARENT,
5308	.ops = &clk_branch2_ops,
5309	},
5310	},
5311	};
5312
5313	static struct clk_regmap_mux gcc_usb3_tert_phy_pipe_clk_src = {
5314	.reg = 0xa206c,
5315	.shift = 0,
5316	.width = 2,
5317	.parent_map = gcc_parent_map_12,
5318	.clkr = {
5319	.hw.init = &(struct clk_init_data){
5320	.name = "gcc_usb3_tert_phy_pipe_clk_src",
5321	.parent_data = gcc_parent_data_12,
5322	.num_parents = ARRAY_SIZE(gcc_parent_data_12),
5323	.ops = &clk_regmap_mux_closest_ops,
5324	},
5325	},
5326	};
5327
5328	static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
5329	.halt_reg = 0xa2068,
5330	.halt_check = BRANCH_HALT_VOTED,
5331	.hwcg_reg = 0xa2068,
5332	.hwcg_bit = 1,
5333	.clkr = {
5334	.enable_reg = 0xa2068,
5335	.enable_mask = BIT(0),
5336	.hw.init = &(const struct clk_init_data) {
5337	.name = "gcc_usb3_tert_phy_pipe_clk",
5338	.parent_hws = (const struct clk_hw*[]) {
5339	&gcc_usb3_tert_phy_pipe_clk_src.clkr.hw,
5340	},
5341	.num_parents = 1,
5342	.ops = &clk_branch2_ops,
5343	},
5344	},
5345	};
5346
5347	static struct clk_branch gcc_usb4_0_cfg_ahb_clk = {
5348	.halt_reg = 0x9f0a8,
5349	.halt_check = BRANCH_HALT_VOTED,
5350	.hwcg_reg = 0x9f0a8,
5351	.hwcg_bit = 1,
5352	.clkr = {
5353	.enable_reg = 0x9f0a8,
5354	.enable_mask = BIT(0),
5355	.hw.init = &(const struct clk_init_data) {
5356	.name = "gcc_usb4_0_cfg_ahb_clk",
5357	.ops = &clk_branch2_ops,
5358	},
5359	},
5360	};
5361
5362	static struct clk_branch gcc_usb4_0_dp0_clk = {
5363	.halt_reg = 0x9f060,
5364	.halt_check = BRANCH_HALT,
5365	.clkr = {
5366	.enable_reg = 0x9f060,
5367	.enable_mask = BIT(0),
5368	.hw.init = &(const struct clk_init_data) {
5369	.name = "gcc_usb4_0_dp0_clk",
5370	.ops = &clk_branch2_ops,
5371	},
5372	},
5373	};
5374
5375	static struct clk_branch gcc_usb4_0_dp1_clk = {
5376	.halt_reg = 0x9f108,
5377	.halt_check = BRANCH_HALT,
5378	.clkr = {
5379	.enable_reg = 0x9f108,
5380	.enable_mask = BIT(0),
5381	.hw.init = &(const struct clk_init_data) {
5382	.name = "gcc_usb4_0_dp1_clk",
5383	.ops = &clk_branch2_ops,
5384	},
5385	},
5386	};
5387
5388	static struct clk_branch gcc_usb4_0_master_clk = {
5389	.halt_reg = 0x9f018,
5390	.halt_check = BRANCH_HALT,
5391	.clkr = {
5392	.enable_reg = 0x9f018,
5393	.enable_mask = BIT(0),
5394	.hw.init = &(const struct clk_init_data) {
5395	.name = "gcc_usb4_0_master_clk",
5396	.parent_hws = (const struct clk_hw*[]) {
5397	&gcc_usb4_0_master_clk_src.clkr.hw,
5398	},
5399	.num_parents = 1,
5400	.flags = CLK_SET_RATE_PARENT,
5401	.ops = &clk_branch2_ops,
5402	},
5403	},
5404	};
5405
5406	static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
5407	.halt_reg = 0x9f0d8,
5408	.halt_check = BRANCH_HALT,
5409	.clkr = {
5410	.enable_reg = 0x9f0d8,
5411	.enable_mask = BIT(0),
5412	.hw.init = &(const struct clk_init_data) {
5413	.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk",
5414	.ops = &clk_branch2_ops,
5415	},
5416	},
5417	};
5418
5419	static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
5420	.halt_reg = 0x9f048,
5421	.halt_check = BRANCH_HALT_VOTED,
5422	.clkr = {
5423	.enable_reg = 0x52010,
5424	.enable_mask = BIT(19),
5425	.hw.init = &(const struct clk_init_data) {
5426	.name = "gcc_usb4_0_phy_pcie_pipe_clk",
5427	.ops = &clk_branch2_ops,
5428	},
5429	},
5430	};
5431
5432	static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
5433	.halt_reg = 0x9f0b0,
5434	.halt_check = BRANCH_HALT,
5435	.clkr = {
5436	.enable_reg = 0x9f0b0,
5437	.enable_mask = BIT(0),
5438	.hw.init = &(const struct clk_init_data) {
5439	.name = "gcc_usb4_0_phy_rx0_clk",
5440	.ops = &clk_branch2_ops,
5441	},
5442	},
5443	};
5444
5445	static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
5446	.halt_reg = 0x9f0c0,
5447	.halt_check = BRANCH_HALT,
5448	.clkr = {
5449	.enable_reg = 0x9f0c0,
5450	.enable_mask = BIT(0),
5451	.hw.init = &(const struct clk_init_data) {
5452	.name = "gcc_usb4_0_phy_rx1_clk",
5453	.ops = &clk_branch2_ops,
5454	},
5455	},
5456	};
5457
5458	static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {
5459	.halt_reg = 0x9f0a4,
5460	.halt_check = BRANCH_HALT_VOTED,
5461	.hwcg_reg = 0x9f0a4,
5462	.hwcg_bit = 1,
5463	.clkr = {
5464	.enable_reg = 0x9f0a4,
5465	.enable_mask = BIT(0),
5466	.hw.init = &(const struct clk_init_data) {
5467	.name = "gcc_usb4_0_phy_usb_pipe_clk",
5468	.ops = &clk_branch2_ops,
5469	},
5470	},
5471	};
5472
5473	static struct clk_branch gcc_usb4_0_sb_if_clk = {
5474	.halt_reg = 0x9f044,
5475	.halt_check = BRANCH_HALT,
5476	.clkr = {
5477	.enable_reg = 0x9f044,
5478	.enable_mask = BIT(0),
5479	.hw.init = &(const struct clk_init_data) {
5480	.name = "gcc_usb4_0_sb_if_clk",
5481	.parent_hws = (const struct clk_hw*[]) {
5482	&gcc_usb4_0_sb_if_clk_src.clkr.hw,
5483	},
5484	.num_parents = 1,
5485	.flags = CLK_SET_RATE_PARENT,
5486	.ops = &clk_branch2_ops,
5487	},
5488	},
5489	};
5490
5491	static struct clk_branch gcc_usb4_0_sys_clk = {
5492	.halt_reg = 0x9f054,
5493	.halt_check = BRANCH_HALT,
5494	.clkr = {
5495	.enable_reg = 0x9f054,
5496	.enable_mask = BIT(0),
5497	.hw.init = &(const struct clk_init_data) {
5498	.name = "gcc_usb4_0_sys_clk",
5499	.ops = &clk_branch2_ops,
5500	},
5501	},
5502	};
5503
5504	static struct clk_branch gcc_usb4_0_tmu_clk = {
5505	.halt_reg = 0x9f088,
5506	.halt_check = BRANCH_HALT_VOTED,
5507	.hwcg_reg = 0x9f088,
5508	.hwcg_bit = 1,
5509	.clkr = {
5510	.enable_reg = 0x9f088,
5511	.enable_mask = BIT(0),
5512	.hw.init = &(const struct clk_init_data) {
5513	.name = "gcc_usb4_0_tmu_clk",
5514	.parent_hws = (const struct clk_hw*[]) {
5515	&gcc_usb4_0_tmu_clk_src.clkr.hw,
5516	},
5517	.num_parents = 1,
5518	.flags = CLK_SET_RATE_PARENT,
5519	.ops = &clk_branch2_ops,
5520	},
5521	},
5522	};
5523
5524	static struct clk_branch gcc_usb4_1_cfg_ahb_clk = {
5525	.halt_reg = 0x2b0a8,
5526	.halt_check = BRANCH_HALT_VOTED,
5527	.hwcg_reg = 0x2b0a8,
5528	.hwcg_bit = 1,
5529	.clkr = {
5530	.enable_reg = 0x2b0a8,
5531	.enable_mask = BIT(0),
5532	.hw.init = &(const struct clk_init_data) {
5533	.name = "gcc_usb4_1_cfg_ahb_clk",
5534	.ops = &clk_branch2_ops,
5535	},
5536	},
5537	};
5538
5539	static struct clk_branch gcc_usb4_1_dp0_clk = {
5540	.halt_reg = 0x2b060,
5541	.halt_check = BRANCH_HALT,
5542	.clkr = {
5543	.enable_reg = 0x2b060,
5544	.enable_mask = BIT(0),
5545	.hw.init = &(const struct clk_init_data) {
5546	.name = "gcc_usb4_1_dp0_clk",
5547	.ops = &clk_branch2_ops,
5548	},
5549	},
5550	};
5551
5552	static struct clk_branch gcc_usb4_1_dp1_clk = {
5553	.halt_reg = 0x2b108,
5554	.halt_check = BRANCH_HALT,
5555	.clkr = {
5556	.enable_reg = 0x2b108,
5557	.enable_mask = BIT(0),
5558	.hw.init = &(const struct clk_init_data) {
5559	.name = "gcc_usb4_1_dp1_clk",
5560	.ops = &clk_branch2_ops,
5561	},
5562	},
5563	};
5564
5565	static struct clk_branch gcc_usb4_1_master_clk = {
5566	.halt_reg = 0x2b018,
5567	.halt_check = BRANCH_HALT,
5568	.clkr = {
5569	.enable_reg = 0x2b018,
5570	.enable_mask = BIT(0),
5571	.hw.init = &(const struct clk_init_data) {
5572	.name = "gcc_usb4_1_master_clk",
5573	.parent_hws = (const struct clk_hw*[]) {
5574	&gcc_usb4_1_master_clk_src.clkr.hw,
5575	},
5576	.num_parents = 1,
5577	.flags = CLK_SET_RATE_PARENT,
5578	.ops = &clk_branch2_ops,
5579	},
5580	},
5581	};
5582
5583	static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
5584	.halt_reg = 0x2b0d8,
5585	.halt_check = BRANCH_HALT,
5586	.clkr = {
5587	.enable_reg = 0x2b0d8,
5588	.enable_mask = BIT(0),
5589	.hw.init = &(const struct clk_init_data) {
5590	.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
5591	.ops = &clk_branch2_ops,
5592	},
5593	},
5594	};
5595
5596	static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
5597	.halt_reg = 0x2b048,
5598	.halt_check = BRANCH_HALT_VOTED,
5599	.clkr = {
5600	.enable_reg = 0x52028,
5601	.enable_mask = BIT(0),
5602	.hw.init = &(const struct clk_init_data) {
5603	.name = "gcc_usb4_1_phy_pcie_pipe_clk",
5604	.ops = &clk_branch2_ops,
5605	},
5606	},
5607	};
5608
5609	static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
5610	.halt_reg = 0x2b0b0,
5611	.halt_check = BRANCH_HALT,
5612	.clkr = {
5613	.enable_reg = 0x2b0b0,
5614	.enable_mask = BIT(0),
5615	.hw.init = &(const struct clk_init_data) {
5616	.name = "gcc_usb4_1_phy_rx0_clk",
5617	.ops = &clk_branch2_ops,
5618	},
5619	},
5620	};
5621
5622	static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
5623	.halt_reg = 0x2b0c0,
5624	.halt_check = BRANCH_HALT,
5625	.clkr = {
5626	.enable_reg = 0x2b0c0,
5627	.enable_mask = BIT(0),
5628	.hw.init = &(const struct clk_init_data) {
5629	.name = "gcc_usb4_1_phy_rx1_clk",
5630	.ops = &clk_branch2_ops,
5631	},
5632	},
5633	};
5634
5635	static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
5636	.halt_reg = 0x2b0a4,
5637	.halt_check = BRANCH_HALT_VOTED,
5638	.hwcg_reg = 0x2b0a4,
5639	.hwcg_bit = 1,
5640	.clkr = {
5641	.enable_reg = 0x2b0a4,
5642	.enable_mask = BIT(0),
5643	.hw.init = &(const struct clk_init_data) {
5644	.name = "gcc_usb4_1_phy_usb_pipe_clk",
5645	.ops = &clk_branch2_ops,
5646	},
5647	},
5648	};
5649
5650	static struct clk_branch gcc_usb4_1_sb_if_clk = {
5651	.halt_reg = 0x2b044,
5652	.halt_check = BRANCH_HALT,
5653	.clkr = {
5654	.enable_reg = 0x2b044,
5655	.enable_mask = BIT(0),
5656	.hw.init = &(const struct clk_init_data) {
5657	.name = "gcc_usb4_1_sb_if_clk",
5658	.parent_hws = (const struct clk_hw*[]) {
5659	&gcc_usb4_1_sb_if_clk_src.clkr.hw,
5660	},
5661	.num_parents = 1,
5662	.flags = CLK_SET_RATE_PARENT,
5663	.ops = &clk_branch2_ops,
5664	},
5665	},
5666	};
5667
5668	static struct clk_branch gcc_usb4_1_sys_clk = {
5669	.halt_reg = 0x2b054,
5670	.halt_check = BRANCH_HALT,
5671	.clkr = {
5672	.enable_reg = 0x2b054,
5673	.enable_mask = BIT(0),
5674	.hw.init = &(const struct clk_init_data) {
5675	.name = "gcc_usb4_1_sys_clk",
5676	.ops = &clk_branch2_ops,
5677	},
5678	},
5679	};
5680
5681	static struct clk_branch gcc_usb4_1_tmu_clk = {
5682	.halt_reg = 0x2b088,
5683	.halt_check = BRANCH_HALT_VOTED,
5684	.hwcg_reg = 0x2b088,
5685	.hwcg_bit = 1,
5686	.clkr = {
5687	.enable_reg = 0x2b088,
5688	.enable_mask = BIT(0),
5689	.hw.init = &(const struct clk_init_data) {
5690	.name = "gcc_usb4_1_tmu_clk",
5691	.parent_hws = (const struct clk_hw*[]) {
5692	&gcc_usb4_1_tmu_clk_src.clkr.hw,
5693	},
5694	.num_parents = 1,
5695	.flags = CLK_SET_RATE_PARENT,
5696	.ops = &clk_branch2_ops,
5697	},
5698	},
5699	};
5700
5701	static struct clk_branch gcc_usb4_2_cfg_ahb_clk = {
5702	.halt_reg = 0x110a8,
5703	.halt_check = BRANCH_HALT_VOTED,
5704	.hwcg_reg = 0x110a8,
5705	.hwcg_bit = 1,
5706	.clkr = {
5707	.enable_reg = 0x110a8,
5708	.enable_mask = BIT(0),
5709	.hw.init = &(const struct clk_init_data) {
5710	.name = "gcc_usb4_2_cfg_ahb_clk",
5711	.ops = &clk_branch2_ops,
5712	},
5713	},
5714	};
5715
5716	static struct clk_branch gcc_usb4_2_dp0_clk = {
5717	.halt_reg = 0x11060,
5718	.halt_check = BRANCH_HALT,
5719	.clkr = {
5720	.enable_reg = 0x11060,
5721	.enable_mask = BIT(0),
5722	.hw.init = &(const struct clk_init_data) {
5723	.name = "gcc_usb4_2_dp0_clk",
5724	.ops = &clk_branch2_ops,
5725	},
5726	},
5727	};
5728
5729	static struct clk_branch gcc_usb4_2_dp1_clk = {
5730	.halt_reg = 0x11108,
5731	.halt_check = BRANCH_HALT,
5732	.clkr = {
5733	.enable_reg = 0x11108,
5734	.enable_mask = BIT(0),
5735	.hw.init = &(const struct clk_init_data) {
5736	.name = "gcc_usb4_2_dp1_clk",
5737	.ops = &clk_branch2_ops,
5738	},
5739	},
5740	};
5741
5742	static struct clk_branch gcc_usb4_2_master_clk = {
5743	.halt_reg = 0x11018,
5744	.halt_check = BRANCH_HALT,
5745	.clkr = {
5746	.enable_reg = 0x11018,
5747	.enable_mask = BIT(0),
5748	.hw.init = &(const struct clk_init_data) {
5749	.name = "gcc_usb4_2_master_clk",
5750	.parent_hws = (const struct clk_hw*[]) {
5751	&gcc_usb4_2_master_clk_src.clkr.hw,
5752	},
5753	.num_parents = 1,
5754	.flags = CLK_SET_RATE_PARENT,
5755	.ops = &clk_branch2_ops,
5756	},
5757	},
5758	};
5759
5760	static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
5761	.halt_reg = 0x110d8,
5762	.halt_check = BRANCH_HALT,
5763	.clkr = {
5764	.enable_reg = 0x110d8,
5765	.enable_mask = BIT(0),
5766	.hw.init = &(const struct clk_init_data) {
5767	.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk",
5768	.ops = &clk_branch2_ops,
5769	},
5770	},
5771	};
5772
5773	static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
5774	.halt_reg = 0x11048,
5775	.halt_check = BRANCH_HALT_VOTED,
5776	.clkr = {
5777	.enable_reg = 0x52028,
5778	.enable_mask = BIT(1),
5779	.hw.init = &(const struct clk_init_data) {
5780	.name = "gcc_usb4_2_phy_pcie_pipe_clk",
5781	.ops = &clk_branch2_ops,
5782	},
5783	},
5784	};
5785
5786	static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
5787	.halt_reg = 0x110b0,
5788	.halt_check = BRANCH_HALT,
5789	.clkr = {
5790	.enable_reg = 0x110b0,
5791	.enable_mask = BIT(0),
5792	.hw.init = &(const struct clk_init_data) {
5793	.name = "gcc_usb4_2_phy_rx0_clk",
5794	.ops = &clk_branch2_ops,
5795	},
5796	},
5797	};
5798
5799	static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
5800	.halt_reg = 0x110c0,
5801	.halt_check = BRANCH_HALT,
5802	.clkr = {
5803	.enable_reg = 0x110c0,
5804	.enable_mask = BIT(0),
5805	.hw.init = &(const struct clk_init_data) {
5806	.name = "gcc_usb4_2_phy_rx1_clk",
5807	.ops = &clk_branch2_ops,
5808	},
5809	},
5810	};
5811
5812	static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {
5813	.halt_reg = 0x110a4,
5814	.halt_check = BRANCH_HALT_VOTED,
5815	.hwcg_reg = 0x110a4,
5816	.hwcg_bit = 1,
5817	.clkr = {
5818	.enable_reg = 0x110a4,
5819	.enable_mask = BIT(0),
5820	.hw.init = &(const struct clk_init_data) {
5821	.name = "gcc_usb4_2_phy_usb_pipe_clk",
5822	.ops = &clk_branch2_ops,
5823	},
5824	},
5825	};
5826
5827	static struct clk_branch gcc_usb4_2_sb_if_clk = {
5828	.halt_reg = 0x11044,
5829	.halt_check = BRANCH_HALT,
5830	.clkr = {
5831	.enable_reg = 0x11044,
5832	.enable_mask = BIT(0),
5833	.hw.init = &(const struct clk_init_data) {
5834	.name = "gcc_usb4_2_sb_if_clk",
5835	.parent_hws = (const struct clk_hw*[]) {
5836	&gcc_usb4_2_sb_if_clk_src.clkr.hw,
5837	},
5838	.num_parents = 1,
5839	.flags = CLK_SET_RATE_PARENT,
5840	.ops = &clk_branch2_ops,
5841	},
5842	},
5843	};
5844
5845	static struct clk_branch gcc_usb4_2_sys_clk = {
5846	.halt_reg = 0x11054,
5847	.halt_check = BRANCH_HALT,
5848	.clkr = {
5849	.enable_reg = 0x11054,
5850	.enable_mask = BIT(0),
5851	.hw.init = &(const struct clk_init_data) {
5852	.name = "gcc_usb4_2_sys_clk",
5853	.ops = &clk_branch2_ops,
5854	},
5855	},
5856	};
5857
5858	static struct clk_branch gcc_usb4_2_tmu_clk = {
5859	.halt_reg = 0x11088,
5860	.halt_check = BRANCH_HALT_VOTED,
5861	.hwcg_reg = 0x11088,
5862	.hwcg_bit = 1,
5863	.clkr = {
5864	.enable_reg = 0x11088,
5865	.enable_mask = BIT(0),
5866	.hw.init = &(const struct clk_init_data) {
5867	.name = "gcc_usb4_2_tmu_clk",
5868	.parent_hws = (const struct clk_hw*[]) {
5869	&gcc_usb4_2_tmu_clk_src.clkr.hw,
5870	},
5871	.num_parents = 1,
5872	.flags = CLK_SET_RATE_PARENT,
5873	.ops = &clk_branch2_ops,
5874	},
5875	},
5876	};
5877
5878	static struct clk_branch gcc_video_axi0_clk = {
5879	.halt_reg = 0x32018,
5880	.halt_check = BRANCH_HALT_SKIP,
5881	.hwcg_reg = 0x32018,
5882	.hwcg_bit = 1,
5883	.clkr = {
5884	.enable_reg = 0x32018,
5885	.enable_mask = BIT(0),
5886	.hw.init = &(const struct clk_init_data) {
5887	.name = "gcc_video_axi0_clk",
5888	.ops = &clk_branch2_ops,
5889	},
5890	},
5891	};
5892
5893	static struct clk_branch gcc_video_axi1_clk = {
5894	.halt_reg = 0x32024,
5895	.halt_check = BRANCH_HALT_SKIP,
5896	.hwcg_reg = 0x32024,
5897	.hwcg_bit = 1,
5898	.clkr = {
5899	.enable_reg = 0x32024,
5900	.enable_mask = BIT(0),
5901	.hw.init = &(const struct clk_init_data) {
5902	.name = "gcc_video_axi1_clk",
5903	.ops = &clk_branch2_ops,
5904	},
5905	},
5906	};
5907
5908	static struct gdsc gcc_pcie_0_tunnel_gdsc = {
5909	.gdscr = 0xa0004,
5910	.en_rest_wait_val = 0x2,
5911	.en_few_wait_val = 0x2,
5912	.clk_dis_wait_val = 0xf,
5913	.pd = {
5914	.name = "gcc_pcie_0_tunnel_gdsc",
5915	},
5916	.pwrsts = PWRSTS_OFF_ON,
5917	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
5918	};
5919
5920	static struct gdsc gcc_pcie_1_tunnel_gdsc = {
5921	.gdscr = 0x2c004,
5922	.en_rest_wait_val = 0x2,
5923	.en_few_wait_val = 0x2,
5924	.clk_dis_wait_val = 0xf,
5925	.pd = {
5926	.name = "gcc_pcie_1_tunnel_gdsc",
5927	},
5928	.pwrsts = PWRSTS_OFF_ON,
5929	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
5930	};
5931
5932	static struct gdsc gcc_pcie_2_tunnel_gdsc = {
5933	.gdscr = 0x13004,
5934	.en_rest_wait_val = 0x2,
5935	.en_few_wait_val = 0x2,
5936	.clk_dis_wait_val = 0xf,
5937	.pd = {
5938	.name = "gcc_pcie_2_tunnel_gdsc",
5939	},
5940	.pwrsts = PWRSTS_OFF_ON,
5941	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
5942	};
5943
5944	static struct gdsc gcc_pcie_3_gdsc = {
5945	.gdscr = 0x58004,
5946	.en_rest_wait_val = 0x2,
5947	.en_few_wait_val = 0x2,
5948	.clk_dis_wait_val = 0xf,
5949	.pd = {
5950	.name = "gcc_pcie_3_gdsc",
5951	},
5952	.pwrsts = PWRSTS_OFF_ON,
5953	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
5954	};
5955
5956	static struct gdsc gcc_pcie_3_phy_gdsc = {
5957	.gdscr = 0x3e000,
5958	.en_rest_wait_val = 0x2,
5959	.en_few_wait_val = 0x2,
5960	.clk_dis_wait_val = 0x2,
5961	.pd = {
5962	.name = "gcc_pcie_3_phy_gdsc",
5963	},
5964	.pwrsts = PWRSTS_OFF_ON,
5965	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
5966	};
5967
5968	static struct gdsc gcc_pcie_4_gdsc = {
5969	.gdscr = 0x6b004,
5970	.en_rest_wait_val = 0x2,
5971	.en_few_wait_val = 0x2,
5972	.clk_dis_wait_val = 0xf,
5973	.pd = {
5974	.name = "gcc_pcie_4_gdsc",
5975	},
5976	.pwrsts = PWRSTS_OFF_ON,
5977	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
5978	};
5979
5980	static struct gdsc gcc_pcie_4_phy_gdsc = {
5981	.gdscr = 0x6c000,
5982	.en_rest_wait_val = 0x2,
5983	.en_few_wait_val = 0x2,
5984	.clk_dis_wait_val = 0x2,
5985	.pd = {
5986	.name = "gcc_pcie_4_phy_gdsc",
5987	},
5988	.pwrsts = PWRSTS_OFF_ON,
5989	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
5990	};
5991
5992	static struct gdsc gcc_pcie_5_gdsc = {
5993	.gdscr = 0x2f004,
5994	.en_rest_wait_val = 0x2,
5995	.en_few_wait_val = 0x2,
5996	.clk_dis_wait_val = 0xf,
5997	.pd = {
5998	.name = "gcc_pcie_5_gdsc",
5999	},
6000	.pwrsts = PWRSTS_OFF_ON,
6001	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6002	};
6003
6004	static struct gdsc gcc_pcie_5_phy_gdsc = {
6005	.gdscr = 0x30000,
6006	.en_rest_wait_val = 0x2,
6007	.en_few_wait_val = 0x2,
6008	.clk_dis_wait_val = 0x2,
6009	.pd = {
6010	.name = "gcc_pcie_5_phy_gdsc",
6011	},
6012	.pwrsts = PWRSTS_OFF_ON,
6013	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6014	};
6015
6016	static struct gdsc gcc_pcie_6_phy_gdsc = {
6017	.gdscr = 0x8e000,
6018	.en_rest_wait_val = 0x2,
6019	.en_few_wait_val = 0x2,
6020	.clk_dis_wait_val = 0x2,
6021	.pd = {
6022	.name = "gcc_pcie_6_phy_gdsc",
6023	},
6024	.pwrsts = PWRSTS_OFF_ON,
6025	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6026	};
6027
6028	static struct gdsc gcc_pcie_6a_gdsc = {
6029	.gdscr = 0x31004,
6030	.en_rest_wait_val = 0x2,
6031	.en_few_wait_val = 0x2,
6032	.clk_dis_wait_val = 0xf,
6033	.pd = {
6034	.name = "gcc_pcie_6a_gdsc",
6035	},
6036	.pwrsts = PWRSTS_OFF_ON,
6037	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6038	};
6039
6040	static struct gdsc gcc_pcie_6b_gdsc = {
6041	.gdscr = 0x8d004,
6042	.en_rest_wait_val = 0x2,
6043	.en_few_wait_val = 0x2,
6044	.clk_dis_wait_val = 0xf,
6045	.pd = {
6046	.name = "gcc_pcie_6b_gdsc",
6047	},
6048	.pwrsts = PWRSTS_OFF_ON,
6049	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
6050	};
6051
6052	static struct gdsc gcc_ufs_mem_phy_gdsc = {
6053	.gdscr = 0x9e000,
6054	.en_rest_wait_val = 0x2,
6055	.en_few_wait_val = 0x2,
6056	.clk_dis_wait_val = 0x2,
6057	.pd = {
6058	.name = "gcc_ufs_mem_phy_gdsc",
6059	},
6060	.pwrsts = PWRSTS_OFF_ON,
6061	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6062	};
6063
6064	static struct gdsc gcc_ufs_phy_gdsc = {
6065	.gdscr = 0x77004,
6066	.en_rest_wait_val = 0x2,
6067	.en_few_wait_val = 0x2,
6068	.clk_dis_wait_val = 0xf,
6069	.pd = {
6070	.name = "gcc_ufs_phy_gdsc",
6071	},
6072	.pwrsts = PWRSTS_OFF_ON,
6073	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6074	};
6075
6076	static struct gdsc gcc_usb20_prim_gdsc = {
6077	.gdscr = 0x29004,
6078	.en_rest_wait_val = 0x2,
6079	.en_few_wait_val = 0x2,
6080	.clk_dis_wait_val = 0xf,
6081	.pd = {
6082	.name = "gcc_usb20_prim_gdsc",
6083	},
6084	.pwrsts = PWRSTS_OFF_ON,
6085	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6086	};
6087
6088	static struct gdsc gcc_usb30_mp_gdsc = {
6089	.gdscr = 0x17004,
6090	.en_rest_wait_val = 0x2,
6091	.en_few_wait_val = 0x2,
6092	.clk_dis_wait_val = 0xf,
6093	.pd = {
6094	.name = "gcc_usb30_mp_gdsc",
6095	},
6096	.pwrsts = PWRSTS_RET_ON,
6097	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6098	};
6099
6100	static struct gdsc gcc_usb30_prim_gdsc = {
6101	.gdscr = 0x39004,
6102	.en_rest_wait_val = 0x2,
6103	.en_few_wait_val = 0x2,
6104	.clk_dis_wait_val = 0xf,
6105	.pd = {
6106	.name = "gcc_usb30_prim_gdsc",
6107	},
6108	.pwrsts = PWRSTS_RET_ON,
6109	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6110	};
6111
6112	static struct gdsc gcc_usb30_sec_gdsc = {
6113	.gdscr = 0xa1004,
6114	.en_rest_wait_val = 0x2,
6115	.en_few_wait_val = 0x2,
6116	.clk_dis_wait_val = 0xf,
6117	.pd = {
6118	.name = "gcc_usb30_sec_gdsc",
6119	},
6120	.pwrsts = PWRSTS_RET_ON,
6121	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6122	};
6123
6124	static struct gdsc gcc_usb30_tert_gdsc = {
6125	.gdscr = 0xa2004,
6126	.en_rest_wait_val = 0x2,
6127	.en_few_wait_val = 0x2,
6128	.clk_dis_wait_val = 0xf,
6129	.pd = {
6130	.name = "gcc_usb30_tert_gdsc",
6131	},
6132	.pwrsts = PWRSTS_RET_ON,
6133	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6134	};
6135
6136	static struct gdsc gcc_usb3_mp_ss0_phy_gdsc = {
6137	.gdscr = 0x1900c,
6138	.en_rest_wait_val = 0x2,
6139	.en_few_wait_val = 0x2,
6140	.clk_dis_wait_val = 0x2,
6141	.pd = {
6142	.name = "gcc_usb3_mp_ss0_phy_gdsc",
6143	},
6144	.pwrsts = PWRSTS_RET_ON,
6145	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6146	};
6147
6148	static struct gdsc gcc_usb3_mp_ss1_phy_gdsc = {
6149	.gdscr = 0x5400c,
6150	.en_rest_wait_val = 0x2,
6151	.en_few_wait_val = 0x2,
6152	.clk_dis_wait_val = 0x2,
6153	.pd = {
6154	.name = "gcc_usb3_mp_ss1_phy_gdsc",
6155	},
6156	.pwrsts = PWRSTS_OFF_ON,
6157	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6158	};
6159
6160	static struct gdsc gcc_usb4_0_gdsc = {
6161	.gdscr = 0x9f004,
6162	.en_rest_wait_val = 0x2,
6163	.en_few_wait_val = 0x2,
6164	.clk_dis_wait_val = 0xf,
6165	.pd = {
6166	.name = "gcc_usb4_0_gdsc",
6167	},
6168	.pwrsts = PWRSTS_OFF_ON,
6169	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6170	};
6171
6172	static struct gdsc gcc_usb4_1_gdsc = {
6173	.gdscr = 0x2b004,
6174	.en_rest_wait_val = 0x2,
6175	.en_few_wait_val = 0x2,
6176	.clk_dis_wait_val = 0xf,
6177	.pd = {
6178	.name = "gcc_usb4_1_gdsc",
6179	},
6180	.pwrsts = PWRSTS_OFF_ON,
6181	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6182	};
6183
6184	static struct gdsc gcc_usb4_2_gdsc = {
6185	.gdscr = 0x11004,
6186	.en_rest_wait_val = 0x2,
6187	.en_few_wait_val = 0x2,
6188	.clk_dis_wait_val = 0xf,
6189	.pd = {
6190	.name = "gcc_usb4_2_gdsc",
6191	},
6192	.pwrsts = PWRSTS_OFF_ON,
6193	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6194	};
6195
6196	static struct gdsc gcc_usb_0_phy_gdsc = {
6197	.gdscr = 0x50024,
6198	.en_rest_wait_val = 0x2,
6199	.en_few_wait_val = 0x2,
6200	.clk_dis_wait_val = 0x2,
6201	.pd = {
6202	.name = "gcc_usb_0_phy_gdsc",
6203	},
6204	.pwrsts = PWRSTS_OFF_ON,
6205	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6206	};
6207
6208	static struct gdsc gcc_usb_1_phy_gdsc = {
6209	.gdscr = 0x2a024,
6210	.en_rest_wait_val = 0x2,
6211	.en_few_wait_val = 0x2,
6212	.clk_dis_wait_val = 0x2,
6213	.pd = {
6214	.name = "gcc_usb_1_phy_gdsc",
6215	},
6216	.pwrsts = PWRSTS_OFF_ON,
6217	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6218	};
6219
6220	static struct gdsc gcc_usb_2_phy_gdsc = {
6221	.gdscr = 0xa3024,
6222	.en_rest_wait_val = 0x2,
6223	.en_few_wait_val = 0x2,
6224	.clk_dis_wait_val = 0x2,
6225	.pd = {
6226	.name = "gcc_usb_2_phy_gdsc",
6227	},
6228	.pwrsts = PWRSTS_RET_ON,
6229	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
6230	};
6231
6232	static struct clk_regmap *gcc_x1e80100_clocks[] = {
6233	[GCC_AGGRE_NOC_USB_NORTH_AXI_CLK] = &gcc_aggre_noc_usb_north_axi_clk.clkr,
6234	[GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK] = &gcc_aggre_noc_usb_south_axi_clk.clkr,
6235	[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
6236	[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
6237	[GCC_AGGRE_USB3_MP_AXI_CLK] = &gcc_aggre_usb3_mp_axi_clk.clkr,
6238	[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
6239	[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
6240	[GCC_AGGRE_USB3_TERT_AXI_CLK] = &gcc_aggre_usb3_tert_axi_clk.clkr,
6241	[GCC_AGGRE_USB4_0_AXI_CLK] = &gcc_aggre_usb4_0_axi_clk.clkr,
6242	[GCC_AGGRE_USB4_1_AXI_CLK] = &gcc_aggre_usb4_1_axi_clk.clkr,
6243	[GCC_AGGRE_USB4_2_AXI_CLK] = &gcc_aggre_usb4_2_axi_clk.clkr,
6244	[GCC_AGGRE_USB_NOC_AXI_CLK] = &gcc_aggre_usb_noc_axi_clk.clkr,
6245	[GCC_AV1E_AHB_CLK] = &gcc_av1e_ahb_clk.clkr,
6246	[GCC_AV1E_AXI_CLK] = &gcc_av1e_axi_clk.clkr,
6247	[GCC_AV1E_XO_CLK] = &gcc_av1e_xo_clk.clkr,
6248	[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
6249	[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
6250	[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
6251	[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
6252	[GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_north_ahb_clk.clkr,
6253	[GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_south_ahb_clk.clkr,
6254	[GCC_CFG_NOC_USB2_PRIM_AXI_CLK] = &gcc_cfg_noc_usb2_prim_axi_clk.clkr,
6255	[GCC_CFG_NOC_USB3_MP_AXI_CLK] = &gcc_cfg_noc_usb3_mp_axi_clk.clkr,
6256	[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
6257	[GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
6258	[GCC_CFG_NOC_USB3_TERT_AXI_CLK] = &gcc_cfg_noc_usb3_tert_axi_clk.clkr,
6259	[GCC_CFG_NOC_USB_ANOC_AHB_CLK] = &gcc_cfg_noc_usb_anoc_ahb_clk.clkr,
6260	[GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_north_ahb_clk.clkr,
6261	[GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK] = &gcc_cfg_noc_usb_anoc_south_ahb_clk.clkr,
6262	[GCC_CNOC_PCIE1_TUNNEL_CLK] = &gcc_cnoc_pcie1_tunnel_clk.clkr,
6263	[GCC_CNOC_PCIE2_TUNNEL_CLK] = &gcc_cnoc_pcie2_tunnel_clk.clkr,
6264	[GCC_CNOC_PCIE_NORTH_SF_AXI_CLK] = &gcc_cnoc_pcie_north_sf_axi_clk.clkr,
6265	[GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK] = &gcc_cnoc_pcie_south_sf_axi_clk.clkr,
6266	[GCC_CNOC_PCIE_TUNNEL_CLK] = &gcc_cnoc_pcie_tunnel_clk.clkr,
6267	[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
6268	[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
6269	[GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
6270	[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
6271	[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
6272	[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
6273	[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
6274	[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
6275	[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
6276	[GCC_GPLL0] = &gcc_gpll0.clkr,
6277	[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
6278	[GCC_GPLL4] = &gcc_gpll4.clkr,
6279	[GCC_GPLL7] = &gcc_gpll7.clkr,
6280	[GCC_GPLL8] = &gcc_gpll8.clkr,
6281	[GCC_GPLL9] = &gcc_gpll9.clkr,
6282	[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
6283	[GCC_GPU_GPLL0_CPH_CLK_SRC] = &gcc_gpu_gpll0_cph_clk_src.clkr,
6284	[GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &gcc_gpu_gpll0_div_cph_clk_src.clkr,
6285	[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
6286	[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
6287	[GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr,
6288	[GCC_PCIE1_PHY_RCHNG_CLK] = &gcc_pcie1_phy_rchng_clk.clkr,
6289	[GCC_PCIE2_PHY_RCHNG_CLK] = &gcc_pcie2_phy_rchng_clk.clkr,
6290	[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
6291	[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
6292	[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
6293	[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
6294	[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
6295	[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
6296	[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
6297	[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
6298	[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
6299	[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
6300	[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
6301	[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
6302	[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
6303	[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
6304	[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
6305	[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
6306	[GCC_PCIE_2_AUX_CLK] = &gcc_pcie_2_aux_clk.clkr,
6307	[GCC_PCIE_2_AUX_CLK_SRC] = &gcc_pcie_2_aux_clk_src.clkr,
6308	[GCC_PCIE_2_CFG_AHB_CLK] = &gcc_pcie_2_cfg_ahb_clk.clkr,
6309	[GCC_PCIE_2_MSTR_AXI_CLK] = &gcc_pcie_2_mstr_axi_clk.clkr,
6310	[GCC_PCIE_2_PHY_RCHNG_CLK_SRC] = &gcc_pcie_2_phy_rchng_clk_src.clkr,
6311	[GCC_PCIE_2_PIPE_CLK] = &gcc_pcie_2_pipe_clk.clkr,
6312	[GCC_PCIE_2_SLV_AXI_CLK] = &gcc_pcie_2_slv_axi_clk.clkr,
6313	[GCC_PCIE_2_SLV_Q2A_AXI_CLK] = &gcc_pcie_2_slv_q2a_axi_clk.clkr,
6314	[GCC_PCIE_3_AUX_CLK] = &gcc_pcie_3_aux_clk.clkr,
6315	[GCC_PCIE_3_AUX_CLK_SRC] = &gcc_pcie_3_aux_clk_src.clkr,
6316	[GCC_PCIE_3_CFG_AHB_CLK] = &gcc_pcie_3_cfg_ahb_clk.clkr,
6317	[GCC_PCIE_3_MSTR_AXI_CLK] = &gcc_pcie_3_mstr_axi_clk.clkr,
6318	[GCC_PCIE_3_PHY_AUX_CLK] = &gcc_pcie_3_phy_aux_clk.clkr,
6319	[GCC_PCIE_3_PHY_RCHNG_CLK] = &gcc_pcie_3_phy_rchng_clk.clkr,
6320	[GCC_PCIE_3_PHY_RCHNG_CLK_SRC] = &gcc_pcie_3_phy_rchng_clk_src.clkr,
6321	[GCC_PCIE_3_PIPE_CLK] = &gcc_pcie_3_pipe_clk.clkr,
6322	[GCC_PCIE_3_PIPE_CLK_SRC] = &gcc_pcie_3_pipe_clk_src.clkr,
6323	[GCC_PCIE_3_PIPE_DIV_CLK_SRC] = &gcc_pcie_3_pipe_div_clk_src.clkr,
6324	[GCC_PCIE_3_PIPEDIV2_CLK] = &gcc_pcie_3_pipediv2_clk.clkr,
6325	[GCC_PCIE_3_SLV_AXI_CLK] = &gcc_pcie_3_slv_axi_clk.clkr,
6326	[GCC_PCIE_3_SLV_Q2A_AXI_CLK] = &gcc_pcie_3_slv_q2a_axi_clk.clkr,
6327	[GCC_PCIE_4_AUX_CLK] = &gcc_pcie_4_aux_clk.clkr,
6328	[GCC_PCIE_4_AUX_CLK_SRC] = &gcc_pcie_4_aux_clk_src.clkr,
6329	[GCC_PCIE_4_CFG_AHB_CLK] = &gcc_pcie_4_cfg_ahb_clk.clkr,
6330	[GCC_PCIE_4_MSTR_AXI_CLK] = &gcc_pcie_4_mstr_axi_clk.clkr,
6331	[GCC_PCIE_4_PHY_RCHNG_CLK] = &gcc_pcie_4_phy_rchng_clk.clkr,
6332	[GCC_PCIE_4_PHY_RCHNG_CLK_SRC] = &gcc_pcie_4_phy_rchng_clk_src.clkr,
6333	[GCC_PCIE_4_PIPE_CLK] = &gcc_pcie_4_pipe_clk.clkr,
6334	[GCC_PCIE_4_PIPE_CLK_SRC] = &gcc_pcie_4_pipe_clk_src.clkr,
6335	[GCC_PCIE_4_PIPE_DIV_CLK_SRC] = &gcc_pcie_4_pipe_div_clk_src.clkr,
6336	[GCC_PCIE_4_PIPEDIV2_CLK] = &gcc_pcie_4_pipediv2_clk.clkr,
6337	[GCC_PCIE_4_SLV_AXI_CLK] = &gcc_pcie_4_slv_axi_clk.clkr,
6338	[GCC_PCIE_4_SLV_Q2A_AXI_CLK] = &gcc_pcie_4_slv_q2a_axi_clk.clkr,
6339	[GCC_PCIE_5_AUX_CLK] = &gcc_pcie_5_aux_clk.clkr,
6340	[GCC_PCIE_5_AUX_CLK_SRC] = &gcc_pcie_5_aux_clk_src.clkr,
6341	[GCC_PCIE_5_CFG_AHB_CLK] = &gcc_pcie_5_cfg_ahb_clk.clkr,
6342	[GCC_PCIE_5_MSTR_AXI_CLK] = &gcc_pcie_5_mstr_axi_clk.clkr,
6343	[GCC_PCIE_5_PHY_RCHNG_CLK] = &gcc_pcie_5_phy_rchng_clk.clkr,
6344	[GCC_PCIE_5_PHY_RCHNG_CLK_SRC] = &gcc_pcie_5_phy_rchng_clk_src.clkr,
6345	[GCC_PCIE_5_PIPE_CLK] = &gcc_pcie_5_pipe_clk.clkr,
6346	[GCC_PCIE_5_PIPE_CLK_SRC] = &gcc_pcie_5_pipe_clk_src.clkr,
6347	[GCC_PCIE_5_PIPE_DIV_CLK_SRC] = &gcc_pcie_5_pipe_div_clk_src.clkr,
6348	[GCC_PCIE_5_PIPEDIV2_CLK] = &gcc_pcie_5_pipediv2_clk.clkr,
6349	[GCC_PCIE_5_SLV_AXI_CLK] = &gcc_pcie_5_slv_axi_clk.clkr,
6350	[GCC_PCIE_5_SLV_Q2A_AXI_CLK] = &gcc_pcie_5_slv_q2a_axi_clk.clkr,
6351	[GCC_PCIE_6A_AUX_CLK] = &gcc_pcie_6a_aux_clk.clkr,
6352	[GCC_PCIE_6A_AUX_CLK_SRC] = &gcc_pcie_6a_aux_clk_src.clkr,
6353	[GCC_PCIE_6A_CFG_AHB_CLK] = &gcc_pcie_6a_cfg_ahb_clk.clkr,
6354	[GCC_PCIE_6A_MSTR_AXI_CLK] = &gcc_pcie_6a_mstr_axi_clk.clkr,
6355	[GCC_PCIE_6A_PHY_AUX_CLK] = &gcc_pcie_6a_phy_aux_clk.clkr,
6356	[GCC_PCIE_6A_PHY_RCHNG_CLK] = &gcc_pcie_6a_phy_rchng_clk.clkr,
6357	[GCC_PCIE_6A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6a_phy_rchng_clk_src.clkr,
6358	[GCC_PCIE_6A_PIPE_CLK] = &gcc_pcie_6a_pipe_clk.clkr,
6359	[GCC_PCIE_6A_PIPE_CLK_SRC] = &gcc_pcie_6a_pipe_clk_src.clkr,
6360	[GCC_PCIE_6A_PIPE_DIV_CLK_SRC] = &gcc_pcie_6a_pipe_div_clk_src.clkr,
6361	[GCC_PCIE_6A_PIPEDIV2_CLK] = &gcc_pcie_6a_pipediv2_clk.clkr,
6362	[GCC_PCIE_6A_SLV_AXI_CLK] = &gcc_pcie_6a_slv_axi_clk.clkr,
6363	[GCC_PCIE_6A_SLV_Q2A_AXI_CLK] = &gcc_pcie_6a_slv_q2a_axi_clk.clkr,
6364	[GCC_PCIE_6B_AUX_CLK] = &gcc_pcie_6b_aux_clk.clkr,
6365	[GCC_PCIE_6B_AUX_CLK_SRC] = &gcc_pcie_6b_aux_clk_src.clkr,
6366	[GCC_PCIE_6B_CFG_AHB_CLK] = &gcc_pcie_6b_cfg_ahb_clk.clkr,
6367	[GCC_PCIE_6B_MSTR_AXI_CLK] = &gcc_pcie_6b_mstr_axi_clk.clkr,
6368	[GCC_PCIE_6B_PHY_AUX_CLK] = &gcc_pcie_6b_phy_aux_clk.clkr,
6369	[GCC_PCIE_6B_PHY_RCHNG_CLK] = &gcc_pcie_6b_phy_rchng_clk.clkr,
6370	[GCC_PCIE_6B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_6b_phy_rchng_clk_src.clkr,
6371	[GCC_PCIE_6B_PIPE_CLK] = &gcc_pcie_6b_pipe_clk.clkr,
6372	[GCC_PCIE_6B_PIPE_CLK_SRC] = &gcc_pcie_6b_pipe_clk_src.clkr,
6373	[GCC_PCIE_6B_PIPE_DIV_CLK_SRC] = &gcc_pcie_6b_pipe_div_clk_src.clkr,
6374	[GCC_PCIE_6B_PIPEDIV2_CLK] = &gcc_pcie_6b_pipediv2_clk.clkr,
6375	[GCC_PCIE_6B_SLV_AXI_CLK] = &gcc_pcie_6b_slv_axi_clk.clkr,
6376	[GCC_PCIE_6B_SLV_Q2A_AXI_CLK] = &gcc_pcie_6b_slv_q2a_axi_clk.clkr,
6377	[GCC_PCIE_RSCC_AHB_CLK] = &gcc_pcie_rscc_ahb_clk.clkr,
6378	[GCC_PCIE_RSCC_XO_CLK] = &gcc_pcie_rscc_xo_clk.clkr,
6379	[GCC_PCIE_RSCC_XO_CLK_SRC] = &gcc_pcie_rscc_xo_clk_src.clkr,
6380	[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
6381	[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
6382	[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
6383	[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
6384	[GCC_QMIP_AV1E_AHB_CLK] = &gcc_qmip_av1e_ahb_clk.clkr,
6385	[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
6386	[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
6387	[GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
6388	[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
6389	[GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr,
6390	[GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
6391	[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
6392	[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
6393	[GCC_QUPV3_WRAP0_CORE_2X_CLK] = &gcc_qupv3_wrap0_core_2x_clk.clkr,
6394	[GCC_QUPV3_WRAP0_CORE_CLK] = &gcc_qupv3_wrap0_core_clk.clkr,
6395	[GCC_QUPV3_WRAP0_QSPI_S2_CLK] = &gcc_qupv3_wrap0_qspi_s2_clk.clkr,
6396	[GCC_QUPV3_WRAP0_QSPI_S3_CLK] = &gcc_qupv3_wrap0_qspi_s3_clk.clkr,
6397	[GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
6398	[GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
6399	[GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
6400	[GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
6401	[GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
6402	[GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
6403	[GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s2_div_clk_src.clkr,
6404	[GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
6405	[GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
6406	[GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap0_s3_div_clk_src.clkr,
6407	[GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
6408	[GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
6409	[GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
6410	[GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
6411	[GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
6412	[GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
6413	[GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
6414	[GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
6415	[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
6416	[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
6417	[GCC_QUPV3_WRAP1_QSPI_S2_CLK] = &gcc_qupv3_wrap1_qspi_s2_clk.clkr,
6418	[GCC_QUPV3_WRAP1_QSPI_S3_CLK] = &gcc_qupv3_wrap1_qspi_s3_clk.clkr,
6419	[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
6420	[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
6421	[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
6422	[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
6423	[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
6424	[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
6425	[GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s2_div_clk_src.clkr,
6426	[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
6427	[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
6428	[GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap1_s3_div_clk_src.clkr,
6429	[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
6430	[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
6431	[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
6432	[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
6433	[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
6434	[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
6435	[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
6436	[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
6437	[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
6438	[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
6439	[GCC_QUPV3_WRAP2_QSPI_S2_CLK] = &gcc_qupv3_wrap2_qspi_s2_clk.clkr,
6440	[GCC_QUPV3_WRAP2_QSPI_S3_CLK] = &gcc_qupv3_wrap2_qspi_s3_clk.clkr,
6441	[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
6442	[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
6443	[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
6444	[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
6445	[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
6446	[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
6447	[GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s2_div_clk_src.clkr,
6448	[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
6449	[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
6450	[GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC] = &gcc_qupv3_wrap2_s3_div_clk_src.clkr,
6451	[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
6452	[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
6453	[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
6454	[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
6455	[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
6456	[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
6457	[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
6458	[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
6459	[GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
6460	[GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
6461	[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
6462	[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
6463	[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
6464	[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
6465	[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
6466	[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
6467	[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
6468	[GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
6469	[GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
6470	[GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
6471	[GCC_SYS_NOC_USB_AXI_CLK] = &gcc_sys_noc_usb_axi_clk.clkr,
6472	[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
6473	[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
6474	[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
6475	[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
6476	[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
6477	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
6478	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
6479	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
6480	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
6481	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
6482	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
6483	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
6484	[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
6485	[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
6486	[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
6487	[GCC_USB20_MOCK_UTMI_CLK_SRC] = &gcc_usb20_mock_utmi_clk_src.clkr,
6488	[GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb20_mock_utmi_postdiv_clk_src.clkr,
6489	[GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
6490	[GCC_USB30_MP_MASTER_CLK] = &gcc_usb30_mp_master_clk.clkr,
6491	[GCC_USB30_MP_MASTER_CLK_SRC] = &gcc_usb30_mp_master_clk_src.clkr,
6492	[GCC_USB30_MP_MOCK_UTMI_CLK] = &gcc_usb30_mp_mock_utmi_clk.clkr,
6493	[GCC_USB30_MP_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mp_mock_utmi_clk_src.clkr,
6494	[GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_mp_mock_utmi_postdiv_clk_src.clkr,
6495	[GCC_USB30_MP_SLEEP_CLK] = &gcc_usb30_mp_sleep_clk.clkr,
6496	[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
6497	[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
6498	[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
6499	[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
6500	[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
6501	[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
6502	[GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
6503	[GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
6504	[GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
6505	[GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] = &gcc_usb30_sec_mock_utmi_clk_src.clkr,
6506	[GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr,
6507	[GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
6508	[GCC_USB30_TERT_MASTER_CLK] = &gcc_usb30_tert_master_clk.clkr,
6509	[GCC_USB30_TERT_MASTER_CLK_SRC] = &gcc_usb30_tert_master_clk_src.clkr,
6510	[GCC_USB30_TERT_MOCK_UTMI_CLK] = &gcc_usb30_tert_mock_utmi_clk.clkr,
6511	[GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr,
6512	[GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr,
6513	[GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr,
6514	[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
6515	[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
6516	[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
6517	[GCC_USB3_MP_PHY_PIPE_0_CLK] = &gcc_usb3_mp_phy_pipe_0_clk.clkr,
6518	[GCC_USB3_MP_PHY_PIPE_1_CLK] = &gcc_usb3_mp_phy_pipe_1_clk.clkr,
6519	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
6520	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
6521	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
6522	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
6523	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
6524	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
6525	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
6526	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
6527	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
6528	[GCC_USB3_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb3_sec_phy_pipe_clk_src.clkr,
6529	[GCC_USB3_TERT_PHY_AUX_CLK] = &gcc_usb3_tert_phy_aux_clk.clkr,
6530	[GCC_USB3_TERT_PHY_AUX_CLK_SRC] = &gcc_usb3_tert_phy_aux_clk_src.clkr,
6531	[GCC_USB3_TERT_PHY_COM_AUX_CLK] = &gcc_usb3_tert_phy_com_aux_clk.clkr,
6532	[GCC_USB3_TERT_PHY_PIPE_CLK] = &gcc_usb3_tert_phy_pipe_clk.clkr,
6533	[GCC_USB3_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb3_tert_phy_pipe_clk_src.clkr,
6534	[GCC_USB4_0_CFG_AHB_CLK] = &gcc_usb4_0_cfg_ahb_clk.clkr,
6535	[GCC_USB4_0_DP0_CLK] = &gcc_usb4_0_dp0_clk.clkr,
6536	[GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr,
6537	[GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr,
6538	[GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr,
6539	[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr,
6540	[GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr,
6541	[GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr,
6542	[GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr,
6543	[GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr,
6544	[GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr,
6545	[GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr,
6546	[GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr,
6547	[GCC_USB4_0_SYS_CLK] = &gcc_usb4_0_sys_clk.clkr,
6548	[GCC_USB4_0_TMU_CLK] = &gcc_usb4_0_tmu_clk.clkr,
6549	[GCC_USB4_0_TMU_CLK_SRC] = &gcc_usb4_0_tmu_clk_src.clkr,
6550	[GCC_USB4_1_CFG_AHB_CLK] = &gcc_usb4_1_cfg_ahb_clk.clkr,
6551	[GCC_USB4_1_DP0_CLK] = &gcc_usb4_1_dp0_clk.clkr,
6552	[GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr,
6553	[GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
6554	[GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
6555	[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
6556	[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
6557	[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
6558	[GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
6559	[GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
6560	[GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
6561	[GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
6562	[GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
6563	[GCC_USB4_1_SYS_CLK] = &gcc_usb4_1_sys_clk.clkr,
6564	[GCC_USB4_1_TMU_CLK] = &gcc_usb4_1_tmu_clk.clkr,
6565	[GCC_USB4_1_TMU_CLK_SRC] = &gcc_usb4_1_tmu_clk_src.clkr,
6566	[GCC_USB4_2_CFG_AHB_CLK] = &gcc_usb4_2_cfg_ahb_clk.clkr,
6567	[GCC_USB4_2_DP0_CLK] = &gcc_usb4_2_dp0_clk.clkr,
6568	[GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr,
6569	[GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr,
6570	[GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr,
6571	[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr,
6572	[GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr,
6573	[GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr,
6574	[GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr,
6575	[GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr,
6576	[GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr,
6577	[GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr,
6578	[GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr,
6579	[GCC_USB4_2_SYS_CLK] = &gcc_usb4_2_sys_clk.clkr,
6580	[GCC_USB4_2_TMU_CLK] = &gcc_usb4_2_tmu_clk.clkr,
6581	[GCC_USB4_2_TMU_CLK_SRC] = &gcc_usb4_2_tmu_clk_src.clkr,
6582	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
6583	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
6584	};
6585
6586	static struct gdsc *gcc_x1e80100_gdscs[] = {
6587	[GCC_PCIE_0_TUNNEL_GDSC] = &gcc_pcie_0_tunnel_gdsc,
6588	[GCC_PCIE_1_TUNNEL_GDSC] = &gcc_pcie_1_tunnel_gdsc,
6589	[GCC_PCIE_2_TUNNEL_GDSC] = &gcc_pcie_2_tunnel_gdsc,
6590	[GCC_PCIE_3_GDSC] = &gcc_pcie_3_gdsc,
6591	[GCC_PCIE_3_PHY_GDSC] = &gcc_pcie_3_phy_gdsc,
6592	[GCC_PCIE_4_GDSC] = &gcc_pcie_4_gdsc,
6593	[GCC_PCIE_4_PHY_GDSC] = &gcc_pcie_4_phy_gdsc,
6594	[GCC_PCIE_5_GDSC] = &gcc_pcie_5_gdsc,
6595	[GCC_PCIE_5_PHY_GDSC] = &gcc_pcie_5_phy_gdsc,
6596	[GCC_PCIE_6_PHY_GDSC] = &gcc_pcie_6_phy_gdsc,
6597	[GCC_PCIE_6A_GDSC] = &gcc_pcie_6a_gdsc,
6598	[GCC_PCIE_6B_GDSC] = &gcc_pcie_6b_gdsc,
6599	[GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc,
6600	[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
6601	[GCC_USB20_PRIM_GDSC] = &gcc_usb20_prim_gdsc,
6602	[GCC_USB30_MP_GDSC] = &gcc_usb30_mp_gdsc,
6603	[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
6604	[GCC_USB30_SEC_GDSC] = &gcc_usb30_sec_gdsc,
6605	[GCC_USB30_TERT_GDSC] = &gcc_usb30_tert_gdsc,
6606	[GCC_USB3_MP_SS0_PHY_GDSC] = &gcc_usb3_mp_ss0_phy_gdsc,
6607	[GCC_USB3_MP_SS1_PHY_GDSC] = &gcc_usb3_mp_ss1_phy_gdsc,
6608	[GCC_USB4_0_GDSC] = &gcc_usb4_0_gdsc,
6609	[GCC_USB4_1_GDSC] = &gcc_usb4_1_gdsc,
6610	[GCC_USB4_2_GDSC] = &gcc_usb4_2_gdsc,
6611	[GCC_USB_0_PHY_GDSC] = &gcc_usb_0_phy_gdsc,
6612	[GCC_USB_1_PHY_GDSC] = &gcc_usb_1_phy_gdsc,
6613	[GCC_USB_2_PHY_GDSC] = &gcc_usb_2_phy_gdsc,
6614	};
6615
6616	static const struct qcom_reset_map gcc_x1e80100_resets[] = {
6617	[GCC_AV1E_BCR] = { 0x4a000 },
6618	[GCC_CAMERA_BCR] = { 0x26000 },
6619	[GCC_DISPLAY_BCR] = { 0x27000 },
6620	[GCC_GPU_BCR] = { 0x71000 },
6621	[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
6622	[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
6623	[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
6624	[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
6625	[GCC_PCIE_0_TUNNEL_BCR] = { 0xa0000 },
6626	[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
6627	[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
6628	[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
6629	[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
6630	[GCC_PCIE_1_TUNNEL_BCR] = { 0x2c000 },
6631	[GCC_PCIE_2_LINK_DOWN_BCR] = { 0xa5014 },
6632	[GCC_PCIE_2_NOCSR_COM_PHY_BCR] = { 0xa5020 },
6633	[GCC_PCIE_2_PHY_BCR] = { 0xa501c },
6634	[GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR] = { 0xa5028 },
6635	[GCC_PCIE_2_TUNNEL_BCR] = { 0x13000 },
6636	[GCC_PCIE_3_BCR] = { 0x58000 },
6637	[GCC_PCIE_3_LINK_DOWN_BCR] = { 0xab014 },
6638	[GCC_PCIE_3_NOCSR_COM_PHY_BCR] = { 0xab020 },
6639	[GCC_PCIE_3_PHY_BCR] = { 0xab01c },
6640	[GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR] = { 0xab024 },
6641	[GCC_PCIE_4_BCR] = { 0x6b000 },
6642	[GCC_PCIE_4_LINK_DOWN_BCR] = { 0xb3014 },
6643	[GCC_PCIE_4_NOCSR_COM_PHY_BCR] = { 0xb3020 },
6644	[GCC_PCIE_4_PHY_BCR] = { 0xb301c },
6645	[GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR] = { 0xb3028 },
6646	[GCC_PCIE_5_BCR] = { 0x2f000 },
6647	[GCC_PCIE_5_LINK_DOWN_BCR] = { 0xaa014 },
6648	[GCC_PCIE_5_NOCSR_COM_PHY_BCR] = { 0xaa020 },
6649	[GCC_PCIE_5_PHY_BCR] = { 0xaa01c },
6650	[GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR] = { 0xaa028 },
6651	[GCC_PCIE_6A_BCR] = { 0x31000 },
6652	[GCC_PCIE_6A_LINK_DOWN_BCR] = { 0xac014 },
6653	[GCC_PCIE_6A_NOCSR_COM_PHY_BCR] = { 0xac020 },
6654	[GCC_PCIE_6A_PHY_BCR] = { 0xac01c },
6655	[GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR] = { 0xac024 },
6656	[GCC_PCIE_6B_BCR] = { 0x8d000 },
6657	[GCC_PCIE_6B_LINK_DOWN_BCR] = { 0xb5014 },
6658	[GCC_PCIE_6B_NOCSR_COM_PHY_BCR] = { 0xb5020 },
6659	[GCC_PCIE_6B_PHY_BCR] = { 0xb501c },
6660	[GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR] = { 0xb5024 },
6661	[GCC_PCIE_PHY_BCR] = { 0x6f000 },
6662	[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
6663	[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
6664	[GCC_PCIE_RSCC_BCR] = { 0xa4000 },
6665	[GCC_PDM_BCR] = { 0x33000 },
6666	[GCC_QUPV3_WRAPPER_0_BCR] = { 0x42000 },
6667	[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
6668	[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
6669	[GCC_QUSB2PHY_HS0_MP_BCR] = { 0x1200c },
6670	[GCC_QUSB2PHY_HS1_MP_BCR] = { 0x12010 },
6671	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
6672	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
6673	[GCC_QUSB2PHY_TERT_BCR] = { 0x12008 },
6674	[GCC_QUSB2PHY_USB20_HS_BCR] = { 0x12014 },
6675	[GCC_SDCC2_BCR] = { 0x14000 },
6676	[GCC_SDCC4_BCR] = { 0x16000 },
6677	[GCC_UFS_PHY_BCR] = { 0x77000 },
6678	[GCC_USB20_PRIM_BCR] = { 0x29000 },
6679	[GCC_USB30_MP_BCR] = { 0x17000 },
6680	[GCC_USB30_PRIM_BCR] = { 0x39000 },
6681	[GCC_USB30_SEC_BCR] = { 0xa1000 },
6682	[GCC_USB30_TERT_BCR] = { 0xa2000 },
6683	[GCC_USB3_MP_SS0_PHY_BCR] = { 0x19008 },
6684	[GCC_USB3_MP_SS1_PHY_BCR] = { 0x54008 },
6685	[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
6686	[GCC_USB3_PHY_SEC_BCR] = { 0x2a000 },
6687	[GCC_USB3_PHY_TERT_BCR] = { 0xa3000 },
6688	[GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
6689	[GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
6690	[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
6691	[GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
6692	[GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
6693	[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
6694	[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
6695	[GCC_USB4_0_BCR] = { 0x9f000 },
6696	[GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
6697	[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
6698	[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
6699	[GCC_USB4_1_BCR] = { 0x2b000 },
6700	[GCC_USB4_2_BCR] = { 0x11000 },
6701	[GCC_USB_0_PHY_BCR] = { 0x50020 },
6702	[GCC_USB_1_PHY_BCR] = { 0x2a020 },
6703	[GCC_USB_2_PHY_BCR] = { 0xa3020 },
6704	[GCC_VIDEO_BCR] = { 0x32000 },
6705	};
6706
6707	static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {
6708	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s0_clk_src),
6709	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s1_clk_src),
6710	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s2_clk_src),
6711	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s3_clk_src),
6712	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s4_clk_src),
6713	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s5_clk_src),
6714	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s6_clk_src),
6715	DEFINE_RCG_DFS(gcc_qupv3_wrap0_s7_clk_src),
6716	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
6717	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
6718	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s2_clk_src),
6719	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
6720	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
6721	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
6722	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
6723	DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
6724	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
6725	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
6726	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
6727	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
6728	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
6729	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
6730	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
6731	DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
6732	};
6733
6734	static const struct regmap_config gcc_x1e80100_regmap_config = {
6735	.reg_bits = 32,
6736	.reg_stride = 4,
6737	.val_bits = 32,
6738	.max_register = 0x1f41f0,
6739	.fast_io = true,
6740	};
6741
6742	static const struct qcom_cc_desc gcc_x1e80100_desc = {
6743	.config = &gcc_x1e80100_regmap_config,
6744	.clks = gcc_x1e80100_clocks,
6745	.num_clks = ARRAY_SIZE(gcc_x1e80100_clocks),
6746	.resets = gcc_x1e80100_resets,
6747	.num_resets = ARRAY_SIZE(gcc_x1e80100_resets),
6748	.gdscs = gcc_x1e80100_gdscs,
6749	.num_gdscs = ARRAY_SIZE(gcc_x1e80100_gdscs),
6750	};
6751
6752	static const struct of_device_id gcc_x1e80100_match_table[] = {
6753	{ .compatible = "qcom,x1e80100-gcc" },
6754	{ }
6755	};
6756	MODULE_DEVICE_TABLE(of, gcc_x1e80100_match_table);
6757
6758	static int gcc_x1e80100_probe(struct platform_device *pdev)
6759	{
6760	struct regmap *regmap;
6761	int ret;
6762
6763	regmap = qcom_cc_map(pdev, desc: &gcc_x1e80100_desc);
6764	if (IS_ERR(ptr: regmap))
6765	return PTR_ERR(ptr: regmap);
6766
6767	ret = qcom_cc_register_rcg_dfs(regmap, rcgs: gcc_dfs_clocks,
6768	ARRAY_SIZE(gcc_dfs_clocks));
6769	if (ret)
6770	return ret;
6771
6772	/* Keep some clocks always-on */
6773	qcom_branch_set_clk_en(regmap, cbcr: 0x26004); /* GCC_CAMERA_AHB_CLK */
6774	qcom_branch_set_clk_en(regmap, cbcr: 0x26028); /* GCC_CAMERA_XO_CLK */
6775	qcom_branch_set_clk_en(regmap, cbcr: 0x27004); /* GCC_DISP_AHB_CLK */
6776	qcom_branch_set_clk_en(regmap, cbcr: 0x27018); /* GCC_DISP_XO_CLK */
6777	qcom_branch_set_clk_en(regmap, cbcr: 0x32004); /* GCC_VIDEO_AHB_CLK */
6778	qcom_branch_set_clk_en(regmap, cbcr: 0x32030); /* GCC_VIDEO_XO_CLK */
6779	qcom_branch_set_clk_en(regmap, cbcr: 0x71004); /* GCC_GPU_CFG_AHB_CLK */
6780
6781	/* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */
6782	regmap_write(map: regmap, reg: 0x52224, val: 0x0);
6783
6784	return qcom_cc_really_probe(pdev, desc: &gcc_x1e80100_desc, regmap);
6785	}
6786
6787	static struct platform_driver gcc_x1e80100_driver = {
6788	.probe = gcc_x1e80100_probe,
6789	.driver = {
6790	.name = "gcc-x1e80100",
6791	.of_match_table = gcc_x1e80100_match_table,
6792	},
6793	};
6794
6795	static int __init gcc_x1e80100_init(void)
6796	{
6797	return platform_driver_register(&gcc_x1e80100_driver);
6798	}
6799	subsys_initcall(gcc_x1e80100_init);
6800
6801	static void __exit gcc_x1e80100_exit(void)
6802	{
6803	platform_driver_unregister(&gcc_x1e80100_driver);
6804	}
6805	module_exit(gcc_x1e80100_exit);
6806
6807	MODULE_DESCRIPTION("QTI GCC X1E80100 Driver");
6808	MODULE_LICENSE("GPL");
6809