1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved |
4 | * Copyright (c) 2023, Linaro Limited |
5 | */ |
6 | |
7 | #include <linux/clk-provider.h> |
8 | #include <linux/mod_devicetable.h> |
9 | #include <linux/module.h> |
10 | #include <linux/platform_device.h> |
11 | #include <linux/regmap.h> |
12 | |
13 | #include <dt-bindings/clock/qcom,sm8650-gpucc.h> |
14 | #include <dt-bindings/reset/qcom,sm8650-gpucc.h> |
15 | |
16 | #include "clk-alpha-pll.h" |
17 | #include "clk-branch.h" |
18 | #include "clk-rcg.h" |
19 | #include "clk-regmap.h" |
20 | #include "clk-regmap-divider.h" |
21 | #include "clk-regmap-mux.h" |
22 | #include "clk-regmap-phy-mux.h" |
23 | #include "gdsc.h" |
24 | #include "reset.h" |
25 | |
26 | enum { |
27 | DT_BI_TCXO, |
28 | DT_GPLL0_OUT_MAIN, |
29 | DT_GPLL0_OUT_MAIN_DIV, |
30 | }; |
31 | |
32 | enum { |
33 | P_BI_TCXO, |
34 | P_GPLL0_OUT_MAIN, |
35 | P_GPLL0_OUT_MAIN_DIV, |
36 | P_GPU_CC_PLL0_OUT_MAIN, |
37 | P_GPU_CC_PLL1_OUT_MAIN, |
38 | }; |
39 | |
40 | static struct pll_vco lucid_ole_vco[] = { |
41 | { 249600000, 2100000000, 0 }, |
42 | }; |
43 | |
44 | static const struct alpha_pll_config gpu_cc_pll0_config = { |
45 | .l = 0x20, |
46 | .alpha = 0x4aaa, |
47 | .config_ctl_val = 0x20485699, |
48 | .config_ctl_hi_val = 0x00182261, |
49 | .config_ctl_hi1_val = 0x82aa299c, |
50 | .test_ctl_val = 0x00000000, |
51 | .test_ctl_hi_val = 0x00000003, |
52 | .test_ctl_hi1_val = 0x00009000, |
53 | .test_ctl_hi2_val = 0x00000034, |
54 | .user_ctl_val = 0x00000000, |
55 | .user_ctl_hi_val = 0x00000005, |
56 | }; |
57 | |
58 | static struct clk_alpha_pll gpu_cc_pll0 = { |
59 | .offset = 0x0, |
60 | .vco_table = lucid_ole_vco, |
61 | .num_vco = ARRAY_SIZE(lucid_ole_vco), |
62 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], |
63 | .clkr = { |
64 | .hw.init = &(struct clk_init_data){ |
65 | .name = "gpu_cc_pll0" , |
66 | .parent_data = &(const struct clk_parent_data){ |
67 | .index = DT_BI_TCXO, |
68 | }, |
69 | .num_parents = 1, |
70 | .ops = &clk_alpha_pll_lucid_evo_ops, |
71 | }, |
72 | }, |
73 | }; |
74 | |
75 | static const struct alpha_pll_config gpu_cc_pll1_config = { |
76 | .l = 0x1b, |
77 | .alpha = 0x1555, |
78 | .config_ctl_val = 0x20485699, |
79 | .config_ctl_hi_val = 0x00182261, |
80 | .config_ctl_hi1_val = 0x82aa299c, |
81 | .test_ctl_val = 0x00000000, |
82 | .test_ctl_hi_val = 0x00000003, |
83 | .test_ctl_hi1_val = 0x00009000, |
84 | .test_ctl_hi2_val = 0x00000034, |
85 | .user_ctl_val = 0x00000000, |
86 | .user_ctl_hi_val = 0x00000005, |
87 | }; |
88 | |
89 | static struct clk_alpha_pll gpu_cc_pll1 = { |
90 | .offset = 0x1000, |
91 | .vco_table = lucid_ole_vco, |
92 | .num_vco = ARRAY_SIZE(lucid_ole_vco), |
93 | .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], |
94 | .clkr = { |
95 | .hw.init = &(struct clk_init_data){ |
96 | .name = "gpu_cc_pll1" , |
97 | .parent_data = &(const struct clk_parent_data){ |
98 | .index = DT_BI_TCXO, |
99 | }, |
100 | .num_parents = 1, |
101 | .ops = &clk_alpha_pll_lucid_evo_ops, |
102 | }, |
103 | }, |
104 | }; |
105 | |
106 | static const struct parent_map gpu_cc_parent_map_0[] = { |
107 | { P_BI_TCXO, 0 }, |
108 | { P_GPLL0_OUT_MAIN, 5 }, |
109 | { P_GPLL0_OUT_MAIN_DIV, 6 }, |
110 | }; |
111 | |
112 | static const struct clk_parent_data gpu_cc_parent_data_0[] = { |
113 | { .index = DT_BI_TCXO }, |
114 | { .index = DT_GPLL0_OUT_MAIN }, |
115 | { .index = DT_GPLL0_OUT_MAIN_DIV }, |
116 | }; |
117 | |
118 | static const struct parent_map gpu_cc_parent_map_1[] = { |
119 | { P_BI_TCXO, 0 }, |
120 | { P_GPU_CC_PLL0_OUT_MAIN, 1 }, |
121 | { P_GPU_CC_PLL1_OUT_MAIN, 3 }, |
122 | { P_GPLL0_OUT_MAIN, 5 }, |
123 | { P_GPLL0_OUT_MAIN_DIV, 6 }, |
124 | }; |
125 | |
126 | static const struct clk_parent_data gpu_cc_parent_data_1[] = { |
127 | { .index = DT_BI_TCXO }, |
128 | { .hw = &gpu_cc_pll0.clkr.hw }, |
129 | { .hw = &gpu_cc_pll1.clkr.hw }, |
130 | { .index = DT_GPLL0_OUT_MAIN }, |
131 | { .index = DT_GPLL0_OUT_MAIN_DIV }, |
132 | }; |
133 | |
134 | static const struct parent_map gpu_cc_parent_map_2[] = { |
135 | { P_BI_TCXO, 0 }, |
136 | { P_GPU_CC_PLL1_OUT_MAIN, 3 }, |
137 | { P_GPLL0_OUT_MAIN, 5 }, |
138 | { P_GPLL0_OUT_MAIN_DIV, 6 }, |
139 | }; |
140 | |
141 | static const struct clk_parent_data gpu_cc_parent_data_2[] = { |
142 | { .index = DT_BI_TCXO }, |
143 | { .hw = &gpu_cc_pll1.clkr.hw }, |
144 | { .index = DT_GPLL0_OUT_MAIN }, |
145 | { .index = DT_GPLL0_OUT_MAIN_DIV }, |
146 | }; |
147 | |
148 | static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { |
149 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
150 | { } |
151 | }; |
152 | |
153 | static struct clk_rcg2 gpu_cc_ff_clk_src = { |
154 | .cmd_rcgr = 0x9474, |
155 | .mnd_width = 0, |
156 | .hid_width = 5, |
157 | .parent_map = gpu_cc_parent_map_0, |
158 | .freq_tbl = ftbl_gpu_cc_ff_clk_src, |
159 | .hw_clk_ctrl = true, |
160 | .clkr.hw.init = &(struct clk_init_data){ |
161 | .name = "gpu_cc_ff_clk_src" , |
162 | .parent_data = gpu_cc_parent_data_0, |
163 | .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), |
164 | .flags = CLK_SET_RATE_PARENT, |
165 | .ops = &clk_rcg2_shared_ops, |
166 | }, |
167 | }; |
168 | |
169 | static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { |
170 | F(19200000, P_BI_TCXO, 1, 0, 0), |
171 | F(260000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), |
172 | F(625000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), |
173 | { } |
174 | }; |
175 | |
176 | static struct clk_rcg2 gpu_cc_gmu_clk_src = { |
177 | .cmd_rcgr = 0x9318, |
178 | .mnd_width = 0, |
179 | .hid_width = 5, |
180 | .parent_map = gpu_cc_parent_map_1, |
181 | .freq_tbl = ftbl_gpu_cc_gmu_clk_src, |
182 | .hw_clk_ctrl = true, |
183 | .clkr.hw.init = &(struct clk_init_data){ |
184 | .name = "gpu_cc_gmu_clk_src" , |
185 | .parent_data = gpu_cc_parent_data_1, |
186 | .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), |
187 | .flags = CLK_SET_RATE_PARENT, |
188 | .ops = &clk_rcg2_shared_ops, |
189 | }, |
190 | }; |
191 | |
192 | static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { |
193 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
194 | F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), |
195 | { } |
196 | }; |
197 | |
198 | static struct clk_rcg2 gpu_cc_hub_clk_src = { |
199 | .cmd_rcgr = 0x93ec, |
200 | .mnd_width = 0, |
201 | .hid_width = 5, |
202 | .parent_map = gpu_cc_parent_map_2, |
203 | .freq_tbl = ftbl_gpu_cc_hub_clk_src, |
204 | .hw_clk_ctrl = true, |
205 | .clkr.hw.init = &(struct clk_init_data){ |
206 | .name = "gpu_cc_hub_clk_src" , |
207 | .parent_data = gpu_cc_parent_data_2, |
208 | .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), |
209 | .flags = CLK_SET_RATE_PARENT, |
210 | .ops = &clk_rcg2_shared_ops, |
211 | }, |
212 | }; |
213 | |
214 | static struct clk_regmap_div gpu_cc_hub_div_clk_src = { |
215 | .reg = 0x942c, |
216 | .shift = 0, |
217 | .width = 4, |
218 | .clkr.hw.init = &(const struct clk_init_data) { |
219 | .name = "gpu_cc_hub_div_clk_src" , |
220 | .parent_hws = (const struct clk_hw*[]){ |
221 | &gpu_cc_hub_clk_src.clkr.hw, |
222 | }, |
223 | .num_parents = 1, |
224 | .flags = CLK_SET_RATE_PARENT, |
225 | .ops = &clk_regmap_div_ro_ops, |
226 | }, |
227 | }; |
228 | |
229 | static struct clk_branch gpu_cc_ahb_clk = { |
230 | .halt_reg = 0x911c, |
231 | .halt_check = BRANCH_HALT_DELAY, |
232 | .clkr = { |
233 | .enable_reg = 0x911c, |
234 | .enable_mask = BIT(0), |
235 | .hw.init = &(struct clk_init_data){ |
236 | .name = "gpu_cc_ahb_clk" , |
237 | .parent_hws = (const struct clk_hw*[]){ |
238 | &gpu_cc_hub_div_clk_src.clkr.hw, |
239 | }, |
240 | .num_parents = 1, |
241 | .flags = CLK_SET_RATE_PARENT, |
242 | .ops = &clk_branch2_ops, |
243 | }, |
244 | }, |
245 | }; |
246 | |
247 | static struct clk_branch gpu_cc_crc_ahb_clk = { |
248 | .halt_reg = 0x9120, |
249 | .halt_check = BRANCH_HALT_VOTED, |
250 | .clkr = { |
251 | .enable_reg = 0x9120, |
252 | .enable_mask = BIT(0), |
253 | .hw.init = &(struct clk_init_data){ |
254 | .name = "gpu_cc_crc_ahb_clk" , |
255 | .parent_hws = (const struct clk_hw*[]){ |
256 | &gpu_cc_hub_clk_src.clkr.hw, |
257 | }, |
258 | .num_parents = 1, |
259 | .flags = CLK_SET_RATE_PARENT, |
260 | .ops = &clk_branch2_ops, |
261 | }, |
262 | }, |
263 | }; |
264 | |
265 | static struct clk_branch gpu_cc_cx_accu_shift_clk = { |
266 | .halt_reg = 0x9160, |
267 | .halt_check = BRANCH_HALT_VOTED, |
268 | .clkr = { |
269 | .enable_reg = 0x9160, |
270 | .enable_mask = BIT(0), |
271 | .hw.init = &(const struct clk_init_data){ |
272 | .name = "gpu_cc_cx_accu_shift_clk" , |
273 | .ops = &clk_branch2_ops, |
274 | }, |
275 | }, |
276 | }; |
277 | |
278 | static struct clk_branch gpu_cc_cx_ff_clk = { |
279 | .halt_reg = 0x914c, |
280 | .halt_check = BRANCH_HALT, |
281 | .clkr = { |
282 | .enable_reg = 0x914c, |
283 | .enable_mask = BIT(0), |
284 | .hw.init = &(struct clk_init_data){ |
285 | .name = "gpu_cc_cx_ff_clk" , |
286 | .parent_hws = (const struct clk_hw*[]){ |
287 | &gpu_cc_ff_clk_src.clkr.hw, |
288 | }, |
289 | .num_parents = 1, |
290 | .flags = CLK_SET_RATE_PARENT, |
291 | .ops = &clk_branch2_ops, |
292 | }, |
293 | }, |
294 | }; |
295 | |
296 | static struct clk_branch gpu_cc_cx_gmu_clk = { |
297 | .halt_reg = 0x913c, |
298 | .halt_check = BRANCH_HALT_VOTED, |
299 | .clkr = { |
300 | .enable_reg = 0x913c, |
301 | .enable_mask = BIT(0), |
302 | .hw.init = &(struct clk_init_data){ |
303 | .name = "gpu_cc_cx_gmu_clk" , |
304 | .parent_hws = (const struct clk_hw*[]){ |
305 | &gpu_cc_gmu_clk_src.clkr.hw, |
306 | }, |
307 | .num_parents = 1, |
308 | .flags = CLK_SET_RATE_PARENT, |
309 | .ops = &clk_branch2_aon_ops, |
310 | }, |
311 | }, |
312 | }; |
313 | |
314 | static struct clk_branch gpu_cc_cxo_aon_clk = { |
315 | .halt_reg = 0x9004, |
316 | .halt_check = BRANCH_HALT_VOTED, |
317 | .clkr = { |
318 | .enable_reg = 0x9004, |
319 | .enable_mask = BIT(0), |
320 | .hw.init = &(struct clk_init_data){ |
321 | .name = "gpu_cc_cxo_aon_clk" , |
322 | .ops = &clk_branch2_ops, |
323 | }, |
324 | }, |
325 | }; |
326 | |
327 | static struct clk_branch gpu_cc_cxo_clk = { |
328 | .halt_reg = 0x9144, |
329 | .halt_check = BRANCH_HALT, |
330 | .clkr = { |
331 | .enable_reg = 0x9144, |
332 | .enable_mask = BIT(0), |
333 | .hw.init = &(struct clk_init_data){ |
334 | .name = "gpu_cc_cxo_clk" , |
335 | .ops = &clk_branch2_ops, |
336 | }, |
337 | }, |
338 | }; |
339 | |
340 | static struct clk_branch gpu_cc_demet_clk = { |
341 | .halt_reg = 0x900c, |
342 | .halt_check = BRANCH_HALT, |
343 | .clkr = { |
344 | .enable_reg = 0x900c, |
345 | .enable_mask = BIT(0), |
346 | .hw.init = &(struct clk_init_data){ |
347 | .name = "gpu_cc_demet_clk" , |
348 | .ops = &clk_branch2_aon_ops, |
349 | }, |
350 | }, |
351 | }; |
352 | |
353 | static struct clk_branch gpu_cc_freq_measure_clk = { |
354 | .halt_reg = 0x9008, |
355 | .halt_check = BRANCH_HALT, |
356 | .clkr = { |
357 | .enable_reg = 0x9008, |
358 | .enable_mask = BIT(0), |
359 | .hw.init = &(struct clk_init_data){ |
360 | .name = "gpu_cc_freq_measure_clk" , |
361 | .ops = &clk_branch2_ops, |
362 | }, |
363 | }, |
364 | }; |
365 | |
366 | static struct clk_branch gpu_cc_gx_gfx3d_clk = { |
367 | .halt_reg = 0x90a8, |
368 | .halt_check = BRANCH_HALT, |
369 | .clkr = { |
370 | .enable_reg = 0x90a8, |
371 | .enable_mask = BIT(0), |
372 | .hw.init = &(struct clk_init_data){ |
373 | .name = "gpu_cc_gx_gfx3d_clk" , |
374 | .ops = &clk_branch2_ops, |
375 | }, |
376 | }, |
377 | }; |
378 | |
379 | static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = { |
380 | .halt_reg = 0x90c8, |
381 | .halt_check = BRANCH_HALT, |
382 | .clkr = { |
383 | .enable_reg = 0x90c8, |
384 | .enable_mask = BIT(0), |
385 | .hw.init = &(struct clk_init_data){ |
386 | .name = "gpu_cc_gx_gfx3d_rdvm_clk" , |
387 | .ops = &clk_branch2_ops, |
388 | }, |
389 | }, |
390 | }; |
391 | |
392 | static struct clk_branch gpu_cc_gx_gmu_clk = { |
393 | .halt_reg = 0x90bc, |
394 | .halt_check = BRANCH_HALT, |
395 | .clkr = { |
396 | .enable_reg = 0x90bc, |
397 | .enable_mask = BIT(0), |
398 | .hw.init = &(struct clk_init_data){ |
399 | .name = "gpu_cc_gx_gmu_clk" , |
400 | .parent_hws = (const struct clk_hw*[]){ |
401 | &gpu_cc_gmu_clk_src.clkr.hw, |
402 | }, |
403 | .num_parents = 1, |
404 | .flags = CLK_SET_RATE_PARENT, |
405 | .ops = &clk_branch2_ops, |
406 | }, |
407 | }, |
408 | }; |
409 | |
410 | static struct clk_branch gpu_cc_gx_vsense_clk = { |
411 | .halt_reg = 0x90b0, |
412 | .halt_check = BRANCH_HALT_VOTED, |
413 | .clkr = { |
414 | .enable_reg = 0x90b0, |
415 | .enable_mask = BIT(0), |
416 | .hw.init = &(struct clk_init_data){ |
417 | .name = "gpu_cc_gx_vsense_clk" , |
418 | .ops = &clk_branch2_ops, |
419 | }, |
420 | }, |
421 | }; |
422 | |
423 | static struct clk_branch gpu_cc_gx_accu_shift_clk = { |
424 | .halt_reg = 0x90d0, |
425 | .halt_check = BRANCH_HALT_VOTED, |
426 | .clkr = { |
427 | .enable_reg = 0x90d0, |
428 | .enable_mask = BIT(0), |
429 | .hw.init = &(const struct clk_init_data){ |
430 | .name = "gpu_cc_gx_accu_shift_clk" , |
431 | .ops = &clk_branch2_ops, |
432 | }, |
433 | }, |
434 | }; |
435 | |
436 | static struct clk_branch gpu_cc_gx_ff_clk = { |
437 | .halt_reg = 0x90c0, |
438 | .halt_check = BRANCH_HALT, |
439 | .clkr = { |
440 | .enable_reg = 0x90c0, |
441 | .enable_mask = BIT(0), |
442 | .hw.init = &(const struct clk_init_data){ |
443 | .name = "gpu_cc_gx_ff_clk" , |
444 | .parent_hws = (const struct clk_hw*[]){ |
445 | &gpu_cc_ff_clk_src.clkr.hw, |
446 | }, |
447 | .num_parents = 1, |
448 | .flags = CLK_SET_RATE_PARENT, |
449 | .ops = &clk_branch2_ops, |
450 | }, |
451 | }, |
452 | }; |
453 | |
454 | static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { |
455 | .halt_reg = 0x7000, |
456 | .halt_check = BRANCH_HALT_VOTED, |
457 | .clkr = { |
458 | .enable_reg = 0x7000, |
459 | .enable_mask = BIT(0), |
460 | .hw.init = &(struct clk_init_data){ |
461 | .name = "gpu_cc_hlos1_vote_gpu_smmu_clk" , |
462 | .ops = &clk_branch2_ops, |
463 | }, |
464 | }, |
465 | }; |
466 | |
467 | static struct clk_branch gpu_cc_hub_aon_clk = { |
468 | .halt_reg = 0x93e8, |
469 | .halt_check = BRANCH_HALT_VOTED, |
470 | .clkr = { |
471 | .enable_reg = 0x93e8, |
472 | .enable_mask = BIT(0), |
473 | .hw.init = &(struct clk_init_data){ |
474 | .name = "gpu_cc_hub_aon_clk" , |
475 | .parent_hws = (const struct clk_hw*[]){ |
476 | &gpu_cc_hub_clk_src.clkr.hw, |
477 | }, |
478 | .num_parents = 1, |
479 | .flags = CLK_SET_RATE_PARENT, |
480 | .ops = &clk_branch2_aon_ops, |
481 | }, |
482 | }, |
483 | }; |
484 | |
485 | static struct clk_branch gpu_cc_hub_cx_int_clk = { |
486 | .halt_reg = 0x9148, |
487 | .halt_check = BRANCH_HALT_VOTED, |
488 | .clkr = { |
489 | .enable_reg = 0x9148, |
490 | .enable_mask = BIT(0), |
491 | .hw.init = &(struct clk_init_data){ |
492 | .name = "gpu_cc_hub_cx_int_clk" , |
493 | .parent_hws = (const struct clk_hw*[]){ |
494 | &gpu_cc_hub_clk_src.clkr.hw, |
495 | }, |
496 | .num_parents = 1, |
497 | .flags = CLK_SET_RATE_PARENT, |
498 | .ops = &clk_branch2_aon_ops, |
499 | }, |
500 | }, |
501 | }; |
502 | |
503 | static struct clk_branch gpu_cc_memnoc_gfx_clk = { |
504 | .halt_reg = 0x9150, |
505 | .halt_check = BRANCH_HALT_VOTED, |
506 | .clkr = { |
507 | .enable_reg = 0x9150, |
508 | .enable_mask = BIT(0), |
509 | .hw.init = &(struct clk_init_data){ |
510 | .name = "gpu_cc_memnoc_gfx_clk" , |
511 | .ops = &clk_branch2_ops, |
512 | }, |
513 | }, |
514 | }; |
515 | |
516 | static struct clk_branch gpu_cc_sleep_clk = { |
517 | .halt_reg = 0x9134, |
518 | .halt_check = BRANCH_HALT_VOTED, |
519 | .clkr = { |
520 | .enable_reg = 0x9134, |
521 | .enable_mask = BIT(0), |
522 | .hw.init = &(struct clk_init_data){ |
523 | .name = "gpu_cc_sleep_clk" , |
524 | .ops = &clk_branch2_ops, |
525 | }, |
526 | }, |
527 | }; |
528 | |
529 | static struct clk_branch gpu_cc_dpm_clk = { |
530 | .halt_reg = 0x9164, |
531 | .halt_check = BRANCH_HALT, |
532 | .clkr = { |
533 | .enable_reg = 0x9164, |
534 | .enable_mask = BIT(0), |
535 | .hw.init = &(const struct clk_init_data){ |
536 | .name = "gpu_cc_dpm_clk" , |
537 | .ops = &clk_branch2_ops, |
538 | }, |
539 | }, |
540 | }; |
541 | |
542 | static struct gdsc gpu_cx_gdsc = { |
543 | .gdscr = 0x9108, |
544 | .gds_hw_ctrl = 0x9168, |
545 | .clk_dis_wait_val = 8, |
546 | .pd = { |
547 | .name = "gpu_cx_gdsc" , |
548 | }, |
549 | .pwrsts = PWRSTS_OFF_ON, |
550 | .flags = VOTABLE | RETAIN_FF_ENABLE, |
551 | }; |
552 | |
553 | static struct gdsc gpu_gx_gdsc = { |
554 | .gdscr = 0x905c, |
555 | .clamp_io_ctrl = 0x9504, |
556 | .resets = (unsigned int []){ GPUCC_GPU_CC_GX_BCR, |
557 | GPUCC_GPU_CC_ACD_BCR, |
558 | GPUCC_GPU_CC_GX_ACD_IROOT_BCR }, |
559 | .reset_count = 3, |
560 | .pd = { |
561 | .name = "gpu_gx_gdsc" , |
562 | .power_on = gdsc_gx_do_nothing_enable, |
563 | }, |
564 | .pwrsts = PWRSTS_OFF_ON, |
565 | .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR, |
566 | }; |
567 | |
568 | static struct clk_regmap *gpu_cc_sm8650_clocks[] = { |
569 | [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, |
570 | [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, |
571 | [GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr, |
572 | [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, |
573 | [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, |
574 | [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, |
575 | [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, |
576 | [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, |
577 | [GPU_CC_DPM_CLK] = &gpu_cc_dpm_clk.clkr, |
578 | [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, |
579 | [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, |
580 | [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, |
581 | [GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr, |
582 | [GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr, |
583 | [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, |
584 | [GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr, |
585 | [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, |
586 | [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, |
587 | [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, |
588 | [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, |
589 | [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, |
590 | [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, |
591 | [GPU_CC_HUB_DIV_CLK_SRC] = &gpu_cc_hub_div_clk_src.clkr, |
592 | [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, |
593 | [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, |
594 | [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, |
595 | [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, |
596 | }; |
597 | |
598 | static const struct qcom_reset_map gpu_cc_sm8650_resets[] = { |
599 | [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, |
600 | [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, |
601 | [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, |
602 | [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, |
603 | [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, |
604 | [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, |
605 | [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, |
606 | [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, |
607 | [GPUCC_GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c }, |
608 | }; |
609 | |
610 | static struct gdsc *gpu_cc_sm8650_gdscs[] = { |
611 | [GPU_CX_GDSC] = &gpu_cx_gdsc, |
612 | [GPU_GX_GDSC] = &gpu_gx_gdsc, |
613 | }; |
614 | |
615 | static const struct regmap_config gpu_cc_sm8650_regmap_config = { |
616 | .reg_bits = 32, |
617 | .reg_stride = 4, |
618 | .val_bits = 32, |
619 | .max_register = 0xa000, |
620 | .fast_io = true, |
621 | }; |
622 | |
623 | static const struct qcom_cc_desc gpu_cc_sm8650_desc = { |
624 | .config = &gpu_cc_sm8650_regmap_config, |
625 | .clks = gpu_cc_sm8650_clocks, |
626 | .num_clks = ARRAY_SIZE(gpu_cc_sm8650_clocks), |
627 | .resets = gpu_cc_sm8650_resets, |
628 | .num_resets = ARRAY_SIZE(gpu_cc_sm8650_resets), |
629 | .gdscs = gpu_cc_sm8650_gdscs, |
630 | .num_gdscs = ARRAY_SIZE(gpu_cc_sm8650_gdscs), |
631 | }; |
632 | |
633 | static const struct of_device_id gpu_cc_sm8650_match_table[] = { |
634 | { .compatible = "qcom,sm8650-gpucc" }, |
635 | { } |
636 | }; |
637 | MODULE_DEVICE_TABLE(of, gpu_cc_sm8650_match_table); |
638 | |
639 | static int gpu_cc_sm8650_probe(struct platform_device *pdev) |
640 | { |
641 | struct regmap *regmap; |
642 | |
643 | regmap = qcom_cc_map(pdev, desc: &gpu_cc_sm8650_desc); |
644 | if (IS_ERR(ptr: regmap)) |
645 | return PTR_ERR(ptr: regmap); |
646 | |
647 | clk_lucid_ole_pll_configure(pll: &gpu_cc_pll0, regmap, config: &gpu_cc_pll0_config); |
648 | clk_lucid_ole_pll_configure(pll: &gpu_cc_pll1, regmap, config: &gpu_cc_pll1_config); |
649 | |
650 | return qcom_cc_really_probe(pdev, desc: &gpu_cc_sm8650_desc, regmap); |
651 | } |
652 | |
653 | static struct platform_driver gpu_cc_sm8650_driver = { |
654 | .probe = gpu_cc_sm8650_probe, |
655 | .driver = { |
656 | .name = "sm8650-gpucc" , |
657 | .of_match_table = gpu_cc_sm8650_match_table, |
658 | }, |
659 | }; |
660 | module_platform_driver(gpu_cc_sm8650_driver); |
661 | |
662 | MODULE_DESCRIPTION("QTI GPU_CC SM8650 Driver" ); |
663 | MODULE_LICENSE("GPL" ); |
664 | |