1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset |
4 | * |
5 | * Copyright (C) 2020 Renesas Electronics Corp. |
6 | * |
7 | * Based on r8a7795-cpg-mssr.c |
8 | * |
9 | * Copyright (C) 2015 Glider bvba |
10 | * Copyright (C) 2015 Renesas Electronics Corp. |
11 | */ |
12 | |
13 | #include <linux/bitfield.h> |
14 | #include <linux/clk.h> |
15 | #include <linux/clk-provider.h> |
16 | #include <linux/device.h> |
17 | #include <linux/err.h> |
18 | #include <linux/init.h> |
19 | #include <linux/kernel.h> |
20 | #include <linux/soc/renesas/rcar-rst.h> |
21 | |
22 | #include <dt-bindings/clock/r8a779a0-cpg-mssr.h> |
23 | |
24 | #include "renesas-cpg-mssr.h" |
25 | #include "rcar-gen4-cpg.h" |
26 | |
27 | enum clk_ids { |
28 | /* Core Clock Outputs exported to DT */ |
29 | LAST_DT_CORE_CLK = R8A779A0_CLK_OSC, |
30 | |
31 | /* External Input Clocks */ |
32 | CLK_EXTAL, |
33 | CLK_EXTALR, |
34 | |
35 | /* Internal Core Clocks */ |
36 | CLK_MAIN, |
37 | CLK_PLL1, |
38 | CLK_PLL20, |
39 | CLK_PLL21, |
40 | CLK_PLL30, |
41 | CLK_PLL31, |
42 | CLK_PLL5, |
43 | CLK_PLL1_DIV2, |
44 | CLK_PLL20_DIV2, |
45 | CLK_PLL21_DIV2, |
46 | CLK_PLL30_DIV2, |
47 | CLK_PLL31_DIV2, |
48 | CLK_PLL5_DIV2, |
49 | CLK_PLL5_DIV4, |
50 | CLK_S1, |
51 | CLK_S3, |
52 | CLK_SDSRC, |
53 | CLK_RPCSRC, |
54 | CLK_OCO, |
55 | |
56 | /* Module Clocks */ |
57 | MOD_CLK_BASE |
58 | }; |
59 | |
60 | #define DEF_PLL(_name, _id, _offset) \ |
61 | DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \ |
62 | .offset = _offset) |
63 | |
64 | static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { |
65 | /* External Clock Inputs */ |
66 | DEF_INPUT("extal" , CLK_EXTAL), |
67 | DEF_INPUT("extalr" , CLK_EXTALR), |
68 | |
69 | /* Internal Core Clocks */ |
70 | DEF_BASE(".main" , CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), |
71 | DEF_BASE(".pll1" , CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), |
72 | DEF_BASE(".pll5" , CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), |
73 | DEF_PLL(".pll20" , CLK_PLL20, 0x0834), |
74 | DEF_PLL(".pll21" , CLK_PLL21, 0x0838), |
75 | DEF_PLL(".pll30" , CLK_PLL30, 0x083c), |
76 | DEF_PLL(".pll31" , CLK_PLL31, 0x0840), |
77 | |
78 | DEF_FIXED(".pll1_div2" , CLK_PLL1_DIV2, CLK_PLL1, 2, 1), |
79 | DEF_FIXED(".pll20_div2" , CLK_PLL20_DIV2, CLK_PLL20, 2, 1), |
80 | DEF_FIXED(".pll21_div2" , CLK_PLL21_DIV2, CLK_PLL21, 2, 1), |
81 | DEF_FIXED(".pll30_div2" , CLK_PLL30_DIV2, CLK_PLL30, 2, 1), |
82 | DEF_FIXED(".pll31_div2" , CLK_PLL31_DIV2, CLK_PLL31, 2, 1), |
83 | DEF_FIXED(".pll5_div2" , CLK_PLL5_DIV2, CLK_PLL5, 2, 1), |
84 | DEF_FIXED(".pll5_div4" , CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1), |
85 | DEF_FIXED(".s1" , CLK_S1, CLK_PLL1_DIV2, 2, 1), |
86 | DEF_FIXED(".s3" , CLK_S3, CLK_PLL1_DIV2, 4, 1), |
87 | DEF_FIXED(".sdsrc" , CLK_SDSRC, CLK_PLL5_DIV4, 1, 1), |
88 | |
89 | DEF_RATE(".oco" , CLK_OCO, 32768), |
90 | |
91 | DEF_BASE(".rpcsrc" , CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), |
92 | |
93 | /* Core Clock Outputs */ |
94 | DEF_GEN4_Z("z0" , R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0), |
95 | DEF_GEN4_Z("z1" , R8A779A0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL21, 2, 8), |
96 | DEF_FIXED("zx" , R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1), |
97 | DEF_FIXED("s1d1" , R8A779A0_CLK_S1D1, CLK_S1, 1, 1), |
98 | DEF_FIXED("s1d2" , R8A779A0_CLK_S1D2, CLK_S1, 2, 1), |
99 | DEF_FIXED("s1d4" , R8A779A0_CLK_S1D4, CLK_S1, 4, 1), |
100 | DEF_FIXED("s1d8" , R8A779A0_CLK_S1D8, CLK_S1, 8, 1), |
101 | DEF_FIXED("s1d12" , R8A779A0_CLK_S1D12, CLK_S1, 12, 1), |
102 | DEF_FIXED("s3d1" , R8A779A0_CLK_S3D1, CLK_S3, 1, 1), |
103 | DEF_FIXED("s3d2" , R8A779A0_CLK_S3D2, CLK_S3, 2, 1), |
104 | DEF_FIXED("s3d4" , R8A779A0_CLK_S3D4, CLK_S3, 4, 1), |
105 | DEF_FIXED("zs" , R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1), |
106 | DEF_FIXED("zt" , R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1), |
107 | DEF_FIXED("ztr" , R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1), |
108 | DEF_FIXED("zr" , R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1), |
109 | DEF_FIXED("cnndsp" , R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1), |
110 | DEF_FIXED("vip" , R8A779A0_CLK_VIP, CLK_PLL5, 5, 1), |
111 | DEF_FIXED("adgh" , R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1), |
112 | DEF_FIXED("icu" , R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1), |
113 | DEF_FIXED("icud2" , R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1), |
114 | DEF_FIXED("vcbus" , R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), |
115 | DEF_FIXED("cbfusa" , R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1), |
116 | DEF_FIXED("cp" , R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), |
117 | DEF_FIXED("cl16mck" , R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1), |
118 | |
119 | DEF_GEN4_SDH("sd0h" , R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870), |
120 | DEF_GEN4_SD("sd0" , R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870), |
121 | |
122 | DEF_BASE("rpc" , R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), |
123 | DEF_BASE("rpcd2" , R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, |
124 | R8A779A0_CLK_RPC), |
125 | |
126 | DEF_DIV6P1("mso" , R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), |
127 | DEF_DIV6P1("canfd" , R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), |
128 | DEF_DIV6P1("csi0" , R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), |
129 | DEF_DIV6P1("dsi" , R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884), |
130 | |
131 | DEF_GEN4_OSC("osc" , R8A779A0_CLK_OSC, CLK_EXTAL, 8), |
132 | DEF_GEN4_MDSEL("r" , R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), |
133 | }; |
134 | |
135 | static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = { |
136 | DEF_MOD("avb0" , 211, R8A779A0_CLK_S3D2), |
137 | DEF_MOD("avb1" , 212, R8A779A0_CLK_S3D2), |
138 | DEF_MOD("avb2" , 213, R8A779A0_CLK_S3D2), |
139 | DEF_MOD("avb3" , 214, R8A779A0_CLK_S3D2), |
140 | DEF_MOD("avb4" , 215, R8A779A0_CLK_S3D2), |
141 | DEF_MOD("avb5" , 216, R8A779A0_CLK_S3D2), |
142 | DEF_MOD("canfd0" , 328, R8A779A0_CLK_CANFD), |
143 | DEF_MOD("csi40" , 331, R8A779A0_CLK_CSI0), |
144 | DEF_MOD("csi41" , 400, R8A779A0_CLK_CSI0), |
145 | DEF_MOD("csi42" , 401, R8A779A0_CLK_CSI0), |
146 | DEF_MOD("csi43" , 402, R8A779A0_CLK_CSI0), |
147 | DEF_MOD("du" , 411, R8A779A0_CLK_S3D1), |
148 | DEF_MOD("dsi0" , 415, R8A779A0_CLK_DSI), |
149 | DEF_MOD("dsi1" , 416, R8A779A0_CLK_DSI), |
150 | DEF_MOD("fcpvd0" , 508, R8A779A0_CLK_S3D1), |
151 | DEF_MOD("fcpvd1" , 509, R8A779A0_CLK_S3D1), |
152 | DEF_MOD("hscif0" , 514, R8A779A0_CLK_S1D2), |
153 | DEF_MOD("hscif1" , 515, R8A779A0_CLK_S1D2), |
154 | DEF_MOD("hscif2" , 516, R8A779A0_CLK_S1D2), |
155 | DEF_MOD("hscif3" , 517, R8A779A0_CLK_S1D2), |
156 | DEF_MOD("i2c0" , 518, R8A779A0_CLK_S1D4), |
157 | DEF_MOD("i2c1" , 519, R8A779A0_CLK_S1D4), |
158 | DEF_MOD("i2c2" , 520, R8A779A0_CLK_S1D4), |
159 | DEF_MOD("i2c3" , 521, R8A779A0_CLK_S1D4), |
160 | DEF_MOD("i2c4" , 522, R8A779A0_CLK_S1D4), |
161 | DEF_MOD("i2c5" , 523, R8A779A0_CLK_S1D4), |
162 | DEF_MOD("i2c6" , 524, R8A779A0_CLK_S1D4), |
163 | DEF_MOD("ispcs0" , 612, R8A779A0_CLK_S1D1), |
164 | DEF_MOD("ispcs1" , 613, R8A779A0_CLK_S1D1), |
165 | DEF_MOD("ispcs2" , 614, R8A779A0_CLK_S1D1), |
166 | DEF_MOD("ispcs3" , 615, R8A779A0_CLK_S1D1), |
167 | DEF_MOD("msi0" , 618, R8A779A0_CLK_MSO), |
168 | DEF_MOD("msi1" , 619, R8A779A0_CLK_MSO), |
169 | DEF_MOD("msi2" , 620, R8A779A0_CLK_MSO), |
170 | DEF_MOD("msi3" , 621, R8A779A0_CLK_MSO), |
171 | DEF_MOD("msi4" , 622, R8A779A0_CLK_MSO), |
172 | DEF_MOD("msi5" , 623, R8A779A0_CLK_MSO), |
173 | DEF_MOD("pwm0" , 628, R8A779A0_CLK_S1D8), |
174 | DEF_MOD("rpc-if" , 629, R8A779A0_CLK_RPCD2), |
175 | DEF_MOD("scif0" , 702, R8A779A0_CLK_S1D8), |
176 | DEF_MOD("scif1" , 703, R8A779A0_CLK_S1D8), |
177 | DEF_MOD("scif3" , 704, R8A779A0_CLK_S1D8), |
178 | DEF_MOD("scif4" , 705, R8A779A0_CLK_S1D8), |
179 | DEF_MOD("sdhi0" , 706, R8A779A0_CLK_SD0), |
180 | DEF_MOD("sys-dmac1" , 709, R8A779A0_CLK_S1D2), |
181 | DEF_MOD("sys-dmac2" , 710, R8A779A0_CLK_S1D2), |
182 | DEF_MOD("tmu0" , 713, R8A779A0_CLK_CL16MCK), |
183 | DEF_MOD("tmu1" , 714, R8A779A0_CLK_S1D4), |
184 | DEF_MOD("tmu2" , 715, R8A779A0_CLK_S1D4), |
185 | DEF_MOD("tmu3" , 716, R8A779A0_CLK_S1D4), |
186 | DEF_MOD("tmu4" , 717, R8A779A0_CLK_S1D4), |
187 | DEF_MOD("tpu0" , 718, R8A779A0_CLK_S1D8), |
188 | DEF_MOD("vin00" , 730, R8A779A0_CLK_S1D1), |
189 | DEF_MOD("vin01" , 731, R8A779A0_CLK_S1D1), |
190 | DEF_MOD("vin02" , 800, R8A779A0_CLK_S1D1), |
191 | DEF_MOD("vin03" , 801, R8A779A0_CLK_S1D1), |
192 | DEF_MOD("vin04" , 802, R8A779A0_CLK_S1D1), |
193 | DEF_MOD("vin05" , 803, R8A779A0_CLK_S1D1), |
194 | DEF_MOD("vin06" , 804, R8A779A0_CLK_S1D1), |
195 | DEF_MOD("vin07" , 805, R8A779A0_CLK_S1D1), |
196 | DEF_MOD("vin10" , 806, R8A779A0_CLK_S1D1), |
197 | DEF_MOD("vin11" , 807, R8A779A0_CLK_S1D1), |
198 | DEF_MOD("vin12" , 808, R8A779A0_CLK_S1D1), |
199 | DEF_MOD("vin13" , 809, R8A779A0_CLK_S1D1), |
200 | DEF_MOD("vin14" , 810, R8A779A0_CLK_S1D1), |
201 | DEF_MOD("vin15" , 811, R8A779A0_CLK_S1D1), |
202 | DEF_MOD("vin16" , 812, R8A779A0_CLK_S1D1), |
203 | DEF_MOD("vin17" , 813, R8A779A0_CLK_S1D1), |
204 | DEF_MOD("vin20" , 814, R8A779A0_CLK_S1D1), |
205 | DEF_MOD("vin21" , 815, R8A779A0_CLK_S1D1), |
206 | DEF_MOD("vin22" , 816, R8A779A0_CLK_S1D1), |
207 | DEF_MOD("vin23" , 817, R8A779A0_CLK_S1D1), |
208 | DEF_MOD("vin24" , 818, R8A779A0_CLK_S1D1), |
209 | DEF_MOD("vin25" , 819, R8A779A0_CLK_S1D1), |
210 | DEF_MOD("vin26" , 820, R8A779A0_CLK_S1D1), |
211 | DEF_MOD("vin27" , 821, R8A779A0_CLK_S1D1), |
212 | DEF_MOD("vin30" , 822, R8A779A0_CLK_S1D1), |
213 | DEF_MOD("vin31" , 823, R8A779A0_CLK_S1D1), |
214 | DEF_MOD("vin32" , 824, R8A779A0_CLK_S1D1), |
215 | DEF_MOD("vin33" , 825, R8A779A0_CLK_S1D1), |
216 | DEF_MOD("vin34" , 826, R8A779A0_CLK_S1D1), |
217 | DEF_MOD("vin35" , 827, R8A779A0_CLK_S1D1), |
218 | DEF_MOD("vin36" , 828, R8A779A0_CLK_S1D1), |
219 | DEF_MOD("vin37" , 829, R8A779A0_CLK_S1D1), |
220 | DEF_MOD("vspd0" , 830, R8A779A0_CLK_S3D1), |
221 | DEF_MOD("vspd1" , 831, R8A779A0_CLK_S3D1), |
222 | DEF_MOD("rwdt" , 907, R8A779A0_CLK_R), |
223 | DEF_MOD("cmt0" , 910, R8A779A0_CLK_R), |
224 | DEF_MOD("cmt1" , 911, R8A779A0_CLK_R), |
225 | DEF_MOD("cmt2" , 912, R8A779A0_CLK_R), |
226 | DEF_MOD("cmt3" , 913, R8A779A0_CLK_R), |
227 | DEF_MOD("pfc0" , 915, R8A779A0_CLK_CP), |
228 | DEF_MOD("pfc1" , 916, R8A779A0_CLK_CP), |
229 | DEF_MOD("pfc2" , 917, R8A779A0_CLK_CP), |
230 | DEF_MOD("pfc3" , 918, R8A779A0_CLK_CP), |
231 | DEF_MOD("tsc" , 919, R8A779A0_CLK_CL16MCK), |
232 | DEF_MOD("vspx0" , 1028, R8A779A0_CLK_S1D1), |
233 | DEF_MOD("vspx1" , 1029, R8A779A0_CLK_S1D1), |
234 | DEF_MOD("vspx2" , 1030, R8A779A0_CLK_S1D1), |
235 | DEF_MOD("vspx3" , 1031, R8A779A0_CLK_S1D1), |
236 | }; |
237 | |
238 | static const unsigned int r8a779a0_crit_mod_clks[] __initconst = { |
239 | MOD_CLK_ID(907), /* RWDT */ |
240 | }; |
241 | |
242 | /* |
243 | * CPG Clock Data |
244 | */ |
245 | /* |
246 | * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC |
247 | * 14 13 (MHz) 21 31 |
248 | * ---------------------------------------------------------------- |
249 | * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 |
250 | * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 |
251 | * 1 0 Prohibited setting |
252 | * 1 1 33.33 / 2 x128 x216 x128 x144 x192 /32 |
253 | */ |
254 | #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ |
255 | (((md) & BIT(13)) >> 13)) |
256 | static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { |
257 | /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ |
258 | { 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, }, |
259 | { 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, }, |
260 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
261 | { 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, }, |
262 | }; |
263 | |
264 | |
265 | static int __init r8a779a0_cpg_mssr_init(struct device *dev) |
266 | { |
267 | const struct rcar_gen4_cpg_pll_config *cpg_pll_config; |
268 | u32 cpg_mode; |
269 | int error; |
270 | |
271 | error = rcar_rst_read_mode_pins(mode: &cpg_mode); |
272 | if (error) |
273 | return error; |
274 | |
275 | cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)]; |
276 | |
277 | return rcar_gen4_cpg_init(config: cpg_pll_config, clk_extalr: CLK_EXTALR, mode: cpg_mode); |
278 | } |
279 | |
280 | const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = { |
281 | /* Core Clocks */ |
282 | .core_clks = r8a779a0_core_clks, |
283 | .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks), |
284 | .last_dt_core_clk = LAST_DT_CORE_CLK, |
285 | .num_total_core_clks = MOD_CLK_BASE, |
286 | |
287 | /* Module Clocks */ |
288 | .mod_clks = r8a779a0_mod_clks, |
289 | .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks), |
290 | .num_hw_mod_clks = 15 * 32, |
291 | |
292 | /* Critical Module Clocks */ |
293 | .crit_mod_clks = r8a779a0_crit_mod_clks, |
294 | .num_crit_mod_clks = ARRAY_SIZE(r8a779a0_crit_mod_clks), |
295 | |
296 | /* Callbacks */ |
297 | .init = r8a779a0_cpg_mssr_init, |
298 | .cpg_clk_register = rcar_gen4_cpg_clk_register, |
299 | |
300 | .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, |
301 | }; |
302 | |