1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * R-Car Gen4 Clock Pulse Generator
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 *
7 */
8
9#ifndef __CLK_RENESAS_RCAR_GEN4_CPG_H__
10#define __CLK_RENESAS_RCAR_GEN4_CPG_H__
11
12enum rcar_gen4_clk_types {
13 CLK_TYPE_GEN4_MAIN = CLK_TYPE_CUSTOM,
14 CLK_TYPE_GEN4_PLL1,
15 CLK_TYPE_GEN4_PLL2,
16 CLK_TYPE_GEN4_PLL2_VAR,
17 CLK_TYPE_GEN4_PLL2X_3X, /* r8a779a0 only */
18 CLK_TYPE_GEN4_PLL3,
19 CLK_TYPE_GEN4_PLL4,
20 CLK_TYPE_GEN4_PLL5,
21 CLK_TYPE_GEN4_PLL6,
22 CLK_TYPE_GEN4_SDSRC,
23 CLK_TYPE_GEN4_SDH,
24 CLK_TYPE_GEN4_SD,
25 CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */
26 CLK_TYPE_GEN4_Z,
27 CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */
28 CLK_TYPE_GEN4_RPCSRC,
29 CLK_TYPE_GEN4_RPC,
30 CLK_TYPE_GEN4_RPCD2,
31
32 /* SoC specific definitions start here */
33 CLK_TYPE_GEN4_SOC_BASE,
34};
35
36#define DEF_GEN4_SDH(_name, _id, _parent, _offset) \
37 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset)
38
39#define DEF_GEN4_SD(_name, _id, _parent, _offset) \
40 DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset)
41
42#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
43 DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \
44 (_parent0) << 16 | (_parent1), \
45 .div = (_div0) << 16 | (_div1), .offset = _md)
46
47#define DEF_GEN4_OSC(_name, _id, _parent, _div) \
48 DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div)
49
50#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \
51 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
52
53struct rcar_gen4_cpg_pll_config {
54 u8 extal_div;
55 u8 pll1_mult;
56 u8 pll1_div;
57 u8 pll2_mult;
58 u8 pll2_div;
59 u8 pll3_mult;
60 u8 pll3_div;
61 u8 pll4_mult;
62 u8 pll4_div;
63 u8 pll5_mult;
64 u8 pll5_div;
65 u8 pll6_mult;
66 u8 pll6_div;
67 u8 osc_prediv;
68};
69
70#define CPG_RPCCKCR 0x874
71#define SD0CKCR1 0x8a4
72
73struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
74 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
75 struct clk **clks, void __iomem *base,
76 struct raw_notifier_head *notifiers);
77int rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
78 unsigned int clk_extalr, u32 mode);
79
80#endif
81

source code of linux/drivers/clk/renesas/rcar-gen4-cpg.h