1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * RZ/G2UL CPG driver |
4 | * |
5 | * Copyright (C) 2022 Renesas Electronics Corp. |
6 | */ |
7 | |
8 | #include <linux/clk-provider.h> |
9 | #include <linux/device.h> |
10 | #include <linux/init.h> |
11 | #include <linux/kernel.h> |
12 | |
13 | #include <dt-bindings/clock/r9a07g043-cpg.h> |
14 | |
15 | #include "rzg2l-cpg.h" |
16 | |
17 | /* Specific registers. */ |
18 | #define CPG_PL2SDHI_DSEL (0x218) |
19 | |
20 | /* Clock select configuration. */ |
21 | #define SEL_SDHI0 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 0, 2) |
22 | #define SEL_SDHI1 SEL_PLL_PACK(CPG_PL2SDHI_DSEL, 4, 2) |
23 | |
24 | /* Clock status configuration. */ |
25 | #define SEL_SDHI0_STS SEL_PLL_PACK(CPG_CLKSTATUS, 28, 1) |
26 | #define SEL_SDHI1_STS SEL_PLL_PACK(CPG_CLKSTATUS, 29, 1) |
27 | |
28 | enum clk_ids { |
29 | /* Core Clock Outputs exported to DT */ |
30 | LAST_DT_CORE_CLK = R9A07G043_CLK_P0_DIV2, |
31 | |
32 | /* External Input Clocks */ |
33 | CLK_EXTAL, |
34 | |
35 | /* Internal Core Clocks */ |
36 | CLK_OSC_DIV1000, |
37 | CLK_PLL1, |
38 | CLK_PLL2, |
39 | CLK_PLL2_DIV2, |
40 | CLK_PLL2_DIV2_8, |
41 | CLK_PLL2_DIV2_10, |
42 | CLK_PLL3, |
43 | CLK_PLL3_400, |
44 | CLK_PLL3_533, |
45 | CLK_PLL3_DIV2, |
46 | CLK_PLL3_DIV2_4, |
47 | CLK_PLL3_DIV2_4_2, |
48 | CLK_SEL_PLL3_3, |
49 | CLK_DIV_PLL3_C, |
50 | #ifdef CONFIG_ARM64 |
51 | CLK_M2_DIV2, |
52 | CLK_PLL5, |
53 | CLK_PLL5_500, |
54 | CLK_PLL5_250, |
55 | #endif |
56 | CLK_PLL6, |
57 | CLK_PLL6_250, |
58 | CLK_P1_DIV2, |
59 | CLK_PLL2_800, |
60 | CLK_PLL2_SDHI_533, |
61 | CLK_PLL2_SDHI_400, |
62 | CLK_PLL2_SDHI_266, |
63 | CLK_SD0_DIV4, |
64 | CLK_SD1_DIV4, |
65 | |
66 | /* Module Clocks */ |
67 | MOD_CLK_BASE, |
68 | }; |
69 | |
70 | /* Divider tables */ |
71 | static const struct clk_div_table dtable_1_8[] = { |
72 | {0, 1}, |
73 | {1, 2}, |
74 | {2, 4}, |
75 | {3, 8}, |
76 | {0, 0}, |
77 | }; |
78 | |
79 | static const struct clk_div_table dtable_1_32[] = { |
80 | {0, 1}, |
81 | {1, 2}, |
82 | {2, 4}, |
83 | {3, 8}, |
84 | {4, 32}, |
85 | {0, 0}, |
86 | }; |
87 | |
88 | /* Mux clock tables */ |
89 | static const char * const sel_pll3_3[] = { ".pll3_533" , ".pll3_400" }; |
90 | static const char * const sel_pll6_2[] = { ".pll6_250" , ".pll5_250" }; |
91 | static const char * const sel_sdhi[] = { ".clk_533" , ".clk_400" , ".clk_266" }; |
92 | |
93 | static const u32 mtable_sdhi[] = { 1, 2, 3 }; |
94 | |
95 | static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { |
96 | /* External Clock Inputs */ |
97 | DEF_INPUT("extal" , CLK_EXTAL), |
98 | |
99 | /* Internal Core Clocks */ |
100 | DEF_FIXED(".osc" , R9A07G043_OSCCLK, CLK_EXTAL, 1, 1), |
101 | DEF_FIXED(".osc_div1000" , CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), |
102 | DEF_SAMPLL(".pll1" , CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)), |
103 | DEF_FIXED(".pll2" , CLK_PLL2, CLK_EXTAL, 200, 3), |
104 | DEF_FIXED(".pll2_div2" , CLK_PLL2_DIV2, CLK_PLL2, 1, 2), |
105 | DEF_FIXED(".clk_800" , CLK_PLL2_800, CLK_PLL2, 1, 2), |
106 | DEF_FIXED(".clk_533" , CLK_PLL2_SDHI_533, CLK_PLL2, 1, 3), |
107 | DEF_FIXED(".clk_400" , CLK_PLL2_SDHI_400, CLK_PLL2_800, 1, 2), |
108 | DEF_FIXED(".clk_266" , CLK_PLL2_SDHI_266, CLK_PLL2_SDHI_533, 1, 2), |
109 | DEF_FIXED(".pll2_div2_8" , CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), |
110 | DEF_FIXED(".pll2_div2_10" , CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10), |
111 | DEF_FIXED(".pll3" , CLK_PLL3, CLK_EXTAL, 200, 3), |
112 | DEF_FIXED(".pll3_div2" , CLK_PLL3_DIV2, CLK_PLL3, 1, 2), |
113 | DEF_FIXED(".pll3_div2_4" , CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), |
114 | DEF_FIXED(".pll3_div2_4_2" , CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2), |
115 | DEF_FIXED(".pll3_400" , CLK_PLL3_400, CLK_PLL3, 1, 4), |
116 | DEF_FIXED(".pll3_533" , CLK_PLL3_533, CLK_PLL3, 1, 3), |
117 | DEF_MUX_RO(".sel_pll3_3" , CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3), |
118 | DEF_DIV("divpl3c" , CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32), |
119 | #ifdef CONFIG_ARM64 |
120 | DEF_FIXED(".pll5" , CLK_PLL5, CLK_EXTAL, 125, 1), |
121 | DEF_FIXED(".pll5_500" , CLK_PLL5_500, CLK_PLL5, 1, 6), |
122 | DEF_FIXED(".pll5_250" , CLK_PLL5_250, CLK_PLL5_500, 1, 2), |
123 | #endif |
124 | DEF_FIXED(".pll6" , CLK_PLL6, CLK_EXTAL, 125, 6), |
125 | DEF_FIXED(".pll6_250" , CLK_PLL6_250, CLK_PLL6, 1, 2), |
126 | |
127 | /* Core output clk */ |
128 | DEF_DIV("I" , R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8), |
129 | DEF_DIV("P0" , R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32), |
130 | DEF_FIXED("P0_DIV2" , R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2), |
131 | DEF_FIXED("TSU" , R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1), |
132 | DEF_DIV("P1" , R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32), |
133 | DEF_FIXED("P1_DIV2" , CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2), |
134 | DEF_DIV("P2" , R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32), |
135 | DEF_FIXED("M0" , R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), |
136 | DEF_FIXED("ZT" , R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1), |
137 | DEF_MUX("HP" , R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2), |
138 | DEF_FIXED("SPI0" , R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2), |
139 | DEF_FIXED("SPI1" , R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4), |
140 | DEF_SD_MUX("SD0" , R9A07G043_CLK_SD0, SEL_SDHI0, SEL_SDHI0_STS, sel_sdhi, |
141 | mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), |
142 | DEF_SD_MUX("SD1" , R9A07G043_CLK_SD1, SEL_SDHI1, SEL_SDHI1_STS, sel_sdhi, |
143 | mtable_sdhi, 0, rzg2l_cpg_sd_clk_mux_notifier), |
144 | DEF_FIXED("SD0_DIV4" , CLK_SD0_DIV4, R9A07G043_CLK_SD0, 1, 4), |
145 | DEF_FIXED("SD1_DIV4" , CLK_SD1_DIV4, R9A07G043_CLK_SD1, 1, 4), |
146 | #ifdef CONFIG_ARM64 |
147 | DEF_FIXED("M2" , R9A07G043_CLK_M2, CLK_PLL3_533, 1, 2), |
148 | DEF_FIXED("M2_DIV2" , CLK_M2_DIV2, R9A07G043_CLK_M2, 1, 2), |
149 | #endif |
150 | }; |
151 | |
152 | static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { |
153 | #ifdef CONFIG_ARM64 |
154 | DEF_MOD("gic" , R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, |
155 | 0x514, 0), |
156 | DEF_MOD("ia55_pclk" , R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, |
157 | 0x518, 0), |
158 | DEF_MOD("ia55_clk" , R9A07G043_IA55_CLK, R9A07G043_CLK_P1, |
159 | 0x518, 1), |
160 | #endif |
161 | #ifdef CONFIG_RISCV |
162 | DEF_MOD("iax45_pclk" , R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2, |
163 | 0x518, 0), |
164 | DEF_MOD("iax45_clk" , R9A07G043_IAX45_CLK, R9A07G043_CLK_P1, |
165 | 0x518, 1), |
166 | #endif |
167 | DEF_MOD("dmac_aclk" , R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, |
168 | 0x52c, 0), |
169 | DEF_MOD("dmac_pclk" , R9A07G043_DMAC_PCLK, CLK_P1_DIV2, |
170 | 0x52c, 1), |
171 | DEF_MOD("ostm0_pclk" , R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0, |
172 | 0x534, 0), |
173 | DEF_MOD("ostm1_pclk" , R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0, |
174 | 0x534, 1), |
175 | DEF_MOD("ostm2_pclk" , R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, |
176 | 0x534, 2), |
177 | DEF_MOD("mtu_x_mck" , R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0, |
178 | 0x538, 0), |
179 | DEF_MOD("wdt0_pclk" , R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, |
180 | 0x548, 0), |
181 | DEF_MOD("wdt0_clk" , R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, |
182 | 0x548, 1), |
183 | DEF_MOD("spi_clk2" , R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1, |
184 | 0x550, 0), |
185 | DEF_MOD("spi_clk" , R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0, |
186 | 0x550, 1), |
187 | DEF_MOD("sdhi0_imclk" , R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, |
188 | 0x554, 0), |
189 | DEF_MOD("sdhi0_imclk2" , R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, |
190 | 0x554, 1), |
191 | DEF_MOD("sdhi0_clk_hs" , R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0, |
192 | 0x554, 2), |
193 | DEF_MOD("sdhi0_aclk" , R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1, |
194 | 0x554, 3), |
195 | DEF_MOD("sdhi1_imclk" , R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4, |
196 | 0x554, 4), |
197 | DEF_MOD("sdhi1_imclk2" , R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4, |
198 | 0x554, 5), |
199 | DEF_MOD("sdhi1_clk_hs" , R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1, |
200 | 0x554, 6), |
201 | DEF_MOD("sdhi1_aclk" , R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1, |
202 | 0x554, 7), |
203 | #ifdef CONFIG_ARM64 |
204 | DEF_MOD("cru_sysclk" , R9A07G043_CRU_SYSCLK, CLK_M2_DIV2, |
205 | 0x564, 0), |
206 | DEF_MOD("cru_vclk" , R9A07G043_CRU_VCLK, R9A07G043_CLK_M2, |
207 | 0x564, 1), |
208 | DEF_MOD("cru_pclk" , R9A07G043_CRU_PCLK, R9A07G043_CLK_ZT, |
209 | 0x564, 2), |
210 | DEF_MOD("cru_aclk" , R9A07G043_CRU_ACLK, R9A07G043_CLK_M0, |
211 | 0x564, 3), |
212 | #endif |
213 | DEF_MOD("ssi0_pclk" , R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0, |
214 | 0x570, 0), |
215 | DEF_MOD("ssi0_sfr" , R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0, |
216 | 0x570, 1), |
217 | DEF_MOD("ssi1_pclk" , R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0, |
218 | 0x570, 2), |
219 | DEF_MOD("ssi1_sfr" , R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0, |
220 | 0x570, 3), |
221 | DEF_MOD("ssi2_pclk" , R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0, |
222 | 0x570, 4), |
223 | DEF_MOD("ssi2_sfr" , R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0, |
224 | 0x570, 5), |
225 | DEF_MOD("ssi3_pclk" , R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0, |
226 | 0x570, 6), |
227 | DEF_MOD("ssi3_sfr" , R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0, |
228 | 0x570, 7), |
229 | DEF_MOD("usb0_host" , R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1, |
230 | 0x578, 0), |
231 | DEF_MOD("usb1_host" , R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1, |
232 | 0x578, 1), |
233 | DEF_MOD("usb0_func" , R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1, |
234 | 0x578, 2), |
235 | DEF_MOD("usb_pclk" , R9A07G043_USB_PCLK, R9A07G043_CLK_P1, |
236 | 0x578, 3), |
237 | DEF_COUPLED("eth0_axi" , R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, |
238 | 0x57c, 0), |
239 | DEF_COUPLED("eth0_chi" , R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, |
240 | 0x57c, 0), |
241 | DEF_COUPLED("eth1_axi" , R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0, |
242 | 0x57c, 1), |
243 | DEF_COUPLED("eth1_chi" , R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT, |
244 | 0x57c, 1), |
245 | DEF_MOD("i2c0" , R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0, |
246 | 0x580, 0), |
247 | DEF_MOD("i2c1" , R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0, |
248 | 0x580, 1), |
249 | DEF_MOD("i2c2" , R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0, |
250 | 0x580, 2), |
251 | DEF_MOD("i2c3" , R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0, |
252 | 0x580, 3), |
253 | DEF_MOD("scif0" , R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, |
254 | 0x584, 0), |
255 | DEF_MOD("scif1" , R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, |
256 | 0x584, 1), |
257 | DEF_MOD("scif2" , R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0, |
258 | 0x584, 2), |
259 | DEF_MOD("scif3" , R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0, |
260 | 0x584, 3), |
261 | DEF_MOD("scif4" , R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0, |
262 | 0x584, 4), |
263 | DEF_MOD("sci0" , R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0, |
264 | 0x588, 0), |
265 | DEF_MOD("sci1" , R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, |
266 | 0x588, 1), |
267 | DEF_MOD("rspi0" , R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0, |
268 | 0x590, 0), |
269 | DEF_MOD("rspi1" , R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0, |
270 | 0x590, 1), |
271 | DEF_MOD("rspi2" , R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0, |
272 | 0x590, 2), |
273 | DEF_MOD("canfd" , R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0, |
274 | 0x594, 0), |
275 | DEF_MOD("gpio" , R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, |
276 | 0x598, 0), |
277 | DEF_MOD("adc_adclk" , R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU, |
278 | 0x5a8, 0), |
279 | DEF_MOD("adc_pclk" , R9A07G043_ADC_PCLK, R9A07G043_CLK_P0, |
280 | 0x5a8, 1), |
281 | DEF_MOD("tsu_pclk" , R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU, |
282 | 0x5ac, 0), |
283 | }; |
284 | |
285 | static struct rzg2l_reset r9a07g043_resets[] = { |
286 | #ifdef CONFIG_ARM64 |
287 | DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0), |
288 | DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1), |
289 | DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0), |
290 | #endif |
291 | #ifdef CONFIG_RISCV |
292 | DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0), |
293 | #endif |
294 | DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0), |
295 | DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1), |
296 | DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0), |
297 | DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1), |
298 | DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2), |
299 | DEF_RST(R9A07G043_MTU_X_PRESET_MTU3, 0x838, 0), |
300 | DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0), |
301 | DEF_RST(R9A07G043_SPI_RST, 0x850, 0), |
302 | DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0), |
303 | DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1), |
304 | #ifdef CONFIG_ARM64 |
305 | DEF_RST(R9A07G043_CRU_CMN_RSTB, 0x864, 0), |
306 | DEF_RST(R9A07G043_CRU_PRESETN, 0x864, 1), |
307 | DEF_RST(R9A07G043_CRU_ARESETN, 0x864, 2), |
308 | #endif |
309 | DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0), |
310 | DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1), |
311 | DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2), |
312 | DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3), |
313 | DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0), |
314 | DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1), |
315 | DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2), |
316 | DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3), |
317 | DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0), |
318 | DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1), |
319 | DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0), |
320 | DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1), |
321 | DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2), |
322 | DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3), |
323 | DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0), |
324 | DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1), |
325 | DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2), |
326 | DEF_RST(R9A07G043_SCIF3_RST_SYSTEM_N, 0x884, 3), |
327 | DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4), |
328 | DEF_RST(R9A07G043_SCI0_RST, 0x888, 0), |
329 | DEF_RST(R9A07G043_SCI1_RST, 0x888, 1), |
330 | DEF_RST(R9A07G043_RSPI0_RST, 0x890, 0), |
331 | DEF_RST(R9A07G043_RSPI1_RST, 0x890, 1), |
332 | DEF_RST(R9A07G043_RSPI2_RST, 0x890, 2), |
333 | DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0), |
334 | DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1), |
335 | DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0), |
336 | DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1), |
337 | DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2), |
338 | DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0), |
339 | DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1), |
340 | DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0), |
341 | }; |
342 | |
343 | static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { |
344 | #ifdef CONFIG_ARM64 |
345 | MOD_CLK_BASE + R9A07G043_GIC600_GICCLK, |
346 | MOD_CLK_BASE + R9A07G043_IA55_CLK, |
347 | #endif |
348 | #ifdef CONFIG_RISCV |
349 | MOD_CLK_BASE + R9A07G043_IAX45_CLK, |
350 | #endif |
351 | MOD_CLK_BASE + R9A07G043_DMAC_ACLK, |
352 | }; |
353 | |
354 | #ifdef CONFIG_ARM64 |
355 | static const unsigned int r9a07g043_no_pm_mod_clks[] = { |
356 | MOD_CLK_BASE + R9A07G043_CRU_SYSCLK, |
357 | MOD_CLK_BASE + R9A07G043_CRU_VCLK, |
358 | }; |
359 | #endif |
360 | |
361 | const struct rzg2l_cpg_info r9a07g043_cpg_info = { |
362 | /* Core Clocks */ |
363 | .core_clks = r9a07g043_core_clks, |
364 | .num_core_clks = ARRAY_SIZE(r9a07g043_core_clks), |
365 | .last_dt_core_clk = LAST_DT_CORE_CLK, |
366 | .num_total_core_clks = MOD_CLK_BASE, |
367 | |
368 | /* Critical Module Clocks */ |
369 | .crit_mod_clks = r9a07g043_crit_mod_clks, |
370 | .num_crit_mod_clks = ARRAY_SIZE(r9a07g043_crit_mod_clks), |
371 | |
372 | /* Module Clocks */ |
373 | .mod_clks = r9a07g043_mod_clks, |
374 | .num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks), |
375 | #ifdef CONFIG_ARM64 |
376 | .num_hw_mod_clks = R9A07G043_TSU_PCLK + 1, |
377 | |
378 | /* No PM Module Clocks */ |
379 | .no_pm_mod_clks = r9a07g043_no_pm_mod_clks, |
380 | .num_no_pm_mod_clks = ARRAY_SIZE(r9a07g043_no_pm_mod_clks), |
381 | #endif |
382 | #ifdef CONFIG_RISCV |
383 | .num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1, |
384 | #endif |
385 | |
386 | /* Resets */ |
387 | .resets = r9a07g043_resets, |
388 | #ifdef CONFIG_ARM64 |
389 | .num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */ |
390 | #endif |
391 | #ifdef CONFIG_RISCV |
392 | .num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */ |
393 | #endif |
394 | |
395 | .has_clk_mon_regs = true, |
396 | }; |
397 | |