1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * RZ/G2L Clock Pulse Generator |
4 | * |
5 | * Copyright (C) 2021 Renesas Electronics Corp. |
6 | * |
7 | */ |
8 | |
9 | #ifndef __RENESAS_RZG2L_CPG_H__ |
10 | #define __RENESAS_RZG2L_CPG_H__ |
11 | |
12 | #include <linux/notifier.h> |
13 | |
14 | #define CPG_SIPLL5_STBY (0x140) |
15 | #define CPG_SIPLL5_CLK1 (0x144) |
16 | #define CPG_SIPLL5_CLK3 (0x14C) |
17 | #define CPG_SIPLL5_CLK4 (0x150) |
18 | #define CPG_SIPLL5_CLK5 (0x154) |
19 | #define CPG_SIPLL5_MON (0x15C) |
20 | #define CPG_PL1_DDIV (0x200) |
21 | #define CPG_PL2_DDIV (0x204) |
22 | #define CPG_PL3A_DDIV (0x208) |
23 | #define CPG_PL6_DDIV (0x210) |
24 | #define CPG_CLKSTATUS (0x280) |
25 | #define CPG_PL3_SSEL (0x408) |
26 | #define CPG_PL6_SSEL (0x414) |
27 | #define CPG_PL6_ETH_SSEL (0x418) |
28 | #define CPG_PL5_SDIV (0x420) |
29 | #define CPG_RST_MON (0x680) |
30 | #define CPG_OTHERFUNC1_REG (0xBE8) |
31 | |
32 | #define CPG_SIPLL5_STBY_RESETB BIT(0) |
33 | #define CPG_SIPLL5_STBY_RESETB_WEN BIT(16) |
34 | #define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18) |
35 | #define CPG_SIPLL5_STBY_DOWNSPREAD_WEN BIT(20) |
36 | #define CPG_SIPLL5_CLK4_RESV_LSB (0xFF) |
37 | #define CPG_SIPLL5_MON_PLL5_LOCK BIT(4) |
38 | |
39 | #define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16) |
40 | |
41 | #define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16) |
42 | #define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24) |
43 | |
44 | #define CPG_CLKSTATUS_SELSDHI0_STS BIT(28) |
45 | #define CPG_CLKSTATUS_SELSDHI1_STS BIT(29) |
46 | |
47 | /* n = 0/1/2 for PLL1/4/6 */ |
48 | #define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n)) |
49 | #define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n)) |
50 | |
51 | #define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12) |
52 | |
53 | #define DDIV_PACK(offset, bitpos, size) \ |
54 | (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) |
55 | #define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2) |
56 | #define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3) |
57 | #define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2) |
58 | #define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3) |
59 | #define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3) |
60 | #define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3) |
61 | #define DIVGPU DDIV_PACK(CPG_PL6_DDIV, 0, 2) |
62 | |
63 | #define SEL_PLL_PACK(offset, bitpos, size) \ |
64 | (((offset) << 20) | ((bitpos) << 12) | ((size) << 8)) |
65 | |
66 | #define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1) |
67 | #define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1) |
68 | #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) |
69 | #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) |
70 | |
71 | #define EXTAL_FREQ_IN_MEGA_HZ (24) |
72 | |
73 | /** |
74 | * Definitions of CPG Core Clocks |
75 | * |
76 | * These include: |
77 | * - Clock outputs exported to DT |
78 | * - External input clocks |
79 | * - Internal CPG clocks |
80 | */ |
81 | struct cpg_core_clk { |
82 | const char *name; |
83 | unsigned int id; |
84 | unsigned int parent; |
85 | unsigned int div; |
86 | unsigned int mult; |
87 | unsigned int type; |
88 | unsigned int conf; |
89 | unsigned int sconf; |
90 | const struct clk_div_table *dtable; |
91 | const u32 *mtable; |
92 | const unsigned long invalid_rate; |
93 | const unsigned long max_rate; |
94 | const char * const *parent_names; |
95 | notifier_fn_t notifier; |
96 | u32 flag; |
97 | u32 mux_flags; |
98 | int num_parents; |
99 | }; |
100 | |
101 | enum clk_types { |
102 | /* Generic */ |
103 | CLK_TYPE_IN, /* External Clock Input */ |
104 | CLK_TYPE_FF, /* Fixed Factor Clock */ |
105 | CLK_TYPE_SAM_PLL, |
106 | CLK_TYPE_G3S_PLL, |
107 | |
108 | /* Clock with divider */ |
109 | CLK_TYPE_DIV, |
110 | CLK_TYPE_G3S_DIV, |
111 | |
112 | /* Clock with clock source selector */ |
113 | CLK_TYPE_MUX, |
114 | |
115 | /* Clock with SD clock source selector */ |
116 | CLK_TYPE_SD_MUX, |
117 | |
118 | /* Clock for SIPLL5 */ |
119 | CLK_TYPE_SIPLL5, |
120 | |
121 | /* Clock for PLL5_4 clock source selector */ |
122 | CLK_TYPE_PLL5_4_MUX, |
123 | |
124 | /* Clock for DSI divider */ |
125 | CLK_TYPE_DSI_DIV, |
126 | |
127 | }; |
128 | |
129 | #define DEF_TYPE(_name, _id, _type...) \ |
130 | { .name = _name, .id = _id, .type = _type } |
131 | #define DEF_BASE(_name, _id, _type, _parent...) \ |
132 | DEF_TYPE(_name, _id, _type, .parent = _parent) |
133 | #define DEF_SAMPLL(_name, _id, _parent, _conf) \ |
134 | DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) |
135 | #define DEF_G3S_PLL(_name, _id, _parent, _conf) \ |
136 | DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf) |
137 | #define DEF_INPUT(_name, _id) \ |
138 | DEF_TYPE(_name, _id, CLK_TYPE_IN) |
139 | #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ |
140 | DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) |
141 | #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ |
142 | DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ |
143 | .parent = _parent, .dtable = _dtable, \ |
144 | .flag = CLK_DIVIDER_HIWORD_MASK) |
145 | #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \ |
146 | DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \ |
147 | .parent = _parent, .dtable = _dtable, \ |
148 | .flag = CLK_DIVIDER_READ_ONLY) |
149 | #define DEF_G3S_DIV(_name, _id, _parent, _conf, _sconf, _dtable, _invalid_rate, \ |
150 | _max_rate, _clk_flags, _notif) \ |
151 | DEF_TYPE(_name, _id, CLK_TYPE_G3S_DIV, .conf = _conf, .sconf = _sconf, \ |
152 | .parent = _parent, .dtable = _dtable, \ |
153 | .invalid_rate = _invalid_rate, \ |
154 | .max_rate = _max_rate, .flag = (_clk_flags), \ |
155 | .notifier = _notif) |
156 | #define DEF_MUX(_name, _id, _conf, _parent_names) \ |
157 | DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ |
158 | .parent_names = _parent_names, \ |
159 | .num_parents = ARRAY_SIZE(_parent_names), \ |
160 | .mux_flags = CLK_MUX_HIWORD_MASK) |
161 | #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \ |
162 | DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \ |
163 | .parent_names = _parent_names, \ |
164 | .num_parents = ARRAY_SIZE(_parent_names), \ |
165 | .mux_flags = CLK_MUX_READ_ONLY) |
166 | #define DEF_SD_MUX(_name, _id, _conf, _sconf, _parent_names, _mtable, _clk_flags, _notifier) \ |
167 | DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, .sconf = _sconf, \ |
168 | .parent_names = _parent_names, \ |
169 | .num_parents = ARRAY_SIZE(_parent_names), \ |
170 | .mtable = _mtable, .flag = _clk_flags, .notifier = _notifier) |
171 | #define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \ |
172 | DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent) |
173 | #define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names) \ |
174 | DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \ |
175 | .parent_names = _parent_names, \ |
176 | .num_parents = ARRAY_SIZE(_parent_names)) |
177 | #define DEF_DSI_DIV(_name, _id, _parent, _flag) \ |
178 | DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag) |
179 | |
180 | /** |
181 | * struct rzg2l_mod_clk - Module Clocks definitions |
182 | * |
183 | * @name: handle between common and hardware-specific interfaces |
184 | * @id: clock index in array containing all Core and Module Clocks |
185 | * @parent: id of parent clock |
186 | * @off: register offset |
187 | * @bit: ON/MON bit |
188 | * @is_coupled: flag to indicate coupled clock |
189 | */ |
190 | struct rzg2l_mod_clk { |
191 | const char *name; |
192 | unsigned int id; |
193 | unsigned int parent; |
194 | u16 off; |
195 | u8 bit; |
196 | bool is_coupled; |
197 | }; |
198 | |
199 | #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ |
200 | { \ |
201 | .name = _name, \ |
202 | .id = MOD_CLK_BASE + (_id), \ |
203 | .parent = (_parent), \ |
204 | .off = (_off), \ |
205 | .bit = (_bit), \ |
206 | .is_coupled = (_is_coupled), \ |
207 | } |
208 | |
209 | #define DEF_MOD(_name, _id, _parent, _off, _bit) \ |
210 | DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false) |
211 | |
212 | #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ |
213 | DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true) |
214 | |
215 | /** |
216 | * struct rzg2l_reset - Reset definitions |
217 | * |
218 | * @off: register offset |
219 | * @bit: reset bit |
220 | * @monbit: monitor bit in CPG_RST_MON register, -1 if none |
221 | */ |
222 | struct rzg2l_reset { |
223 | u16 off; |
224 | u8 bit; |
225 | s8 monbit; |
226 | }; |
227 | |
228 | #define DEF_RST_MON(_id, _off, _bit, _monbit) \ |
229 | [_id] = { \ |
230 | .off = (_off), \ |
231 | .bit = (_bit), \ |
232 | .monbit = (_monbit) \ |
233 | } |
234 | #define DEF_RST(_id, _off, _bit) \ |
235 | DEF_RST_MON(_id, _off, _bit, -1) |
236 | |
237 | /** |
238 | * struct rzg2l_cpg_info - SoC-specific CPG Description |
239 | * |
240 | * @core_clks: Array of Core Clock definitions |
241 | * @num_core_clks: Number of entries in core_clks[] |
242 | * @last_dt_core_clk: ID of the last Core Clock exported to DT |
243 | * @num_total_core_clks: Total number of Core Clocks (exported + internal) |
244 | * |
245 | * @mod_clks: Array of Module Clock definitions |
246 | * @num_mod_clks: Number of entries in mod_clks[] |
247 | * @num_hw_mod_clks: Number of Module Clocks supported by the hardware |
248 | * |
249 | * @resets: Array of Module Reset definitions |
250 | * @num_resets: Number of entries in resets[] |
251 | * |
252 | * @crit_mod_clks: Array with Module Clock IDs of critical clocks that |
253 | * should not be disabled without a knowledgeable driver |
254 | * @num_crit_mod_clks: Number of entries in crit_mod_clks[] |
255 | * @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers |
256 | */ |
257 | struct rzg2l_cpg_info { |
258 | /* Core Clocks */ |
259 | const struct cpg_core_clk *core_clks; |
260 | unsigned int num_core_clks; |
261 | unsigned int last_dt_core_clk; |
262 | unsigned int num_total_core_clks; |
263 | |
264 | /* Module Clocks */ |
265 | const struct rzg2l_mod_clk *mod_clks; |
266 | unsigned int num_mod_clks; |
267 | unsigned int num_hw_mod_clks; |
268 | |
269 | /* No PM Module Clocks */ |
270 | const unsigned int *no_pm_mod_clks; |
271 | unsigned int num_no_pm_mod_clks; |
272 | |
273 | /* Resets */ |
274 | const struct rzg2l_reset *resets; |
275 | unsigned int num_resets; |
276 | |
277 | /* Critical Module Clocks that should not be disabled */ |
278 | const unsigned int *crit_mod_clks; |
279 | unsigned int num_crit_mod_clks; |
280 | |
281 | bool has_clk_mon_regs; |
282 | }; |
283 | |
284 | extern const struct rzg2l_cpg_info r9a07g043_cpg_info; |
285 | extern const struct rzg2l_cpg_info r9a07g044_cpg_info; |
286 | extern const struct rzg2l_cpg_info r9a07g054_cpg_info; |
287 | extern const struct rzg2l_cpg_info r9a08g045_cpg_info; |
288 | extern const struct rzg2l_cpg_info r9a09g011_cpg_info; |
289 | |
290 | int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data); |
291 | int rzg3s_cpg_div_clk_notifier(struct notifier_block *nb, unsigned long event, void *data); |
292 | |
293 | #endif |
294 | |