1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * RZ/G3S CPG driver |
4 | * |
5 | * Copyright (C) 2023 Renesas Electronics Corp. |
6 | */ |
7 | |
8 | #include <linux/clk-provider.h> |
9 | #include <linux/device.h> |
10 | #include <linux/init.h> |
11 | #include <linux/kernel.h> |
12 | |
13 | #include <dt-bindings/clock/r9a08g045-cpg.h> |
14 | |
15 | #include "rzg2l-cpg.h" |
16 | |
17 | /* RZ/G3S Specific registers. */ |
18 | #define G3S_CPG_PL2_DDIV (0x204) |
19 | #define G3S_CPG_SDHI_DDIV (0x218) |
20 | #define G3S_CPG_PLL_DSEL (0x240) |
21 | #define G3S_CPG_SDHI_DSEL (0x244) |
22 | #define G3S_CLKDIVSTATUS (0x280) |
23 | #define G3S_CLKSELSTATUS (0x284) |
24 | |
25 | /* RZ/G3S Specific division configuration. */ |
26 | #define G3S_DIVPL2B DDIV_PACK(G3S_CPG_PL2_DDIV, 4, 3) |
27 | #define G3S_DIV_SDHI0 DDIV_PACK(G3S_CPG_SDHI_DDIV, 0, 1) |
28 | #define G3S_DIV_SDHI1 DDIV_PACK(G3S_CPG_SDHI_DDIV, 4, 1) |
29 | #define G3S_DIV_SDHI2 DDIV_PACK(G3S_CPG_SDHI_DDIV, 8, 1) |
30 | |
31 | /* RZ/G3S Clock status configuration. */ |
32 | #define G3S_DIVPL1A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 0, 1) |
33 | #define G3S_DIVPL2B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 5, 1) |
34 | #define G3S_DIVPL3A_STS DDIV_PACK(G3S_CLKDIVSTATUS, 8, 1) |
35 | #define G3S_DIVPL3B_STS DDIV_PACK(G3S_CLKDIVSTATUS, 9, 1) |
36 | #define G3S_DIVPL3C_STS DDIV_PACK(G3S_CLKDIVSTATUS, 10, 1) |
37 | #define G3S_DIV_SDHI0_STS DDIV_PACK(G3S_CLKDIVSTATUS, 24, 1) |
38 | #define G3S_DIV_SDHI1_STS DDIV_PACK(G3S_CLKDIVSTATUS, 25, 1) |
39 | #define G3S_DIV_SDHI2_STS DDIV_PACK(G3S_CLKDIVSTATUS, 26, 1) |
40 | |
41 | #define G3S_SEL_PLL4_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 6, 1) |
42 | #define G3S_SEL_SDHI0_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 16, 1) |
43 | #define G3S_SEL_SDHI1_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 17, 1) |
44 | #define G3S_SEL_SDHI2_STS SEL_PLL_PACK(G3S_CLKSELSTATUS, 18, 1) |
45 | |
46 | /* RZ/G3S Specific clocks select. */ |
47 | #define G3S_SEL_PLL4 SEL_PLL_PACK(G3S_CPG_PLL_DSEL, 6, 1) |
48 | #define G3S_SEL_SDHI0 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 0, 2) |
49 | #define G3S_SEL_SDHI1 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 4, 2) |
50 | #define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2) |
51 | |
52 | /* PLL 1/4/6 configuration registers macro. */ |
53 | #define G3S_PLL146_CONF(clk1, clk2) ((clk1) << 22 | (clk2) << 12) |
54 | |
55 | #define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \ |
56 | DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \ |
57 | .parent_names = (_parent_names), \ |
58 | .num_parents = ARRAY_SIZE((_parent_names)), \ |
59 | .mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \ |
60 | .flag = (_clk_flags)) |
61 | |
62 | enum clk_ids { |
63 | /* Core Clock Outputs exported to DT */ |
64 | LAST_DT_CORE_CLK = R9A08G045_SWD, |
65 | |
66 | /* External Input Clocks */ |
67 | CLK_EXTAL, |
68 | |
69 | /* Internal Core Clocks */ |
70 | CLK_OSC_DIV1000, |
71 | CLK_PLL1, |
72 | CLK_PLL2, |
73 | CLK_PLL2_DIV2, |
74 | CLK_PLL2_DIV2_8, |
75 | CLK_PLL2_DIV6, |
76 | CLK_PLL3, |
77 | CLK_PLL3_DIV2, |
78 | CLK_PLL3_DIV2_4, |
79 | CLK_PLL3_DIV2_8, |
80 | CLK_PLL3_DIV6, |
81 | CLK_PLL4, |
82 | CLK_PLL6, |
83 | CLK_PLL6_DIV2, |
84 | CLK_SEL_SDHI0, |
85 | CLK_SEL_SDHI1, |
86 | CLK_SEL_SDHI2, |
87 | CLK_SEL_PLL4, |
88 | CLK_P1_DIV2, |
89 | CLK_P3_DIV2, |
90 | CLK_SD0_DIV4, |
91 | CLK_SD1_DIV4, |
92 | CLK_SD2_DIV4, |
93 | |
94 | /* Module Clocks */ |
95 | MOD_CLK_BASE, |
96 | }; |
97 | |
98 | /* Divider tables */ |
99 | static const struct clk_div_table dtable_1_2[] = { |
100 | { 0, 1 }, |
101 | { 1, 2 }, |
102 | { 0, 0 }, |
103 | }; |
104 | |
105 | static const struct clk_div_table dtable_1_8[] = { |
106 | { 0, 1 }, |
107 | { 1, 2 }, |
108 | { 2, 4 }, |
109 | { 3, 8 }, |
110 | { 0, 0 }, |
111 | }; |
112 | |
113 | static const struct clk_div_table dtable_1_32[] = { |
114 | { 0, 1 }, |
115 | { 1, 2 }, |
116 | { 2, 4 }, |
117 | { 3, 8 }, |
118 | { 4, 32 }, |
119 | { 0, 0 }, |
120 | }; |
121 | |
122 | /* Mux clock names tables. */ |
123 | static const char * const sel_sdhi[] = { ".pll2_div2" , ".pll6" , ".pll2_div6" }; |
124 | static const char * const sel_pll4[] = { ".osc_div1000" , ".pll4" }; |
125 | |
126 | /* Mux clock indices tables. */ |
127 | static const u32 mtable_sd[] = { 0, 2, 3 }; |
128 | static const u32 mtable_pll4[] = { 0, 1 }; |
129 | |
130 | static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = { |
131 | /* External Clock Inputs */ |
132 | DEF_INPUT("extal" , CLK_EXTAL), |
133 | |
134 | /* Internal Core Clocks */ |
135 | DEF_FIXED(".osc_div1000" , CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000), |
136 | DEF_G3S_PLL(".pll1" , CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8)), |
137 | DEF_FIXED(".pll2" , CLK_PLL2, CLK_EXTAL, 200, 3), |
138 | DEF_FIXED(".pll3" , CLK_PLL3, CLK_EXTAL, 200, 3), |
139 | DEF_FIXED(".pll4" , CLK_PLL4, CLK_EXTAL, 100, 3), |
140 | DEF_FIXED(".pll6" , CLK_PLL6, CLK_EXTAL, 125, 6), |
141 | DEF_FIXED(".pll2_div2" , CLK_PLL2_DIV2, CLK_PLL2, 1, 2), |
142 | DEF_FIXED(".pll2_div2_8" , CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8), |
143 | DEF_FIXED(".pll2_div6" , CLK_PLL2_DIV6, CLK_PLL2, 1, 6), |
144 | DEF_FIXED(".pll3_div2" , CLK_PLL3_DIV2, CLK_PLL3, 1, 2), |
145 | DEF_FIXED(".pll3_div2_4" , CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4), |
146 | DEF_FIXED(".pll3_div2_8" , CLK_PLL3_DIV2_8, CLK_PLL3_DIV2, 1, 8), |
147 | DEF_FIXED(".pll3_div6" , CLK_PLL3_DIV6, CLK_PLL3, 1, 6), |
148 | DEF_FIXED(".pll6_div2" , CLK_PLL6_DIV2, CLK_PLL6, 1, 2), |
149 | DEF_SD_MUX(".sel_sd0" , CLK_SEL_SDHI0, G3S_SEL_SDHI0, G3S_SEL_SDHI0_STS, sel_sdhi, |
150 | mtable_sd, 0, NULL), |
151 | DEF_SD_MUX(".sel_sd1" , CLK_SEL_SDHI1, G3S_SEL_SDHI1, G3S_SEL_SDHI1_STS, sel_sdhi, |
152 | mtable_sd, 0, NULL), |
153 | DEF_SD_MUX(".sel_sd2" , CLK_SEL_SDHI2, G3S_SEL_SDHI2, G3S_SEL_SDHI2_STS, sel_sdhi, |
154 | mtable_sd, 0, NULL), |
155 | DEF_SD_MUX(".sel_pll4" , CLK_SEL_PLL4, G3S_SEL_PLL4, G3S_SEL_PLL4_STS, sel_pll4, |
156 | mtable_pll4, CLK_SET_PARENT_GATE, NULL), |
157 | |
158 | /* Core output clk */ |
159 | DEF_G3S_DIV("I" , R9A08G045_CLK_I, CLK_PLL1, DIVPL1A, G3S_DIVPL1A_STS, dtable_1_8, |
160 | 0, 0, 0, NULL), |
161 | DEF_G3S_DIV("P0" , R9A08G045_CLK_P0, CLK_PLL2_DIV2_8, G3S_DIVPL2B, G3S_DIVPL2B_STS, |
162 | dtable_1_32, 0, 0, 0, NULL), |
163 | DEF_G3S_DIV("SD0" , R9A08G045_CLK_SD0, CLK_SEL_SDHI0, G3S_DIV_SDHI0, G3S_DIV_SDHI0_STS, |
164 | dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, |
165 | rzg3s_cpg_div_clk_notifier), |
166 | DEF_G3S_DIV("SD1" , R9A08G045_CLK_SD1, CLK_SEL_SDHI1, G3S_DIV_SDHI1, G3S_DIV_SDHI1_STS, |
167 | dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, |
168 | rzg3s_cpg_div_clk_notifier), |
169 | DEF_G3S_DIV("SD2" , R9A08G045_CLK_SD2, CLK_SEL_SDHI2, G3S_DIV_SDHI2, G3S_DIV_SDHI2_STS, |
170 | dtable_1_2, 800000000UL, 500000000UL, CLK_SET_RATE_PARENT, |
171 | rzg3s_cpg_div_clk_notifier), |
172 | DEF_FIXED(".sd0_div4" , CLK_SD0_DIV4, R9A08G045_CLK_SD0, 1, 4), |
173 | DEF_FIXED(".sd1_div4" , CLK_SD1_DIV4, R9A08G045_CLK_SD1, 1, 4), |
174 | DEF_FIXED(".sd2_div4" , CLK_SD2_DIV4, R9A08G045_CLK_SD2, 1, 4), |
175 | DEF_FIXED("M0" , R9A08G045_CLK_M0, CLK_PLL3_DIV2_4, 1, 1), |
176 | DEF_G3S_DIV("P1" , R9A08G045_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3A, G3S_DIVPL3A_STS, |
177 | dtable_1_32, 0, 0, 0, NULL), |
178 | DEF_FIXED("P1_DIV2" , CLK_P1_DIV2, R9A08G045_CLK_P1, 1, 2), |
179 | DEF_G3S_DIV("P2" , R9A08G045_CLK_P2, CLK_PLL3_DIV2_8, DIVPL3B, G3S_DIVPL3B_STS, |
180 | dtable_1_32, 0, 0, 0, NULL), |
181 | DEF_G3S_DIV("P3" , R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C_STS, |
182 | dtable_1_32, 0, 0, 0, NULL), |
183 | DEF_FIXED("P3_DIV2" , CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2), |
184 | DEF_FIXED("ZT" , R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1), |
185 | DEF_FIXED("S0" , R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2), |
186 | DEF_FIXED("OSC" , R9A08G045_OSCCLK, CLK_EXTAL, 1, 1), |
187 | DEF_FIXED("OSC2" , R9A08G045_OSCCLK2, CLK_EXTAL, 1, 3), |
188 | DEF_FIXED("HP" , R9A08G045_CLK_HP, CLK_PLL6, 1, 2), |
189 | }; |
190 | |
191 | static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { |
192 | DEF_MOD("gic_gicclk" , R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0), |
193 | DEF_MOD("ia55_pclk" , R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0), |
194 | DEF_MOD("ia55_clk" , R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), |
195 | DEF_MOD("dmac_aclk" , R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), |
196 | DEF_MOD("wdt0_pclk" , R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0), |
197 | DEF_MOD("wdt0_clk" , R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1), |
198 | DEF_MOD("sdhi0_imclk" , R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), |
199 | DEF_MOD("sdhi0_imclk2" , R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1), |
200 | DEF_MOD("sdhi0_clk_hs" , R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2), |
201 | DEF_MOD("sdhi0_aclk" , R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3), |
202 | DEF_MOD("sdhi1_imclk" , R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4), |
203 | DEF_MOD("sdhi1_imclk2" , R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5), |
204 | DEF_MOD("sdhi1_clk_hs" , R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6), |
205 | DEF_MOD("sdhi1_aclk" , R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7), |
206 | DEF_MOD("sdhi2_imclk" , R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8), |
207 | DEF_MOD("sdhi2_imclk2" , R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9), |
208 | DEF_MOD("sdhi2_clk_hs" , R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10), |
209 | DEF_MOD("sdhi2_aclk" , R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11), |
210 | DEF_COUPLED("eth0_axi" , R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0), |
211 | DEF_COUPLED("eth0_chi" , R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0), |
212 | DEF_MOD("eth0_refclk" , R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8), |
213 | DEF_COUPLED("eth1_axi" , R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1), |
214 | DEF_COUPLED("eth1_chi" , R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1), |
215 | DEF_MOD("eth1_refclk" , R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), |
216 | DEF_MOD("scif0_clk_pck" , R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), |
217 | DEF_MOD("gpio_hclk" , R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), |
218 | }; |
219 | |
220 | static const struct rzg2l_reset r9a08g045_resets[] = { |
221 | DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0), |
222 | DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1), |
223 | DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0), |
224 | DEF_RST(R9A08G045_WDT0_PRESETN, 0x848, 0), |
225 | DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0), |
226 | DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1), |
227 | DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2), |
228 | DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0), |
229 | DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1), |
230 | DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0), |
231 | DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), |
232 | DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), |
233 | DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), |
234 | }; |
235 | |
236 | static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { |
237 | MOD_CLK_BASE + R9A08G045_GIC600_GICCLK, |
238 | MOD_CLK_BASE + R9A08G045_IA55_PCLK, |
239 | MOD_CLK_BASE + R9A08G045_IA55_CLK, |
240 | MOD_CLK_BASE + R9A08G045_DMAC_ACLK, |
241 | }; |
242 | |
243 | const struct rzg2l_cpg_info r9a08g045_cpg_info = { |
244 | /* Core Clocks */ |
245 | .core_clks = r9a08g045_core_clks, |
246 | .num_core_clks = ARRAY_SIZE(r9a08g045_core_clks), |
247 | .last_dt_core_clk = LAST_DT_CORE_CLK, |
248 | .num_total_core_clks = MOD_CLK_BASE, |
249 | |
250 | /* Critical Module Clocks */ |
251 | .crit_mod_clks = r9a08g045_crit_mod_clks, |
252 | .num_crit_mod_clks = ARRAY_SIZE(r9a08g045_crit_mod_clks), |
253 | |
254 | /* Module Clocks */ |
255 | .mod_clks = r9a08g045_mod_clks, |
256 | .num_mod_clks = ARRAY_SIZE(r9a08g045_mod_clks), |
257 | .num_hw_mod_clks = R9A08G045_VBAT_BCLK + 1, |
258 | |
259 | /* Resets */ |
260 | .resets = r9a08g045_resets, |
261 | .num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ |
262 | |
263 | .has_clk_mon_regs = true, |
264 | }; |
265 | |