1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * drivers/clocksource/arm_global_timer.c |
4 | * |
5 | * Copyright (C) 2013 STMicroelectronics (R&D) Limited. |
6 | * Author: Stuart Menefy <stuart.menefy@st.com> |
7 | * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> |
8 | */ |
9 | |
10 | #include <linux/init.h> |
11 | #include <linux/interrupt.h> |
12 | #include <linux/bitfield.h> |
13 | #include <linux/clocksource.h> |
14 | #include <linux/clockchips.h> |
15 | #include <linux/cpu.h> |
16 | #include <linux/clk.h> |
17 | #include <linux/delay.h> |
18 | #include <linux/err.h> |
19 | #include <linux/io.h> |
20 | #include <linux/of.h> |
21 | #include <linux/of_irq.h> |
22 | #include <linux/of_address.h> |
23 | #include <linux/sched_clock.h> |
24 | |
25 | #include <asm/cputype.h> |
26 | |
27 | #define GT_COUNTER0 0x00 |
28 | #define GT_COUNTER1 0x04 |
29 | |
30 | #define GT_CONTROL 0x08 |
31 | #define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */ |
32 | #define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */ |
33 | #define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */ |
34 | #define GT_CONTROL_AUTO_INC BIT(3) /* banked */ |
35 | #define GT_CONTROL_PRESCALER_MASK GENMASK(15, 8) |
36 | |
37 | #define GT_INT_STATUS 0x0c |
38 | #define GT_INT_STATUS_EVENT_FLAG BIT(0) |
39 | |
40 | #define GT_COMP0 0x10 |
41 | #define GT_COMP1 0x14 |
42 | #define GT_AUTO_INC 0x18 |
43 | |
44 | #define MAX_F_ERR 50 |
45 | /* |
46 | * We are expecting to be clocked by the ARM peripheral clock. |
47 | * |
48 | * Note: it is assumed we are using a prescaler value of zero, so this is |
49 | * the units for all operations. |
50 | */ |
51 | static void __iomem *gt_base; |
52 | static struct notifier_block gt_clk_rate_change_nb; |
53 | static u32 gt_psv_new, gt_psv_bck; |
54 | static unsigned long gt_target_rate; |
55 | static int gt_ppi; |
56 | static struct clock_event_device __percpu *gt_evt; |
57 | |
58 | /* |
59 | * To get the value from the Global Timer Counter register proceed as follows: |
60 | * 1. Read the upper 32-bit timer counter register |
61 | * 2. Read the lower 32-bit timer counter register |
62 | * 3. Read the upper 32-bit timer counter register again. If the value is |
63 | * different to the 32-bit upper value read previously, go back to step 2. |
64 | * Otherwise the 64-bit timer counter value is correct. |
65 | */ |
66 | static u64 notrace _gt_counter_read(void) |
67 | { |
68 | u64 counter; |
69 | u32 lower; |
70 | u32 upper, old_upper; |
71 | |
72 | upper = readl_relaxed(gt_base + GT_COUNTER1); |
73 | do { |
74 | old_upper = upper; |
75 | lower = readl_relaxed(gt_base + GT_COUNTER0); |
76 | upper = readl_relaxed(gt_base + GT_COUNTER1); |
77 | } while (upper != old_upper); |
78 | |
79 | counter = upper; |
80 | counter <<= 32; |
81 | counter |= lower; |
82 | return counter; |
83 | } |
84 | |
85 | static u64 gt_counter_read(void) |
86 | { |
87 | return _gt_counter_read(); |
88 | } |
89 | |
90 | /* |
91 | * To ensure that updates to comparator value register do not set the |
92 | * Interrupt Status Register proceed as follows: |
93 | * 1. Clear the Comp Enable bit in the Timer Control Register. |
94 | * 2. Write the lower 32-bit Comparator Value Register. |
95 | * 3. Write the upper 32-bit Comparator Value Register. |
96 | * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit. |
97 | */ |
98 | static void gt_compare_set(unsigned long delta, int periodic) |
99 | { |
100 | u64 counter = gt_counter_read(); |
101 | unsigned long ctrl; |
102 | |
103 | counter += delta; |
104 | ctrl = readl(addr: gt_base + GT_CONTROL); |
105 | ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE | |
106 | GT_CONTROL_AUTO_INC); |
107 | ctrl |= GT_CONTROL_TIMER_ENABLE; |
108 | writel_relaxed(ctrl, gt_base + GT_CONTROL); |
109 | writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0); |
110 | writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1); |
111 | |
112 | if (periodic) { |
113 | writel_relaxed(delta, gt_base + GT_AUTO_INC); |
114 | ctrl |= GT_CONTROL_AUTO_INC; |
115 | } |
116 | |
117 | ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE; |
118 | writel_relaxed(ctrl, gt_base + GT_CONTROL); |
119 | } |
120 | |
121 | static int gt_clockevent_shutdown(struct clock_event_device *evt) |
122 | { |
123 | unsigned long ctrl; |
124 | |
125 | ctrl = readl(addr: gt_base + GT_CONTROL); |
126 | ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE | |
127 | GT_CONTROL_AUTO_INC); |
128 | writel(val: ctrl, addr: gt_base + GT_CONTROL); |
129 | return 0; |
130 | } |
131 | |
132 | static int gt_clockevent_set_periodic(struct clock_event_device *evt) |
133 | { |
134 | gt_compare_set(DIV_ROUND_CLOSEST(gt_target_rate, HZ), periodic: 1); |
135 | return 0; |
136 | } |
137 | |
138 | static int gt_clockevent_set_next_event(unsigned long evt, |
139 | struct clock_event_device *unused) |
140 | { |
141 | gt_compare_set(delta: evt, periodic: 0); |
142 | return 0; |
143 | } |
144 | |
145 | static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id) |
146 | { |
147 | struct clock_event_device *evt = dev_id; |
148 | |
149 | if (!(readl_relaxed(gt_base + GT_INT_STATUS) & |
150 | GT_INT_STATUS_EVENT_FLAG)) |
151 | return IRQ_NONE; |
152 | |
153 | /** |
154 | * ERRATA 740657( Global Timer can send 2 interrupts for |
155 | * the same event in single-shot mode) |
156 | * Workaround: |
157 | * Either disable single-shot mode. |
158 | * Or |
159 | * Modify the Interrupt Handler to avoid the |
160 | * offending sequence. This is achieved by clearing |
161 | * the Global Timer flag _after_ having incremented |
162 | * the Comparator register value to a higher value. |
163 | */ |
164 | if (clockevent_state_oneshot(dev: evt)) |
165 | gt_compare_set(ULONG_MAX, periodic: 0); |
166 | |
167 | writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS); |
168 | evt->event_handler(evt); |
169 | |
170 | return IRQ_HANDLED; |
171 | } |
172 | |
173 | static int gt_starting_cpu(unsigned int cpu) |
174 | { |
175 | struct clock_event_device *clk = this_cpu_ptr(gt_evt); |
176 | |
177 | clk->name = "arm_global_timer" ; |
178 | clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
179 | CLOCK_EVT_FEAT_PERCPU; |
180 | clk->set_state_shutdown = gt_clockevent_shutdown; |
181 | clk->set_state_periodic = gt_clockevent_set_periodic; |
182 | clk->set_state_oneshot = gt_clockevent_shutdown; |
183 | clk->set_state_oneshot_stopped = gt_clockevent_shutdown; |
184 | clk->set_next_event = gt_clockevent_set_next_event; |
185 | clk->cpumask = cpumask_of(cpu); |
186 | clk->rating = 300; |
187 | clk->irq = gt_ppi; |
188 | clockevents_config_and_register(dev: clk, freq: gt_target_rate, |
189 | min_delta: 1, max_delta: 0xffffffff); |
190 | enable_percpu_irq(irq: clk->irq, type: IRQ_TYPE_NONE); |
191 | return 0; |
192 | } |
193 | |
194 | static int gt_dying_cpu(unsigned int cpu) |
195 | { |
196 | struct clock_event_device *clk = this_cpu_ptr(gt_evt); |
197 | |
198 | gt_clockevent_shutdown(evt: clk); |
199 | disable_percpu_irq(irq: clk->irq); |
200 | return 0; |
201 | } |
202 | |
203 | static u64 gt_clocksource_read(struct clocksource *cs) |
204 | { |
205 | return gt_counter_read(); |
206 | } |
207 | |
208 | static void gt_resume(struct clocksource *cs) |
209 | { |
210 | unsigned long ctrl; |
211 | |
212 | ctrl = readl(addr: gt_base + GT_CONTROL); |
213 | if (!(ctrl & GT_CONTROL_TIMER_ENABLE)) |
214 | /* re-enable timer on resume */ |
215 | writel(GT_CONTROL_TIMER_ENABLE, addr: gt_base + GT_CONTROL); |
216 | } |
217 | |
218 | static struct clocksource gt_clocksource = { |
219 | .name = "arm_global_timer" , |
220 | .rating = 300, |
221 | .read = gt_clocksource_read, |
222 | .mask = CLOCKSOURCE_MASK(64), |
223 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
224 | .resume = gt_resume, |
225 | }; |
226 | |
227 | #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK |
228 | static u64 notrace gt_sched_clock_read(void) |
229 | { |
230 | return _gt_counter_read(); |
231 | } |
232 | #endif |
233 | |
234 | static unsigned long gt_read_long(void) |
235 | { |
236 | return readl_relaxed(gt_base + GT_COUNTER0); |
237 | } |
238 | |
239 | static struct delay_timer gt_delay_timer = { |
240 | .read_current_timer = gt_read_long, |
241 | }; |
242 | |
243 | static void gt_write_presc(u32 psv) |
244 | { |
245 | u32 reg; |
246 | |
247 | reg = readl(addr: gt_base + GT_CONTROL); |
248 | reg &= ~GT_CONTROL_PRESCALER_MASK; |
249 | reg |= FIELD_PREP(GT_CONTROL_PRESCALER_MASK, psv); |
250 | writel(val: reg, addr: gt_base + GT_CONTROL); |
251 | } |
252 | |
253 | static u32 gt_read_presc(void) |
254 | { |
255 | u32 reg; |
256 | |
257 | reg = readl(addr: gt_base + GT_CONTROL); |
258 | return FIELD_GET(GT_CONTROL_PRESCALER_MASK, reg); |
259 | } |
260 | |
261 | static void __init gt_delay_timer_init(void) |
262 | { |
263 | gt_delay_timer.freq = gt_target_rate; |
264 | register_current_timer_delay(>_delay_timer); |
265 | } |
266 | |
267 | static int __init gt_clocksource_init(void) |
268 | { |
269 | writel(val: 0, addr: gt_base + GT_CONTROL); |
270 | writel(val: 0, addr: gt_base + GT_COUNTER0); |
271 | writel(val: 0, addr: gt_base + GT_COUNTER1); |
272 | /* set prescaler and enable timer on all the cores */ |
273 | writel(FIELD_PREP(GT_CONTROL_PRESCALER_MASK, |
274 | CONFIG_ARM_GT_INITIAL_PRESCALER_VAL - 1) | |
275 | GT_CONTROL_TIMER_ENABLE, addr: gt_base + GT_CONTROL); |
276 | |
277 | #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK |
278 | sched_clock_register(gt_sched_clock_read, 64, gt_target_rate); |
279 | #endif |
280 | return clocksource_register_hz(cs: >_clocksource, hz: gt_target_rate); |
281 | } |
282 | |
283 | static int gt_clk_rate_change_cb(struct notifier_block *nb, |
284 | unsigned long event, void *data) |
285 | { |
286 | struct clk_notifier_data *ndata = data; |
287 | |
288 | switch (event) { |
289 | case PRE_RATE_CHANGE: |
290 | { |
291 | unsigned long psv; |
292 | |
293 | psv = DIV_ROUND_CLOSEST(ndata->new_rate, gt_target_rate); |
294 | if (!psv || |
295 | abs(gt_target_rate - (ndata->new_rate / psv)) > MAX_F_ERR) |
296 | return NOTIFY_BAD; |
297 | |
298 | psv--; |
299 | |
300 | /* prescaler within legal range? */ |
301 | if (!FIELD_FIT(GT_CONTROL_PRESCALER_MASK, psv)) |
302 | return NOTIFY_BAD; |
303 | |
304 | /* |
305 | * store timer clock ctrl register so we can restore it in case |
306 | * of an abort. |
307 | */ |
308 | gt_psv_bck = gt_read_presc(); |
309 | gt_psv_new = psv; |
310 | /* scale down: adjust divider in post-change notification */ |
311 | if (ndata->new_rate < ndata->old_rate) |
312 | return NOTIFY_DONE; |
313 | |
314 | /* scale up: adjust divider now - before frequency change */ |
315 | gt_write_presc(psv); |
316 | break; |
317 | } |
318 | case POST_RATE_CHANGE: |
319 | /* scale up: pre-change notification did the adjustment */ |
320 | if (ndata->new_rate > ndata->old_rate) |
321 | return NOTIFY_OK; |
322 | |
323 | /* scale down: adjust divider now - after frequency change */ |
324 | gt_write_presc(psv: gt_psv_new); |
325 | break; |
326 | |
327 | case ABORT_RATE_CHANGE: |
328 | /* we have to undo the adjustment in case we scale up */ |
329 | if (ndata->new_rate < ndata->old_rate) |
330 | return NOTIFY_OK; |
331 | |
332 | /* restore original register value */ |
333 | gt_write_presc(psv: gt_psv_bck); |
334 | break; |
335 | default: |
336 | return NOTIFY_DONE; |
337 | } |
338 | |
339 | return NOTIFY_DONE; |
340 | } |
341 | |
342 | static int __init global_timer_of_register(struct device_node *np) |
343 | { |
344 | struct clk *gt_clk; |
345 | static unsigned long gt_clk_rate; |
346 | int err = 0; |
347 | |
348 | /* |
349 | * In A9 r2p0 the comparators for each processor with the global timer |
350 | * fire when the timer value is greater than or equal to. In previous |
351 | * revisions the comparators fired when the timer value was equal to. |
352 | */ |
353 | if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9 |
354 | && (read_cpuid_id() & 0xf0000f) < 0x200000) { |
355 | pr_warn("global-timer: non support for this cpu version.\n" ); |
356 | return -ENOSYS; |
357 | } |
358 | |
359 | gt_ppi = irq_of_parse_and_map(node: np, index: 0); |
360 | if (!gt_ppi) { |
361 | pr_warn("global-timer: unable to parse irq\n" ); |
362 | return -EINVAL; |
363 | } |
364 | |
365 | gt_base = of_iomap(node: np, index: 0); |
366 | if (!gt_base) { |
367 | pr_warn("global-timer: invalid base address\n" ); |
368 | return -ENXIO; |
369 | } |
370 | |
371 | gt_clk = of_clk_get(np, index: 0); |
372 | if (!IS_ERR(ptr: gt_clk)) { |
373 | err = clk_prepare_enable(clk: gt_clk); |
374 | if (err) |
375 | goto out_unmap; |
376 | } else { |
377 | pr_warn("global-timer: clk not found\n" ); |
378 | err = -EINVAL; |
379 | goto out_unmap; |
380 | } |
381 | |
382 | gt_clk_rate = clk_get_rate(clk: gt_clk); |
383 | gt_target_rate = gt_clk_rate / CONFIG_ARM_GT_INITIAL_PRESCALER_VAL; |
384 | gt_clk_rate_change_nb.notifier_call = |
385 | gt_clk_rate_change_cb; |
386 | err = clk_notifier_register(clk: gt_clk, nb: >_clk_rate_change_nb); |
387 | if (err) { |
388 | pr_warn("Unable to register clock notifier\n" ); |
389 | goto out_clk; |
390 | } |
391 | |
392 | gt_evt = alloc_percpu(struct clock_event_device); |
393 | if (!gt_evt) { |
394 | pr_warn("global-timer: can't allocate memory\n" ); |
395 | err = -ENOMEM; |
396 | goto out_clk_nb; |
397 | } |
398 | |
399 | err = request_percpu_irq(irq: gt_ppi, handler: gt_clockevent_interrupt, |
400 | devname: "gt" , percpu_dev_id: gt_evt); |
401 | if (err) { |
402 | pr_warn("global-timer: can't register interrupt %d (%d)\n" , |
403 | gt_ppi, err); |
404 | goto out_free; |
405 | } |
406 | |
407 | /* Register and immediately configure the timer on the boot CPU */ |
408 | err = gt_clocksource_init(); |
409 | if (err) |
410 | goto out_irq; |
411 | |
412 | err = cpuhp_setup_state(state: CPUHP_AP_ARM_GLOBAL_TIMER_STARTING, |
413 | name: "clockevents/arm/global_timer:starting" , |
414 | startup: gt_starting_cpu, teardown: gt_dying_cpu); |
415 | if (err) |
416 | goto out_irq; |
417 | |
418 | gt_delay_timer_init(); |
419 | |
420 | return 0; |
421 | |
422 | out_irq: |
423 | free_percpu_irq(gt_ppi, gt_evt); |
424 | out_free: |
425 | free_percpu(pdata: gt_evt); |
426 | out_clk_nb: |
427 | clk_notifier_unregister(clk: gt_clk, nb: >_clk_rate_change_nb); |
428 | out_clk: |
429 | clk_disable_unprepare(clk: gt_clk); |
430 | out_unmap: |
431 | iounmap(addr: gt_base); |
432 | WARN(err, "ARM Global timer register failed (%d)\n" , err); |
433 | |
434 | return err; |
435 | } |
436 | |
437 | /* Only tested on r2p2 and r3p0 */ |
438 | TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer" , |
439 | global_timer_of_register); |
440 | |