1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* |
3 | * Clocksource driver for Loongson-1 SoC |
4 | * |
5 | * Copyright (c) 2023 Keguang Zhang <keguang.zhang@gmail.com> |
6 | */ |
7 | |
8 | #include <linux/clockchips.h> |
9 | #include <linux/interrupt.h> |
10 | #include <linux/sizes.h> |
11 | #include "timer-of.h" |
12 | |
13 | /* Loongson-1 PWM Timer Register Definitions */ |
14 | #define PWM_CNTR 0x0 |
15 | #define PWM_HRC 0x4 |
16 | #define PWM_LRC 0x8 |
17 | #define PWM_CTRL 0xc |
18 | |
19 | /* PWM Control Register Bits */ |
20 | #define INT_LRC_EN BIT(11) |
21 | #define INT_HRC_EN BIT(10) |
22 | #define CNTR_RST BIT(7) |
23 | #define INT_SR BIT(6) |
24 | #define INT_EN BIT(5) |
25 | #define PWM_SINGLE BIT(4) |
26 | #define PWM_OE BIT(3) |
27 | #define CNT_EN BIT(0) |
28 | |
29 | #define CNTR_WIDTH 24 |
30 | |
31 | static DEFINE_RAW_SPINLOCK(ls1x_timer_lock); |
32 | |
33 | struct ls1x_clocksource { |
34 | void __iomem *reg_base; |
35 | unsigned long ticks_per_jiffy; |
36 | struct clocksource clksrc; |
37 | }; |
38 | |
39 | static inline struct ls1x_clocksource *to_ls1x_clksrc(struct clocksource *c) |
40 | { |
41 | return container_of(c, struct ls1x_clocksource, clksrc); |
42 | } |
43 | |
44 | static inline void ls1x_pwmtimer_set_period(unsigned int period, |
45 | struct timer_of *to) |
46 | { |
47 | writel(val: period, addr: timer_of_base(to) + PWM_LRC); |
48 | writel(val: period, addr: timer_of_base(to) + PWM_HRC); |
49 | } |
50 | |
51 | static inline void ls1x_pwmtimer_clear(struct timer_of *to) |
52 | { |
53 | writel(val: 0, addr: timer_of_base(to) + PWM_CNTR); |
54 | } |
55 | |
56 | static inline void ls1x_pwmtimer_start(struct timer_of *to) |
57 | { |
58 | writel(val: (INT_EN | PWM_OE | CNT_EN), addr: timer_of_base(to) + PWM_CTRL); |
59 | } |
60 | |
61 | static inline void ls1x_pwmtimer_stop(struct timer_of *to) |
62 | { |
63 | writel(val: 0, addr: timer_of_base(to) + PWM_CTRL); |
64 | } |
65 | |
66 | static inline void ls1x_pwmtimer_irq_ack(struct timer_of *to) |
67 | { |
68 | int val; |
69 | |
70 | val = readl(addr: timer_of_base(to) + PWM_CTRL); |
71 | val |= INT_SR; |
72 | writel(val, addr: timer_of_base(to) + PWM_CTRL); |
73 | } |
74 | |
75 | static irqreturn_t ls1x_clockevent_isr(int irq, void *dev_id) |
76 | { |
77 | struct clock_event_device *clkevt = dev_id; |
78 | struct timer_of *to = to_timer_of(clkevt); |
79 | |
80 | ls1x_pwmtimer_irq_ack(to); |
81 | ls1x_pwmtimer_clear(to); |
82 | ls1x_pwmtimer_start(to); |
83 | |
84 | clkevt->event_handler(clkevt); |
85 | |
86 | return IRQ_HANDLED; |
87 | } |
88 | |
89 | static int ls1x_clockevent_set_state_periodic(struct clock_event_device *clkevt) |
90 | { |
91 | struct timer_of *to = to_timer_of(clkevt); |
92 | |
93 | raw_spin_lock(&ls1x_timer_lock); |
94 | ls1x_pwmtimer_set_period(period: timer_of_period(to), to); |
95 | ls1x_pwmtimer_clear(to); |
96 | ls1x_pwmtimer_start(to); |
97 | raw_spin_unlock(&ls1x_timer_lock); |
98 | |
99 | return 0; |
100 | } |
101 | |
102 | static int ls1x_clockevent_tick_resume(struct clock_event_device *clkevt) |
103 | { |
104 | raw_spin_lock(&ls1x_timer_lock); |
105 | ls1x_pwmtimer_start(to: to_timer_of(clkevt)); |
106 | raw_spin_unlock(&ls1x_timer_lock); |
107 | |
108 | return 0; |
109 | } |
110 | |
111 | static int ls1x_clockevent_set_state_shutdown(struct clock_event_device *clkevt) |
112 | { |
113 | raw_spin_lock(&ls1x_timer_lock); |
114 | ls1x_pwmtimer_stop(to: to_timer_of(clkevt)); |
115 | raw_spin_unlock(&ls1x_timer_lock); |
116 | |
117 | return 0; |
118 | } |
119 | |
120 | static int ls1x_clockevent_set_next(unsigned long evt, |
121 | struct clock_event_device *clkevt) |
122 | { |
123 | struct timer_of *to = to_timer_of(clkevt); |
124 | |
125 | raw_spin_lock(&ls1x_timer_lock); |
126 | ls1x_pwmtimer_set_period(period: evt, to); |
127 | ls1x_pwmtimer_clear(to); |
128 | ls1x_pwmtimer_start(to); |
129 | raw_spin_unlock(&ls1x_timer_lock); |
130 | |
131 | return 0; |
132 | } |
133 | |
134 | static struct timer_of ls1x_to = { |
135 | .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, |
136 | .clkevt = { |
137 | .name = "ls1x-pwmtimer" , |
138 | .features = CLOCK_EVT_FEAT_PERIODIC | |
139 | CLOCK_EVT_FEAT_ONESHOT, |
140 | .rating = 300, |
141 | .set_next_event = ls1x_clockevent_set_next, |
142 | .set_state_periodic = ls1x_clockevent_set_state_periodic, |
143 | .set_state_oneshot = ls1x_clockevent_set_state_shutdown, |
144 | .set_state_shutdown = ls1x_clockevent_set_state_shutdown, |
145 | .tick_resume = ls1x_clockevent_tick_resume, |
146 | }, |
147 | .of_irq = { |
148 | .handler = ls1x_clockevent_isr, |
149 | .flags = IRQF_TIMER, |
150 | }, |
151 | }; |
152 | |
153 | /* |
154 | * Since the PWM timer overflows every two ticks, its not very useful |
155 | * to just read by itself. So use jiffies to emulate a free |
156 | * running counter: |
157 | */ |
158 | static u64 ls1x_clocksource_read(struct clocksource *cs) |
159 | { |
160 | struct ls1x_clocksource *ls1x_cs = to_ls1x_clksrc(c: cs); |
161 | unsigned long flags; |
162 | int count; |
163 | u32 jifs; |
164 | static int old_count; |
165 | static u32 old_jifs; |
166 | |
167 | raw_spin_lock_irqsave(&ls1x_timer_lock, flags); |
168 | /* |
169 | * Although our caller may have the read side of xtime_lock, |
170 | * this is now a seqlock, and we are cheating in this routine |
171 | * by having side effects on state that we cannot undo if |
172 | * there is a collision on the seqlock and our caller has to |
173 | * retry. (Namely, old_jifs and old_count.) So we must treat |
174 | * jiffies as volatile despite the lock. We read jiffies |
175 | * before latching the timer count to guarantee that although |
176 | * the jiffies value might be older than the count (that is, |
177 | * the counter may underflow between the last point where |
178 | * jiffies was incremented and the point where we latch the |
179 | * count), it cannot be newer. |
180 | */ |
181 | jifs = jiffies; |
182 | /* read the count */ |
183 | count = readl(addr: ls1x_cs->reg_base + PWM_CNTR); |
184 | |
185 | /* |
186 | * It's possible for count to appear to go the wrong way for this |
187 | * reason: |
188 | * |
189 | * The timer counter underflows, but we haven't handled the resulting |
190 | * interrupt and incremented jiffies yet. |
191 | * |
192 | * Previous attempts to handle these cases intelligently were buggy, so |
193 | * we just do the simple thing now. |
194 | */ |
195 | if (count < old_count && jifs == old_jifs) |
196 | count = old_count; |
197 | |
198 | old_count = count; |
199 | old_jifs = jifs; |
200 | |
201 | raw_spin_unlock_irqrestore(&ls1x_timer_lock, flags); |
202 | |
203 | return (u64)(jifs * ls1x_cs->ticks_per_jiffy) + count; |
204 | } |
205 | |
206 | static struct ls1x_clocksource ls1x_clocksource = { |
207 | .clksrc = { |
208 | .name = "ls1x-pwmtimer" , |
209 | .rating = 300, |
210 | .read = ls1x_clocksource_read, |
211 | .mask = CLOCKSOURCE_MASK(CNTR_WIDTH), |
212 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
213 | }, |
214 | }; |
215 | |
216 | static int __init ls1x_pwm_clocksource_init(struct device_node *np) |
217 | { |
218 | struct timer_of *to = &ls1x_to; |
219 | int ret; |
220 | |
221 | ret = timer_of_init(np, to); |
222 | if (ret) |
223 | return ret; |
224 | |
225 | clockevents_config_and_register(dev: &to->clkevt, freq: timer_of_rate(to), |
226 | min_delta: 0x1, GENMASK(CNTR_WIDTH - 1, 0)); |
227 | |
228 | ls1x_clocksource.reg_base = timer_of_base(to); |
229 | ls1x_clocksource.ticks_per_jiffy = timer_of_period(to); |
230 | |
231 | return clocksource_register_hz(cs: &ls1x_clocksource.clksrc, |
232 | hz: timer_of_rate(to)); |
233 | } |
234 | |
235 | TIMER_OF_DECLARE(ls1x_pwm_clocksource, "loongson,ls1b-pwmtimer" , |
236 | ls1x_pwm_clocksource_init); |
237 | |