1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* |
3 | * comedi/drivers/me_daq.c |
4 | * Hardware driver for Meilhaus data acquisition cards: |
5 | * ME-2000i, ME-2600i, ME-3000vm1 |
6 | * |
7 | * Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de> |
8 | */ |
9 | |
10 | /* |
11 | * Driver: me_daq |
12 | * Description: Meilhaus PCI data acquisition cards |
13 | * Devices: [Meilhaus] ME-2600i (me-2600i), ME-2000i (me-2000i) |
14 | * Author: Michael Hillmann <hillmann@syscongroup.de> |
15 | * Status: experimental |
16 | * |
17 | * Configuration options: not applicable, uses PCI auto config |
18 | * |
19 | * Supports: |
20 | * Analog Input, Analog Output, Digital I/O |
21 | */ |
22 | |
23 | #include <linux/module.h> |
24 | #include <linux/interrupt.h> |
25 | #include <linux/sched.h> |
26 | #include <linux/comedi/comedi_pci.h> |
27 | |
28 | #include "plx9052.h" |
29 | |
30 | #define ME2600_FIRMWARE "me2600_firmware.bin" |
31 | |
32 | #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */ |
33 | |
34 | /* |
35 | * PCI BAR2 Memory map (dev->mmio) |
36 | */ |
37 | #define ME_CTRL1_REG 0x00 /* R (ai start) | W */ |
38 | #define ME_CTRL1_INT_ENA BIT(15) |
39 | #define ME_CTRL1_COUNTER_B_IRQ BIT(12) |
40 | #define ME_CTRL1_COUNTER_A_IRQ BIT(11) |
41 | #define ME_CTRL1_CHANLIST_READY_IRQ BIT(10) |
42 | #define ME_CTRL1_EXT_IRQ BIT(9) |
43 | #define ME_CTRL1_ADFIFO_HALFFULL_IRQ BIT(8) |
44 | #define ME_CTRL1_SCAN_COUNT_ENA BIT(5) |
45 | #define ME_CTRL1_SIMULTANEOUS_ENA BIT(4) |
46 | #define ME_CTRL1_TRIGGER_FALLING_EDGE BIT(3) |
47 | #define ME_CTRL1_CONTINUOUS_MODE BIT(2) |
48 | #define ME_CTRL1_ADC_MODE(x) (((x) & 0x3) << 0) |
49 | #define ME_CTRL1_ADC_MODE_DISABLE ME_CTRL1_ADC_MODE(0) |
50 | #define ME_CTRL1_ADC_MODE_SOFT_TRIG ME_CTRL1_ADC_MODE(1) |
51 | #define ME_CTRL1_ADC_MODE_SCAN_TRIG ME_CTRL1_ADC_MODE(2) |
52 | #define ME_CTRL1_ADC_MODE_EXT_TRIG ME_CTRL1_ADC_MODE(3) |
53 | #define ME_CTRL1_ADC_MODE_MASK ME_CTRL1_ADC_MODE(3) |
54 | #define ME_CTRL2_REG 0x02 /* R (dac update) | W */ |
55 | #define ME_CTRL2_ADFIFO_ENA BIT(10) |
56 | #define ME_CTRL2_CHANLIST_ENA BIT(9) |
57 | #define ME_CTRL2_PORT_B_ENA BIT(7) |
58 | #define ME_CTRL2_PORT_A_ENA BIT(6) |
59 | #define ME_CTRL2_COUNTER_B_ENA BIT(4) |
60 | #define ME_CTRL2_COUNTER_A_ENA BIT(3) |
61 | #define ME_CTRL2_DAC_ENA BIT(1) |
62 | #define ME_CTRL2_BUFFERED_DAC BIT(0) |
63 | #define ME_STATUS_REG 0x04 /* R | W (clears interrupts) */ |
64 | #define ME_STATUS_COUNTER_B_IRQ BIT(12) |
65 | #define ME_STATUS_COUNTER_A_IRQ BIT(11) |
66 | #define ME_STATUS_CHANLIST_READY_IRQ BIT(10) |
67 | #define ME_STATUS_EXT_IRQ BIT(9) |
68 | #define ME_STATUS_ADFIFO_HALFFULL_IRQ BIT(8) |
69 | #define ME_STATUS_ADFIFO_FULL BIT(4) |
70 | #define ME_STATUS_ADFIFO_HALFFULL BIT(3) |
71 | #define ME_STATUS_ADFIFO_EMPTY BIT(2) |
72 | #define ME_STATUS_CHANLIST_FULL BIT(1) |
73 | #define ME_STATUS_FST_ACTIVE BIT(0) |
74 | #define ME_DIO_PORT_A_REG 0x06 /* R | W */ |
75 | #define ME_DIO_PORT_B_REG 0x08 /* R | W */ |
76 | #define ME_TIMER_DATA_REG(x) (0x0a + ((x) * 2)) /* - | W */ |
77 | #define ME_AI_FIFO_REG 0x10 /* R (fifo) | W (chanlist) */ |
78 | #define ME_AI_FIFO_CHANLIST_DIFF BIT(7) |
79 | #define ME_AI_FIFO_CHANLIST_UNIPOLAR BIT(6) |
80 | #define ME_AI_FIFO_CHANLIST_GAIN(x) (((x) & 0x3) << 4) |
81 | #define ME_AI_FIFO_CHANLIST_CHAN(x) (((x) & 0xf) << 0) |
82 | #define ME_DAC_CTRL_REG 0x12 /* R (updates) | W */ |
83 | #define ME_DAC_CTRL_BIPOLAR(x) BIT(7 - ((x) & 0x3)) |
84 | #define ME_DAC_CTRL_GAIN(x) BIT(11 - ((x) & 0x3)) |
85 | #define ME_DAC_CTRL_MASK(x) (ME_DAC_CTRL_BIPOLAR(x) | \ |
86 | ME_DAC_CTRL_GAIN(x)) |
87 | #define ME_AO_DATA_REG(x) (0x14 + ((x) * 2)) /* - | W */ |
88 | #define ME_COUNTER_ENDDATA_REG(x) (0x1c + ((x) * 2)) /* - | W */ |
89 | #define ME_COUNTER_STARTDATA_REG(x) (0x20 + ((x) * 2)) /* - | W */ |
90 | #define ME_COUNTER_VALUE_REG(x) (0x20 + ((x) * 2)) /* R | - */ |
91 | |
92 | static const struct comedi_lrange me_ai_range = { |
93 | 8, { |
94 | BIP_RANGE(10), |
95 | BIP_RANGE(5), |
96 | BIP_RANGE(2.5), |
97 | BIP_RANGE(1.25), |
98 | UNI_RANGE(10), |
99 | UNI_RANGE(5), |
100 | UNI_RANGE(2.5), |
101 | UNI_RANGE(1.25) |
102 | } |
103 | }; |
104 | |
105 | static const struct comedi_lrange me_ao_range = { |
106 | 3, { |
107 | BIP_RANGE(10), |
108 | BIP_RANGE(5), |
109 | UNI_RANGE(10) |
110 | } |
111 | }; |
112 | |
113 | enum me_boardid { |
114 | BOARD_ME2600, |
115 | BOARD_ME2000, |
116 | }; |
117 | |
118 | struct me_board { |
119 | const char *name; |
120 | int needs_firmware; |
121 | int has_ao; |
122 | }; |
123 | |
124 | static const struct me_board me_boards[] = { |
125 | [BOARD_ME2600] = { |
126 | .name = "me-2600i" , |
127 | .needs_firmware = 1, |
128 | .has_ao = 1, |
129 | }, |
130 | [BOARD_ME2000] = { |
131 | .name = "me-2000i" , |
132 | }, |
133 | }; |
134 | |
135 | struct me_private_data { |
136 | void __iomem *plx_regbase; /* PLX configuration base address */ |
137 | |
138 | unsigned short ctrl1; /* Mirror of CONTROL_1 register */ |
139 | unsigned short ctrl2; /* Mirror of CONTROL_2 register */ |
140 | unsigned short dac_ctrl; /* Mirror of the DAC_CONTROL register */ |
141 | }; |
142 | |
143 | static inline void sleep(unsigned int sec) |
144 | { |
145 | schedule_timeout_interruptible(timeout: sec * HZ); |
146 | } |
147 | |
148 | static int me_dio_insn_config(struct comedi_device *dev, |
149 | struct comedi_subdevice *s, |
150 | struct comedi_insn *insn, |
151 | unsigned int *data) |
152 | { |
153 | struct me_private_data *devpriv = dev->private; |
154 | unsigned int chan = CR_CHAN(insn->chanspec); |
155 | unsigned int mask; |
156 | int ret; |
157 | |
158 | if (chan < 16) |
159 | mask = 0x0000ffff; |
160 | else |
161 | mask = 0xffff0000; |
162 | |
163 | ret = comedi_dio_insn_config(dev, s, insn, data, mask); |
164 | if (ret) |
165 | return ret; |
166 | |
167 | if (s->io_bits & 0x0000ffff) |
168 | devpriv->ctrl2 |= ME_CTRL2_PORT_A_ENA; |
169 | else |
170 | devpriv->ctrl2 &= ~ME_CTRL2_PORT_A_ENA; |
171 | if (s->io_bits & 0xffff0000) |
172 | devpriv->ctrl2 |= ME_CTRL2_PORT_B_ENA; |
173 | else |
174 | devpriv->ctrl2 &= ~ME_CTRL2_PORT_B_ENA; |
175 | |
176 | writew(val: devpriv->ctrl2, addr: dev->mmio + ME_CTRL2_REG); |
177 | |
178 | return insn->n; |
179 | } |
180 | |
181 | static int me_dio_insn_bits(struct comedi_device *dev, |
182 | struct comedi_subdevice *s, |
183 | struct comedi_insn *insn, |
184 | unsigned int *data) |
185 | { |
186 | void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A_REG; |
187 | void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B_REG; |
188 | unsigned int mask; |
189 | unsigned int val; |
190 | |
191 | mask = comedi_dio_update_state(s, data); |
192 | if (mask) { |
193 | if (mask & 0x0000ffff) |
194 | writew(val: (s->state & 0xffff), addr: mmio_porta); |
195 | if (mask & 0xffff0000) |
196 | writew(val: ((s->state >> 16) & 0xffff), addr: mmio_portb); |
197 | } |
198 | |
199 | if (s->io_bits & 0x0000ffff) |
200 | val = s->state & 0xffff; |
201 | else |
202 | val = readw(addr: mmio_porta); |
203 | |
204 | if (s->io_bits & 0xffff0000) |
205 | val |= (s->state & 0xffff0000); |
206 | else |
207 | val |= (readw(addr: mmio_portb) << 16); |
208 | |
209 | data[1] = val; |
210 | |
211 | return insn->n; |
212 | } |
213 | |
214 | static int me_ai_eoc(struct comedi_device *dev, |
215 | struct comedi_subdevice *s, |
216 | struct comedi_insn *insn, |
217 | unsigned long context) |
218 | { |
219 | unsigned int status; |
220 | |
221 | status = readw(addr: dev->mmio + ME_STATUS_REG); |
222 | if ((status & ME_STATUS_ADFIFO_EMPTY) == 0) |
223 | return 0; |
224 | return -EBUSY; |
225 | } |
226 | |
227 | static int me_ai_insn_read(struct comedi_device *dev, |
228 | struct comedi_subdevice *s, |
229 | struct comedi_insn *insn, |
230 | unsigned int *data) |
231 | { |
232 | struct me_private_data *devpriv = dev->private; |
233 | unsigned int chan = CR_CHAN(insn->chanspec); |
234 | unsigned int range = CR_RANGE(insn->chanspec); |
235 | unsigned int aref = CR_AREF(insn->chanspec); |
236 | unsigned int val; |
237 | int ret = 0; |
238 | int i; |
239 | |
240 | /* |
241 | * For differential operation, there are only 8 input channels |
242 | * and only bipolar ranges are available. |
243 | */ |
244 | if (aref & AREF_DIFF) { |
245 | if (chan > 7 || comedi_range_is_unipolar(s, range)) |
246 | return -EINVAL; |
247 | } |
248 | |
249 | /* clear chanlist and ad fifo */ |
250 | devpriv->ctrl2 &= ~(ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA); |
251 | writew(val: devpriv->ctrl2, addr: dev->mmio + ME_CTRL2_REG); |
252 | |
253 | writew(val: 0x00, addr: dev->mmio + ME_STATUS_REG); /* clear interrupts */ |
254 | |
255 | /* enable the chanlist and ADC fifo */ |
256 | devpriv->ctrl2 |= (ME_CTRL2_ADFIFO_ENA | ME_CTRL2_CHANLIST_ENA); |
257 | writew(val: devpriv->ctrl2, addr: dev->mmio + ME_CTRL2_REG); |
258 | |
259 | /* write to channel list fifo */ |
260 | val = ME_AI_FIFO_CHANLIST_CHAN(chan) | ME_AI_FIFO_CHANLIST_GAIN(range); |
261 | if (comedi_range_is_unipolar(s, range)) |
262 | val |= ME_AI_FIFO_CHANLIST_UNIPOLAR; |
263 | if (aref & AREF_DIFF) |
264 | val |= ME_AI_FIFO_CHANLIST_DIFF; |
265 | writew(val, addr: dev->mmio + ME_AI_FIFO_REG); |
266 | |
267 | /* set ADC mode to software trigger */ |
268 | devpriv->ctrl1 |= ME_CTRL1_ADC_MODE_SOFT_TRIG; |
269 | writew(val: devpriv->ctrl1, addr: dev->mmio + ME_CTRL1_REG); |
270 | |
271 | for (i = 0; i < insn->n; i++) { |
272 | /* start ai conversion */ |
273 | readw(addr: dev->mmio + ME_CTRL1_REG); |
274 | |
275 | /* wait for ADC fifo not empty flag */ |
276 | ret = comedi_timeout(dev, s, insn, cb: me_ai_eoc, context: 0); |
277 | if (ret) |
278 | break; |
279 | |
280 | /* get value from ADC fifo */ |
281 | val = readw(addr: dev->mmio + ME_AI_FIFO_REG) & s->maxdata; |
282 | |
283 | /* munge 2's complement value to offset binary */ |
284 | data[i] = comedi_offset_munge(s, val); |
285 | } |
286 | |
287 | /* stop any running conversion */ |
288 | devpriv->ctrl1 &= ~ME_CTRL1_ADC_MODE_MASK; |
289 | writew(val: devpriv->ctrl1, addr: dev->mmio + ME_CTRL1_REG); |
290 | |
291 | return ret ? ret : insn->n; |
292 | } |
293 | |
294 | static int me_ao_insn_write(struct comedi_device *dev, |
295 | struct comedi_subdevice *s, |
296 | struct comedi_insn *insn, |
297 | unsigned int *data) |
298 | { |
299 | struct me_private_data *devpriv = dev->private; |
300 | unsigned int chan = CR_CHAN(insn->chanspec); |
301 | unsigned int range = CR_RANGE(insn->chanspec); |
302 | unsigned int val = s->readback[chan]; |
303 | int i; |
304 | |
305 | /* Enable all DAC */ |
306 | devpriv->ctrl2 |= ME_CTRL2_DAC_ENA; |
307 | writew(val: devpriv->ctrl2, addr: dev->mmio + ME_CTRL2_REG); |
308 | |
309 | /* and set DAC to "buffered" mode */ |
310 | devpriv->ctrl2 |= ME_CTRL2_BUFFERED_DAC; |
311 | writew(val: devpriv->ctrl2, addr: dev->mmio + ME_CTRL2_REG); |
312 | |
313 | /* Set dac-control register */ |
314 | devpriv->dac_ctrl &= ~ME_DAC_CTRL_MASK(chan); |
315 | if (range == 0) |
316 | devpriv->dac_ctrl |= ME_DAC_CTRL_GAIN(chan); |
317 | if (comedi_range_is_bipolar(s, range)) |
318 | devpriv->dac_ctrl |= ME_DAC_CTRL_BIPOLAR(chan); |
319 | writew(val: devpriv->dac_ctrl, addr: dev->mmio + ME_DAC_CTRL_REG); |
320 | |
321 | /* Update dac-control register */ |
322 | readw(addr: dev->mmio + ME_DAC_CTRL_REG); |
323 | |
324 | /* Set data register */ |
325 | for (i = 0; i < insn->n; i++) { |
326 | val = data[i]; |
327 | |
328 | writew(val, addr: dev->mmio + ME_AO_DATA_REG(chan)); |
329 | } |
330 | s->readback[chan] = val; |
331 | |
332 | /* Update dac with data registers */ |
333 | readw(addr: dev->mmio + ME_CTRL2_REG); |
334 | |
335 | return insn->n; |
336 | } |
337 | |
338 | static int me2600_xilinx_download(struct comedi_device *dev, |
339 | const u8 *data, size_t size, |
340 | unsigned long context) |
341 | { |
342 | struct me_private_data *devpriv = dev->private; |
343 | unsigned int value; |
344 | unsigned int file_length; |
345 | unsigned int i; |
346 | |
347 | /* disable irq's on PLX */ |
348 | writel(val: 0x00, addr: devpriv->plx_regbase + PLX9052_INTCSR); |
349 | |
350 | /* First, make a dummy read to reset xilinx */ |
351 | value = readw(addr: dev->mmio + XILINX_DOWNLOAD_RESET); |
352 | |
353 | /* Wait until reset is over */ |
354 | sleep(sec: 1); |
355 | |
356 | /* Write a dummy value to Xilinx */ |
357 | writeb(val: 0x00, addr: dev->mmio + 0x0); |
358 | sleep(sec: 1); |
359 | |
360 | /* |
361 | * Format of the firmware |
362 | * Build longs from the byte-wise coded header |
363 | * Byte 1-3: length of the array |
364 | * Byte 4-7: version |
365 | * Byte 8-11: date |
366 | * Byte 12-15: reserved |
367 | */ |
368 | if (size < 16) |
369 | return -EINVAL; |
370 | |
371 | file_length = (((unsigned int)data[0] & 0xff) << 24) + |
372 | (((unsigned int)data[1] & 0xff) << 16) + |
373 | (((unsigned int)data[2] & 0xff) << 8) + |
374 | ((unsigned int)data[3] & 0xff); |
375 | |
376 | /* |
377 | * Loop for writing firmware byte by byte to xilinx |
378 | * Firmware data start at offset 16 |
379 | */ |
380 | for (i = 0; i < file_length; i++) |
381 | writeb(val: (data[16 + i] & 0xff), addr: dev->mmio + 0x0); |
382 | |
383 | /* Write 5 dummy values to xilinx */ |
384 | for (i = 0; i < 5; i++) |
385 | writeb(val: 0x00, addr: dev->mmio + 0x0); |
386 | |
387 | /* Test if there was an error during download -> INTB was thrown */ |
388 | value = readl(addr: devpriv->plx_regbase + PLX9052_INTCSR); |
389 | if (value & PLX9052_INTCSR_LI2STAT) { |
390 | /* Disable interrupt */ |
391 | writel(val: 0x00, addr: devpriv->plx_regbase + PLX9052_INTCSR); |
392 | dev_err(dev->class_dev, "Xilinx download failed\n" ); |
393 | return -EIO; |
394 | } |
395 | |
396 | /* Wait until the Xilinx is ready for real work */ |
397 | sleep(sec: 1); |
398 | |
399 | /* Enable PLX-Interrupts */ |
400 | writel(PLX9052_INTCSR_LI1ENAB | |
401 | PLX9052_INTCSR_LI1POL | |
402 | PLX9052_INTCSR_PCIENAB, |
403 | addr: devpriv->plx_regbase + PLX9052_INTCSR); |
404 | |
405 | return 0; |
406 | } |
407 | |
408 | static int me_reset(struct comedi_device *dev) |
409 | { |
410 | struct me_private_data *devpriv = dev->private; |
411 | |
412 | /* Reset board */ |
413 | writew(val: 0x00, addr: dev->mmio + ME_CTRL1_REG); |
414 | writew(val: 0x00, addr: dev->mmio + ME_CTRL2_REG); |
415 | writew(val: 0x00, addr: dev->mmio + ME_STATUS_REG); /* clear interrupts */ |
416 | writew(val: 0x00, addr: dev->mmio + ME_DAC_CTRL_REG); |
417 | |
418 | /* Save values in the board context */ |
419 | devpriv->dac_ctrl = 0; |
420 | devpriv->ctrl1 = 0; |
421 | devpriv->ctrl2 = 0; |
422 | |
423 | return 0; |
424 | } |
425 | |
426 | static int me_auto_attach(struct comedi_device *dev, |
427 | unsigned long context) |
428 | { |
429 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
430 | const struct me_board *board = NULL; |
431 | struct me_private_data *devpriv; |
432 | struct comedi_subdevice *s; |
433 | int ret; |
434 | |
435 | if (context < ARRAY_SIZE(me_boards)) |
436 | board = &me_boards[context]; |
437 | if (!board) |
438 | return -ENODEV; |
439 | dev->board_ptr = board; |
440 | dev->board_name = board->name; |
441 | |
442 | devpriv = comedi_alloc_devpriv(dev, size: sizeof(*devpriv)); |
443 | if (!devpriv) |
444 | return -ENOMEM; |
445 | |
446 | ret = comedi_pci_enable(dev); |
447 | if (ret) |
448 | return ret; |
449 | |
450 | devpriv->plx_regbase = pci_ioremap_bar(pdev: pcidev, bar: 0); |
451 | if (!devpriv->plx_regbase) |
452 | return -ENOMEM; |
453 | |
454 | dev->mmio = pci_ioremap_bar(pdev: pcidev, bar: 2); |
455 | if (!dev->mmio) |
456 | return -ENOMEM; |
457 | |
458 | /* Download firmware and reset card */ |
459 | if (board->needs_firmware) { |
460 | ret = comedi_load_firmware(dev, hw_dev: &comedi_to_pci_dev(dev)->dev, |
461 | ME2600_FIRMWARE, |
462 | cb: me2600_xilinx_download, context: 0); |
463 | if (ret < 0) |
464 | return ret; |
465 | } |
466 | me_reset(dev); |
467 | |
468 | ret = comedi_alloc_subdevices(dev, num_subdevices: 3); |
469 | if (ret) |
470 | return ret; |
471 | |
472 | s = &dev->subdevices[0]; |
473 | s->type = COMEDI_SUBD_AI; |
474 | s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_DIFF; |
475 | s->n_chan = 16; |
476 | s->maxdata = 0x0fff; |
477 | s->len_chanlist = 16; |
478 | s->range_table = &me_ai_range; |
479 | s->insn_read = me_ai_insn_read; |
480 | |
481 | s = &dev->subdevices[1]; |
482 | if (board->has_ao) { |
483 | s->type = COMEDI_SUBD_AO; |
484 | s->subdev_flags = SDF_WRITABLE | SDF_COMMON; |
485 | s->n_chan = 4; |
486 | s->maxdata = 0x0fff; |
487 | s->len_chanlist = 4; |
488 | s->range_table = &me_ao_range; |
489 | s->insn_write = me_ao_insn_write; |
490 | |
491 | ret = comedi_alloc_subdev_readback(s); |
492 | if (ret) |
493 | return ret; |
494 | } else { |
495 | s->type = COMEDI_SUBD_UNUSED; |
496 | } |
497 | |
498 | s = &dev->subdevices[2]; |
499 | s->type = COMEDI_SUBD_DIO; |
500 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE; |
501 | s->n_chan = 32; |
502 | s->maxdata = 1; |
503 | s->len_chanlist = 32; |
504 | s->range_table = &range_digital; |
505 | s->insn_bits = me_dio_insn_bits; |
506 | s->insn_config = me_dio_insn_config; |
507 | |
508 | return 0; |
509 | } |
510 | |
511 | static void me_detach(struct comedi_device *dev) |
512 | { |
513 | struct me_private_data *devpriv = dev->private; |
514 | |
515 | if (devpriv) { |
516 | if (dev->mmio) |
517 | me_reset(dev); |
518 | if (devpriv->plx_regbase) |
519 | iounmap(addr: devpriv->plx_regbase); |
520 | } |
521 | comedi_pci_detach(dev); |
522 | } |
523 | |
524 | static struct comedi_driver me_daq_driver = { |
525 | .driver_name = "me_daq" , |
526 | .module = THIS_MODULE, |
527 | .auto_attach = me_auto_attach, |
528 | .detach = me_detach, |
529 | }; |
530 | |
531 | static int me_daq_pci_probe(struct pci_dev *dev, |
532 | const struct pci_device_id *id) |
533 | { |
534 | return comedi_pci_auto_config(pcidev: dev, driver: &me_daq_driver, context: id->driver_data); |
535 | } |
536 | |
537 | static const struct pci_device_id me_daq_pci_table[] = { |
538 | { PCI_VDEVICE(MEILHAUS, 0x2600), BOARD_ME2600 }, |
539 | { PCI_VDEVICE(MEILHAUS, 0x2000), BOARD_ME2000 }, |
540 | { 0 } |
541 | }; |
542 | MODULE_DEVICE_TABLE(pci, me_daq_pci_table); |
543 | |
544 | static struct pci_driver me_daq_pci_driver = { |
545 | .name = "me_daq" , |
546 | .id_table = me_daq_pci_table, |
547 | .probe = me_daq_pci_probe, |
548 | .remove = comedi_pci_auto_unconfig, |
549 | }; |
550 | module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver); |
551 | |
552 | MODULE_AUTHOR("Comedi https://www.comedi.org" ); |
553 | MODULE_DESCRIPTION("Comedi low-level driver" ); |
554 | MODULE_LICENSE("GPL" ); |
555 | MODULE_FIRMWARE(ME2600_FIRMWARE); |
556 | |