1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * PCA953x 4/8/16/24/40 bit I/O ports
4 *
5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * Derived from drivers/i2c/chips/pca9539.c
9 */
10
11#include <linux/atomic.h>
12#include <linux/bitmap.h>
13#include <linux/cleanup.h>
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <linux/i2c.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/mod_devicetable.h>
21#include <linux/module.h>
22#include <linux/mutex.h>
23#include <linux/pm.h>
24#include <linux/regmap.h>
25#include <linux/regulator/consumer.h>
26#include <linux/seq_file.h>
27#include <linux/slab.h>
28
29#include <linux/gpio/consumer.h>
30#include <linux/gpio/driver.h>
31
32#include <linux/pinctrl/pinconf-generic.h>
33
34#include <linux/platform_data/pca953x.h>
35
36#define PCA953X_INPUT 0x00
37#define PCA953X_OUTPUT 0x01
38#define PCA953X_INVERT 0x02
39#define PCA953X_DIRECTION 0x03
40
41#define REG_ADDR_MASK GENMASK(5, 0)
42#define REG_ADDR_EXT BIT(6)
43#define REG_ADDR_AI BIT(7)
44
45#define PCA957X_IN 0x00
46#define PCA957X_INVRT 0x01
47#define PCA957X_BKEN 0x02
48#define PCA957X_PUPD 0x03
49#define PCA957X_CFG 0x04
50#define PCA957X_OUT 0x05
51#define PCA957X_MSK 0x06
52#define PCA957X_INTS 0x07
53
54#define PCAL953X_OUT_STRENGTH 0x20
55#define PCAL953X_IN_LATCH 0x22
56#define PCAL953X_PULL_EN 0x23
57#define PCAL953X_PULL_SEL 0x24
58#define PCAL953X_INT_MASK 0x25
59#define PCAL953X_INT_STAT 0x26
60#define PCAL953X_OUT_CONF 0x27
61
62#define PCAL6524_INT_EDGE 0x28
63#define PCAL6524_INT_CLR 0x2a
64#define PCAL6524_IN_STATUS 0x2b
65#define PCAL6524_OUT_INDCONF 0x2c
66#define PCAL6524_DEBOUNCE 0x2d
67
68#define PCA_GPIO_MASK GENMASK(7, 0)
69
70#define PCAL_GPIO_MASK GENMASK(4, 0)
71#define PCAL_PINCTRL_MASK GENMASK(6, 5)
72
73#define PCA_INT BIT(8)
74#define PCA_PCAL BIT(9)
75#define PCA_LATCH_INT (PCA_PCAL | PCA_INT)
76#define PCA953X_TYPE BIT(12)
77#define PCA957X_TYPE BIT(13)
78#define PCAL653X_TYPE BIT(14)
79#define PCA_TYPE_MASK GENMASK(15, 12)
80
81#define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
82
83static const struct i2c_device_id pca953x_id[] = {
84 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, },
85 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
86 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
87 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, },
88 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
89 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
90 { "pca9536", 4 | PCA953X_TYPE, },
91 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
92 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
93 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
94 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
95 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
96 { "pca9556", 8 | PCA953X_TYPE, },
97 { "pca9557", 8 | PCA953X_TYPE, },
98 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
99 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
100 { "pca9698", 40 | PCA953X_TYPE, },
101
102 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
103 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
104 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
105 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, },
106 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
107 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, },
108 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
109
110 { "max7310", 8 | PCA953X_TYPE, },
111 { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
112 { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
113 { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
114 { "max7318", 16 | PCA953X_TYPE | PCA_INT, },
115 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
116 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
117 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
118 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
119 { "tca9538", 8 | PCA953X_TYPE | PCA_INT, },
120 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
121 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, },
122 { "xra1202", 8 | PCA953X_TYPE },
123 { }
124};
125MODULE_DEVICE_TABLE(i2c, pca953x_id);
126
127#ifdef CONFIG_GPIO_PCA953X_IRQ
128
129#include <linux/acpi.h>
130#include <linux/dmi.h>
131
132static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true };
133
134static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = {
135 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
136 { }
137};
138
139static int pca953x_acpi_get_irq(struct device *dev)
140{
141 int ret;
142
143 ret = devm_acpi_dev_add_driver_gpios(dev, gpios: pca953x_acpi_irq_gpios);
144 if (ret)
145 dev_warn(dev, "can't add GPIO ACPI mapping\n");
146
147 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), con_id: "irq", index: 0);
148 if (ret < 0)
149 return ret;
150
151 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret);
152 return ret;
153}
154
155static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = {
156 {
157 /*
158 * On Intel Galileo Gen 2 board the IRQ pin of one of
159 * the I²C GPIO expanders, which has GpioInt() resource,
160 * is provided as an absolute number instead of being
161 * relative. Since first controller (gpio-sch.c) and
162 * second (gpio-dwapb.c) are at the fixed bases, we may
163 * safely refer to the number in the global space to get
164 * an IRQ out of it.
165 */
166 .matches = {
167 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
168 },
169 },
170 {}
171};
172#endif
173
174static const struct acpi_device_id pca953x_acpi_ids[] = {
175 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
176 { }
177};
178MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
179
180#define MAX_BANK 5
181#define BANK_SZ 8
182#define MAX_LINE (MAX_BANK * BANK_SZ)
183
184#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
185
186struct pca953x_reg_config {
187 int direction;
188 int output;
189 int input;
190 int invert;
191};
192
193static const struct pca953x_reg_config pca953x_regs = {
194 .direction = PCA953X_DIRECTION,
195 .output = PCA953X_OUTPUT,
196 .input = PCA953X_INPUT,
197 .invert = PCA953X_INVERT,
198};
199
200static const struct pca953x_reg_config pca957x_regs = {
201 .direction = PCA957X_CFG,
202 .output = PCA957X_OUT,
203 .input = PCA957X_IN,
204 .invert = PCA957X_INVRT,
205};
206
207struct pca953x_chip {
208 unsigned gpio_start;
209 struct mutex i2c_lock;
210 struct regmap *regmap;
211
212#ifdef CONFIG_GPIO_PCA953X_IRQ
213 struct mutex irq_lock;
214 DECLARE_BITMAP(irq_mask, MAX_LINE);
215 DECLARE_BITMAP(irq_stat, MAX_LINE);
216 DECLARE_BITMAP(irq_trig_raise, MAX_LINE);
217 DECLARE_BITMAP(irq_trig_fall, MAX_LINE);
218 DECLARE_BITMAP(irq_trig_level_high, MAX_LINE);
219 DECLARE_BITMAP(irq_trig_level_low, MAX_LINE);
220#endif
221 atomic_t wakeup_path;
222
223 struct i2c_client *client;
224 struct gpio_chip gpio_chip;
225 unsigned long driver_data;
226 struct regulator *regulator;
227
228 const struct pca953x_reg_config *regs;
229
230 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off);
231 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg,
232 u32 checkbank);
233};
234
235static int pca953x_bank_shift(struct pca953x_chip *chip)
236{
237 return fls(x: (chip->gpio_chip.ngpio - 1) / BANK_SZ);
238}
239
240#define PCA953x_BANK_INPUT BIT(0)
241#define PCA953x_BANK_OUTPUT BIT(1)
242#define PCA953x_BANK_POLARITY BIT(2)
243#define PCA953x_BANK_CONFIG BIT(3)
244
245#define PCA957x_BANK_INPUT BIT(0)
246#define PCA957x_BANK_POLARITY BIT(1)
247#define PCA957x_BANK_BUSHOLD BIT(2)
248#define PCA957x_BANK_CONFIG BIT(4)
249#define PCA957x_BANK_OUTPUT BIT(5)
250
251#define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2)
252#define PCAL9xxx_BANK_PULL_EN BIT(8 + 3)
253#define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4)
254#define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5)
255#define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6)
256
257/*
258 * We care about the following registers:
259 * - Standard set, below 0x40, each port can be replicated up to 8 times
260 * - PCA953x standard
261 * Input port 0x00 + 0 * bank_size R
262 * Output port 0x00 + 1 * bank_size RW
263 * Polarity Inversion port 0x00 + 2 * bank_size RW
264 * Configuration port 0x00 + 3 * bank_size RW
265 * - PCA957x with mixed up registers
266 * Input port 0x00 + 0 * bank_size R
267 * Polarity Inversion port 0x00 + 1 * bank_size RW
268 * Bus hold port 0x00 + 2 * bank_size RW
269 * Configuration port 0x00 + 4 * bank_size RW
270 * Output port 0x00 + 5 * bank_size RW
271 *
272 * - Extended set, above 0x40, often chip specific.
273 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
274 * Input latch register 0x40 + 2 * bank_size RW
275 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW
276 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW
277 * Interrupt mask register 0x40 + 5 * bank_size RW
278 * Interrupt status register 0x40 + 6 * bank_size R
279 *
280 * - Registers with bit 0x80 set, the AI bit
281 * The bit is cleared and the registers fall into one of the
282 * categories above.
283 */
284
285static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
286 u32 checkbank)
287{
288 int bank_shift = pca953x_bank_shift(chip);
289 int bank = (reg & REG_ADDR_MASK) >> bank_shift;
290 int offset = reg & (BIT(bank_shift) - 1);
291
292 /* Special PCAL extended register check. */
293 if (reg & REG_ADDR_EXT) {
294 if (!(chip->driver_data & PCA_PCAL))
295 return false;
296 bank += 8;
297 }
298
299 /* Register is not in the matching bank. */
300 if (!(BIT(bank) & checkbank))
301 return false;
302
303 /* Register is not within allowed range of bank. */
304 if (offset >= NBANK(chip))
305 return false;
306
307 return true;
308}
309
310/*
311 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the
312 * same register layout as the PCAL6524, the spacing of the registers has been
313 * fundamentally altered by compacting them and thus does not obey the same
314 * rules, including being able to use bit shifting to determine bank. These
315 * chips hence need special handling here.
316 */
317static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg,
318 u32 checkbank)
319{
320 int bank_shift;
321 int bank;
322 int offset;
323
324 if (reg >= 0x54) {
325 /*
326 * Handle lack of reserved registers after output port
327 * configuration register to form a bank.
328 */
329 reg -= 0x54;
330 bank_shift = 16;
331 } else if (reg >= 0x30) {
332 /*
333 * Reserved block between 14h and 2Fh does not align on
334 * expected bank boundaries like other devices.
335 */
336 reg -= 0x30;
337 bank_shift = 8;
338 } else {
339 bank_shift = 0;
340 }
341
342 bank = bank_shift + reg / NBANK(chip);
343 offset = reg % NBANK(chip);
344
345 /* Register is not in the matching bank. */
346 if (!(BIT(bank) & checkbank))
347 return false;
348
349 /* Register is not within allowed range of bank. */
350 if (offset >= NBANK(chip))
351 return false;
352
353 return true;
354}
355
356static bool pca953x_readable_register(struct device *dev, unsigned int reg)
357{
358 struct pca953x_chip *chip = dev_get_drvdata(dev);
359 u32 bank;
360
361 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
362 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
363 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
364 PCA957x_BANK_BUSHOLD;
365 } else {
366 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
367 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
368 }
369
370 if (chip->driver_data & PCA_PCAL) {
371 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
372 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
373 PCAL9xxx_BANK_IRQ_STAT;
374 }
375
376 return chip->check_reg(chip, reg, bank);
377}
378
379static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
380{
381 struct pca953x_chip *chip = dev_get_drvdata(dev);
382 u32 bank;
383
384 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
385 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
386 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
387 } else {
388 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
389 PCA953x_BANK_CONFIG;
390 }
391
392 if (chip->driver_data & PCA_PCAL)
393 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
394 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
395
396 return chip->check_reg(chip, reg, bank);
397}
398
399static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
400{
401 struct pca953x_chip *chip = dev_get_drvdata(dev);
402 u32 bank;
403
404 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
405 bank = PCA957x_BANK_INPUT;
406 else
407 bank = PCA953x_BANK_INPUT;
408
409 if (chip->driver_data & PCA_PCAL)
410 bank |= PCAL9xxx_BANK_IRQ_STAT;
411
412 return chip->check_reg(chip, reg, bank);
413}
414
415static const struct regmap_config pca953x_i2c_regmap = {
416 .reg_bits = 8,
417 .val_bits = 8,
418
419 .use_single_read = true,
420 .use_single_write = true,
421
422 .readable_reg = pca953x_readable_register,
423 .writeable_reg = pca953x_writeable_register,
424 .volatile_reg = pca953x_volatile_register,
425
426 .disable_locking = true,
427 .cache_type = REGCACHE_MAPLE,
428 .max_register = 0x7f,
429};
430
431static const struct regmap_config pca953x_ai_i2c_regmap = {
432 .reg_bits = 8,
433 .val_bits = 8,
434
435 .read_flag_mask = REG_ADDR_AI,
436 .write_flag_mask = REG_ADDR_AI,
437
438 .readable_reg = pca953x_readable_register,
439 .writeable_reg = pca953x_writeable_register,
440 .volatile_reg = pca953x_volatile_register,
441
442 .disable_locking = true,
443 .cache_type = REGCACHE_MAPLE,
444 .max_register = 0x7f,
445};
446
447static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off)
448{
449 int bank_shift = pca953x_bank_shift(chip);
450 int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
451 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
452 u8 regaddr = pinctrl | addr | (off / BANK_SZ);
453
454 return regaddr;
455}
456
457/*
458 * The PCAL6534 and compatible chips have altered bank alignment that doesn't
459 * fit within the bit shifting scheme used for other devices.
460 */
461static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off)
462{
463 int addr;
464 int pinctrl;
465
466 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip);
467
468 switch (reg) {
469 case PCAL953X_OUT_STRENGTH:
470 case PCAL953X_IN_LATCH:
471 case PCAL953X_PULL_EN:
472 case PCAL953X_PULL_SEL:
473 case PCAL953X_INT_MASK:
474 case PCAL953X_INT_STAT:
475 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20;
476 break;
477 case PCAL6524_INT_EDGE:
478 case PCAL6524_INT_CLR:
479 case PCAL6524_IN_STATUS:
480 case PCAL6524_OUT_INDCONF:
481 case PCAL6524_DEBOUNCE:
482 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c;
483 break;
484 default:
485 pinctrl = 0;
486 break;
487 }
488
489 return pinctrl + addr + (off / BANK_SZ);
490}
491
492static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
493{
494 u8 regaddr = chip->recalc_addr(chip, reg, 0);
495 u8 value[MAX_BANK];
496 int i, ret;
497
498 for (i = 0; i < NBANK(chip); i++)
499 value[i] = bitmap_get_value8(val, i * BANK_SZ);
500
501 ret = regmap_bulk_write(map: chip->regmap, reg: regaddr, val: value, NBANK(chip));
502 if (ret < 0) {
503 dev_err(&chip->client->dev, "failed writing register: %d\n", ret);
504 return ret;
505 }
506
507 return 0;
508}
509
510static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val)
511{
512 u8 regaddr = chip->recalc_addr(chip, reg, 0);
513 u8 value[MAX_BANK];
514 int i, ret;
515
516 ret = regmap_bulk_read(map: chip->regmap, reg: regaddr, val: value, NBANK(chip));
517 if (ret < 0) {
518 dev_err(&chip->client->dev, "failed reading register: %d\n", ret);
519 return ret;
520 }
521
522 for (i = 0; i < NBANK(chip); i++)
523 bitmap_set_value8(val, value[i], i * BANK_SZ);
524
525 return 0;
526}
527
528static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
529{
530 struct pca953x_chip *chip = gpiochip_get_data(gc);
531 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
532 u8 bit = BIT(off % BANK_SZ);
533
534 guard(mutex)(T: &chip->i2c_lock);
535
536 return regmap_write_bits(map: chip->regmap, reg: dirreg, mask: bit, val: bit);
537}
538
539static int pca953x_gpio_direction_output(struct gpio_chip *gc,
540 unsigned off, int val)
541{
542 struct pca953x_chip *chip = gpiochip_get_data(gc);
543 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
544 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
545 u8 bit = BIT(off % BANK_SZ);
546 int ret;
547
548 guard(mutex)(T: &chip->i2c_lock);
549
550 /* set output level */
551 ret = regmap_write_bits(map: chip->regmap, reg: outreg, mask: bit, val: val ? bit : 0);
552 if (ret)
553 return ret;
554
555 /* then direction */
556 return regmap_write_bits(map: chip->regmap, reg: dirreg, mask: bit, val: 0);
557}
558
559static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
560{
561 struct pca953x_chip *chip = gpiochip_get_data(gc);
562 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off);
563 u8 bit = BIT(off % BANK_SZ);
564 u32 reg_val;
565 int ret;
566
567 scoped_guard(mutex, &chip->i2c_lock)
568 ret = regmap_read(map: chip->regmap, reg: inreg, val: &reg_val);
569 if (ret < 0)
570 return ret;
571
572 return !!(reg_val & bit);
573}
574
575static int pca953x_gpio_set_value(struct gpio_chip *gc, unsigned int off,
576 int val)
577{
578 struct pca953x_chip *chip = gpiochip_get_data(gc);
579 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off);
580 u8 bit = BIT(off % BANK_SZ);
581
582 guard(mutex)(T: &chip->i2c_lock);
583
584 return regmap_write_bits(map: chip->regmap, reg: outreg, mask: bit, val: val ? bit : 0);
585}
586
587static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
588{
589 struct pca953x_chip *chip = gpiochip_get_data(gc);
590 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off);
591 u8 bit = BIT(off % BANK_SZ);
592 u32 reg_val;
593 int ret;
594
595 scoped_guard(mutex, &chip->i2c_lock)
596 ret = regmap_read(map: chip->regmap, reg: dirreg, val: &reg_val);
597 if (ret < 0)
598 return ret;
599
600 if (reg_val & bit)
601 return GPIO_LINE_DIRECTION_IN;
602
603 return GPIO_LINE_DIRECTION_OUT;
604}
605
606static int pca953x_gpio_get_multiple(struct gpio_chip *gc,
607 unsigned long *mask, unsigned long *bits)
608{
609 struct pca953x_chip *chip = gpiochip_get_data(gc);
610 DECLARE_BITMAP(reg_val, MAX_LINE);
611 int ret;
612
613 scoped_guard(mutex, &chip->i2c_lock)
614 ret = pca953x_read_regs(chip, reg: chip->regs->input, val: reg_val);
615 if (ret)
616 return ret;
617
618 bitmap_replace(dst: bits, old: bits, new: reg_val, mask, nbits: gc->ngpio);
619 return 0;
620}
621
622static int pca953x_gpio_set_multiple(struct gpio_chip *gc,
623 unsigned long *mask, unsigned long *bits)
624{
625 struct pca953x_chip *chip = gpiochip_get_data(gc);
626 DECLARE_BITMAP(reg_val, MAX_LINE);
627 int ret;
628
629 guard(mutex)(T: &chip->i2c_lock);
630
631 ret = pca953x_read_regs(chip, reg: chip->regs->output, val: reg_val);
632 if (ret)
633 return ret;
634
635 bitmap_replace(dst: reg_val, old: reg_val, new: bits, mask, nbits: gc->ngpio);
636
637 return pca953x_write_regs(chip, reg: chip->regs->output, val: reg_val);
638}
639
640static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
641 unsigned int offset,
642 unsigned long config)
643{
644 enum pin_config_param param = pinconf_to_config_param(config);
645 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset);
646 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset);
647 u8 bit = BIT(offset % BANK_SZ);
648 int ret;
649
650 /*
651 * pull-up/pull-down configuration requires PCAL extended
652 * registers
653 */
654 if (!(chip->driver_data & PCA_PCAL))
655 return -ENOTSUPP;
656
657 guard(mutex)(T: &chip->i2c_lock);
658
659 /* Configure pull-up/pull-down */
660 if (param == PIN_CONFIG_BIAS_PULL_UP)
661 ret = regmap_write_bits(map: chip->regmap, reg: pull_sel_reg, mask: bit, val: bit);
662 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
663 ret = regmap_write_bits(map: chip->regmap, reg: pull_sel_reg, mask: bit, val: 0);
664 else
665 ret = 0;
666 if (ret)
667 return ret;
668
669 /* Disable/Enable pull-up/pull-down */
670 if (param == PIN_CONFIG_BIAS_DISABLE)
671 return regmap_write_bits(map: chip->regmap, reg: pull_en_reg, mask: bit, val: 0);
672 else
673 return regmap_write_bits(map: chip->regmap, reg: pull_en_reg, mask: bit, val: bit);
674}
675
676static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
677 unsigned long config)
678{
679 struct pca953x_chip *chip = gpiochip_get_data(gc);
680
681 switch (pinconf_to_config_param(config)) {
682 case PIN_CONFIG_BIAS_PULL_UP:
683 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
684 case PIN_CONFIG_BIAS_PULL_DOWN:
685 case PIN_CONFIG_BIAS_DISABLE:
686 return pca953x_gpio_set_pull_up_down(chip, offset, config);
687 default:
688 return -ENOTSUPP;
689 }
690}
691
692static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
693{
694 struct gpio_chip *gc = &chip->gpio_chip;
695
696 gc->direction_input = pca953x_gpio_direction_input;
697 gc->direction_output = pca953x_gpio_direction_output;
698 gc->get = pca953x_gpio_get_value;
699 gc->set_rv = pca953x_gpio_set_value;
700 gc->get_direction = pca953x_gpio_get_direction;
701 gc->get_multiple = pca953x_gpio_get_multiple;
702 gc->set_multiple_rv = pca953x_gpio_set_multiple;
703 gc->set_config = pca953x_gpio_set_config;
704 gc->can_sleep = true;
705
706 gc->base = chip->gpio_start;
707 gc->ngpio = gpios;
708 gc->label = dev_name(dev: &chip->client->dev);
709 gc->parent = &chip->client->dev;
710 gc->owner = THIS_MODULE;
711}
712
713#ifdef CONFIG_GPIO_PCA953X_IRQ
714static void pca953x_irq_mask(struct irq_data *d)
715{
716 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
717 struct pca953x_chip *chip = gpiochip_get_data(gc);
718 irq_hw_number_t hwirq = irqd_to_hwirq(d);
719
720 clear_bit(nr: hwirq, addr: chip->irq_mask);
721 gpiochip_disable_irq(gc, offset: hwirq);
722}
723
724static void pca953x_irq_unmask(struct irq_data *d)
725{
726 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
727 struct pca953x_chip *chip = gpiochip_get_data(gc);
728 irq_hw_number_t hwirq = irqd_to_hwirq(d);
729
730 gpiochip_enable_irq(gc, offset: hwirq);
731 set_bit(nr: hwirq, addr: chip->irq_mask);
732}
733
734static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
735{
736 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
737 struct pca953x_chip *chip = gpiochip_get_data(gc);
738
739 if (on)
740 atomic_inc(v: &chip->wakeup_path);
741 else
742 atomic_dec(v: &chip->wakeup_path);
743
744 return irq_set_irq_wake(irq: chip->client->irq, on);
745}
746
747static void pca953x_irq_bus_lock(struct irq_data *d)
748{
749 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
750 struct pca953x_chip *chip = gpiochip_get_data(gc);
751
752 mutex_lock(&chip->irq_lock);
753}
754
755static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
756{
757 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
758 struct pca953x_chip *chip = gpiochip_get_data(gc);
759 DECLARE_BITMAP(irq_mask, MAX_LINE);
760 DECLARE_BITMAP(reg_direction, MAX_LINE);
761 int level;
762
763 if (chip->driver_data & PCA_PCAL) {
764 guard(mutex)(T: &chip->i2c_lock);
765
766 /* Enable latch on interrupt-enabled inputs */
767 pca953x_write_regs(chip, PCAL953X_IN_LATCH, val: chip->irq_mask);
768
769 bitmap_complement(dst: irq_mask, src: chip->irq_mask, nbits: gc->ngpio);
770
771 /* Unmask enabled interrupts */
772 pca953x_write_regs(chip, PCAL953X_INT_MASK, val: irq_mask);
773 }
774
775 /* Switch direction to input if needed */
776 pca953x_read_regs(chip, reg: chip->regs->direction, val: reg_direction);
777
778 bitmap_or(dst: irq_mask, src1: chip->irq_trig_fall, src2: chip->irq_trig_raise, nbits: gc->ngpio);
779 bitmap_or(dst: irq_mask, src1: irq_mask, src2: chip->irq_trig_level_high, nbits: gc->ngpio);
780 bitmap_or(dst: irq_mask, src1: irq_mask, src2: chip->irq_trig_level_low, nbits: gc->ngpio);
781 bitmap_complement(dst: reg_direction, src: reg_direction, nbits: gc->ngpio);
782 bitmap_and(dst: irq_mask, src1: irq_mask, src2: reg_direction, nbits: gc->ngpio);
783
784 /* Look for any newly setup interrupt */
785 for_each_set_bit(level, irq_mask, gc->ngpio)
786 pca953x_gpio_direction_input(gc: &chip->gpio_chip, off: level);
787
788 mutex_unlock(lock: &chip->irq_lock);
789}
790
791static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
792{
793 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
794 struct pca953x_chip *chip = gpiochip_get_data(gc);
795 struct device *dev = &chip->client->dev;
796 irq_hw_number_t hwirq = irqd_to_hwirq(d);
797
798 if (!(type & IRQ_TYPE_SENSE_MASK)) {
799 dev_err(dev, "irq %d: unsupported type %d\n", d->irq, type);
800 return -EINVAL;
801 }
802
803 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING);
804 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING);
805 assign_bit(hwirq, chip->irq_trig_level_low, type & IRQ_TYPE_LEVEL_LOW);
806 assign_bit(hwirq, chip->irq_trig_level_high, type & IRQ_TYPE_LEVEL_HIGH);
807
808 return 0;
809}
810
811static void pca953x_irq_shutdown(struct irq_data *d)
812{
813 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
814 struct pca953x_chip *chip = gpiochip_get_data(gc);
815 irq_hw_number_t hwirq = irqd_to_hwirq(d);
816
817 clear_bit(nr: hwirq, addr: chip->irq_trig_raise);
818 clear_bit(nr: hwirq, addr: chip->irq_trig_fall);
819 clear_bit(nr: hwirq, addr: chip->irq_trig_level_low);
820 clear_bit(nr: hwirq, addr: chip->irq_trig_level_high);
821}
822
823static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p)
824{
825 struct gpio_chip *gc = irq_data_get_irq_chip_data(d: data);
826
827 seq_puts(m: p, s: dev_name(dev: gc->parent));
828}
829
830static const struct irq_chip pca953x_irq_chip = {
831 .irq_mask = pca953x_irq_mask,
832 .irq_unmask = pca953x_irq_unmask,
833 .irq_set_wake = pca953x_irq_set_wake,
834 .irq_bus_lock = pca953x_irq_bus_lock,
835 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
836 .irq_set_type = pca953x_irq_set_type,
837 .irq_shutdown = pca953x_irq_shutdown,
838 .irq_print_chip = pca953x_irq_print_chip,
839 .flags = IRQCHIP_IMMUTABLE,
840 GPIOCHIP_IRQ_RESOURCE_HELPERS,
841};
842
843static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending)
844{
845 struct gpio_chip *gc = &chip->gpio_chip;
846 DECLARE_BITMAP(reg_direction, MAX_LINE);
847 DECLARE_BITMAP(old_stat, MAX_LINE);
848 DECLARE_BITMAP(cur_stat, MAX_LINE);
849 DECLARE_BITMAP(new_stat, MAX_LINE);
850 DECLARE_BITMAP(trigger, MAX_LINE);
851 DECLARE_BITMAP(edges, MAX_LINE);
852 int ret;
853
854 ret = pca953x_read_regs(chip, reg: chip->regs->input, val: cur_stat);
855 if (ret)
856 return false;
857
858 /* Remove output pins from the equation */
859 pca953x_read_regs(chip, reg: chip->regs->direction, val: reg_direction);
860
861 bitmap_copy(dst: old_stat, src: chip->irq_stat, nbits: gc->ngpio);
862
863 bitmap_and(dst: new_stat, src1: cur_stat, src2: reg_direction, nbits: gc->ngpio);
864 bitmap_xor(dst: cur_stat, src1: new_stat, src2: old_stat, nbits: gc->ngpio);
865 bitmap_and(dst: trigger, src1: cur_stat, src2: chip->irq_mask, nbits: gc->ngpio);
866
867 bitmap_copy(dst: chip->irq_stat, src: new_stat, nbits: gc->ngpio);
868
869 if (bitmap_empty(src: chip->irq_trig_level_high, nbits: gc->ngpio) &&
870 bitmap_empty(src: chip->irq_trig_level_low, nbits: gc->ngpio)) {
871 if (bitmap_empty(src: trigger, nbits: gc->ngpio))
872 return false;
873 }
874
875 bitmap_and(dst: cur_stat, src1: chip->irq_trig_fall, src2: old_stat, nbits: gc->ngpio);
876 bitmap_and(dst: old_stat, src1: chip->irq_trig_raise, src2: new_stat, nbits: gc->ngpio);
877 bitmap_or(dst: edges, src1: old_stat, src2: cur_stat, nbits: gc->ngpio);
878 bitmap_and(dst: pending, src1: edges, src2: trigger, nbits: gc->ngpio);
879
880 bitmap_and(dst: cur_stat, src1: new_stat, src2: chip->irq_trig_level_high, nbits: gc->ngpio);
881 bitmap_and(dst: cur_stat, src1: cur_stat, src2: chip->irq_mask, nbits: gc->ngpio);
882 bitmap_or(dst: pending, src1: pending, src2: cur_stat, nbits: gc->ngpio);
883
884 bitmap_complement(dst: cur_stat, src: new_stat, nbits: gc->ngpio);
885 bitmap_and(dst: cur_stat, src1: cur_stat, src2: reg_direction, nbits: gc->ngpio);
886 bitmap_and(dst: old_stat, src1: cur_stat, src2: chip->irq_trig_level_low, nbits: gc->ngpio);
887 bitmap_and(dst: old_stat, src1: old_stat, src2: chip->irq_mask, nbits: gc->ngpio);
888 bitmap_or(dst: pending, src1: pending, src2: old_stat, nbits: gc->ngpio);
889
890 return !bitmap_empty(src: pending, nbits: gc->ngpio);
891}
892
893static irqreturn_t pca953x_irq_handler(int irq, void *devid)
894{
895 struct pca953x_chip *chip = devid;
896 struct gpio_chip *gc = &chip->gpio_chip;
897 DECLARE_BITMAP(pending, MAX_LINE);
898 int level;
899 bool ret;
900
901 bitmap_zero(dst: pending, MAX_LINE);
902
903 scoped_guard(mutex, &chip->i2c_lock)
904 ret = pca953x_irq_pending(chip, pending);
905 if (ret) {
906 ret = 0;
907
908 for_each_set_bit(level, pending, gc->ngpio) {
909 int nested_irq = irq_find_mapping(domain: gc->irq.domain, hwirq: level);
910
911 if (unlikely(nested_irq <= 0)) {
912 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level);
913 continue;
914 }
915
916 handle_nested_irq(irq: nested_irq);
917 ret = 1;
918 }
919 }
920
921 return IRQ_RETVAL(ret);
922}
923
924static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
925{
926 struct i2c_client *client = chip->client;
927 struct device *dev = &client->dev;
928 DECLARE_BITMAP(reg_direction, MAX_LINE);
929 DECLARE_BITMAP(irq_stat, MAX_LINE);
930 struct gpio_chip *gc = &chip->gpio_chip;
931 struct gpio_irq_chip *girq;
932 int ret;
933
934 if (dmi_first_match(list: pca953x_dmi_acpi_irq_info)) {
935 ret = pca953x_acpi_get_irq(dev);
936 if (ret > 0)
937 client->irq = ret;
938 }
939
940 if (!client->irq)
941 return 0;
942
943 if (irq_base == -1)
944 return 0;
945
946 if (!(chip->driver_data & PCA_INT))
947 return 0;
948
949 ret = pca953x_read_regs(chip, reg: chip->regs->input, val: irq_stat);
950 if (ret)
951 return ret;
952
953 /*
954 * There is no way to know which GPIO line generated the
955 * interrupt. We have to rely on the previous read for
956 * this purpose.
957 */
958 pca953x_read_regs(chip, reg: chip->regs->direction, val: reg_direction);
959 bitmap_and(dst: chip->irq_stat, src1: irq_stat, src2: reg_direction, nbits: gc->ngpio);
960 mutex_init(&chip->irq_lock);
961
962 girq = &chip->gpio_chip.irq;
963 gpio_irq_chip_set_chip(girq, chip: &pca953x_irq_chip);
964 /* This will let us handle the parent IRQ in the driver */
965 girq->parent_handler = NULL;
966 girq->num_parents = 0;
967 girq->parents = NULL;
968 girq->default_type = IRQ_TYPE_NONE;
969 girq->handler = handle_simple_irq;
970 girq->threaded = true;
971 girq->first = irq_base; /* FIXME: get rid of this */
972
973 ret = devm_request_threaded_irq(dev, irq: client->irq, NULL, thread_fn: pca953x_irq_handler,
974 IRQF_ONESHOT | IRQF_SHARED, devname: dev_name(dev),
975 dev_id: chip);
976 if (ret)
977 return dev_err_probe(dev, err: client->irq, fmt: "failed to request irq\n");
978
979 return 0;
980}
981
982#else /* CONFIG_GPIO_PCA953X_IRQ */
983static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base)
984{
985 struct i2c_client *client = chip->client;
986 struct device *dev = &client->dev;
987
988 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
989 dev_warn(dev, "interrupt support not compiled in\n");
990
991 return 0;
992}
993#endif
994
995static int device_pca95xx_init(struct pca953x_chip *chip)
996{
997 DECLARE_BITMAP(val, MAX_LINE);
998 u8 regaddr;
999 int ret;
1000
1001 regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
1002 ret = regcache_sync_region(map: chip->regmap, min: regaddr,
1003 max: regaddr + NBANK(chip) - 1);
1004 if (ret)
1005 return ret;
1006
1007 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
1008 ret = regcache_sync_region(map: chip->regmap, min: regaddr,
1009 max: regaddr + NBANK(chip) - 1);
1010 if (ret)
1011 return ret;
1012
1013 /* clear polarity inversion */
1014 bitmap_zero(dst: val, MAX_LINE);
1015
1016 return pca953x_write_regs(chip, reg: chip->regs->invert, val);
1017}
1018
1019static int device_pca957x_init(struct pca953x_chip *chip)
1020{
1021 DECLARE_BITMAP(val, MAX_LINE);
1022 unsigned int i;
1023 int ret;
1024
1025 ret = device_pca95xx_init(chip);
1026 if (ret)
1027 return ret;
1028
1029 /* To enable register 6, 7 to control pull up and pull down */
1030 for (i = 0; i < NBANK(chip); i++)
1031 bitmap_set_value8(val, 0x02, i * BANK_SZ);
1032
1033 return pca953x_write_regs(chip, PCA957X_BKEN, val);
1034}
1035
1036static void pca953x_disable_regulator(void *reg)
1037{
1038 regulator_disable(regulator: reg);
1039}
1040
1041static int pca953x_get_and_enable_regulator(struct pca953x_chip *chip)
1042{
1043 struct device *dev = &chip->client->dev;
1044 struct regulator *reg = chip->regulator;
1045 int ret;
1046
1047 reg = devm_regulator_get(dev, id: "vcc");
1048 if (IS_ERR(ptr: reg))
1049 return dev_err_probe(dev, err: PTR_ERR(ptr: reg), fmt: "reg get err\n");
1050
1051 ret = regulator_enable(regulator: reg);
1052 if (ret)
1053 return dev_err_probe(dev, err: ret, fmt: "reg en err\n");
1054
1055 ret = devm_add_action_or_reset(dev, pca953x_disable_regulator, reg);
1056 if (ret)
1057 return ret;
1058
1059 chip->regulator = reg;
1060 return 0;
1061}
1062
1063static int pca953x_probe(struct i2c_client *client)
1064{
1065 struct device *dev = &client->dev;
1066 struct pca953x_platform_data *pdata;
1067 struct pca953x_chip *chip;
1068 int irq_base;
1069 int ret;
1070 const struct regmap_config *regmap_config;
1071
1072 chip = devm_kzalloc(dev, size: sizeof(*chip), GFP_KERNEL);
1073 if (chip == NULL)
1074 return -ENOMEM;
1075
1076 pdata = dev_get_platdata(dev);
1077 if (pdata) {
1078 irq_base = pdata->irq_base;
1079 chip->gpio_start = pdata->gpio_base;
1080 } else {
1081 struct gpio_desc *reset_gpio;
1082
1083 chip->gpio_start = -1;
1084 irq_base = 0;
1085
1086 /*
1087 * See if we need to de-assert a reset pin.
1088 *
1089 * There is no known ACPI-enabled platforms that are
1090 * using "reset" GPIO. Otherwise any of those platform
1091 * must use _DSD method with corresponding property.
1092 */
1093 reset_gpio = devm_gpiod_get_optional(dev, con_id: "reset", flags: GPIOD_OUT_LOW);
1094 if (IS_ERR(ptr: reset_gpio))
1095 return dev_err_probe(dev, err: PTR_ERR(ptr: reset_gpio),
1096 fmt: "Failed to get reset gpio\n");
1097 }
1098
1099 chip->client = client;
1100 chip->driver_data = (uintptr_t)i2c_get_match_data(client);
1101 if (!chip->driver_data)
1102 return -ENODEV;
1103
1104 ret = pca953x_get_and_enable_regulator(chip);
1105 if (ret)
1106 return ret;
1107
1108 i2c_set_clientdata(client, data: chip);
1109
1110 pca953x_setup_gpio(chip, gpios: chip->driver_data & PCA_GPIO_MASK);
1111
1112 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1113 dev_info(dev, "using AI\n");
1114 regmap_config = &pca953x_ai_i2c_regmap;
1115 } else {
1116 dev_info(dev, "using no AI\n");
1117 regmap_config = &pca953x_i2c_regmap;
1118 }
1119
1120 if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) {
1121 chip->recalc_addr = pcal6534_recalc_addr;
1122 chip->check_reg = pcal6534_check_register;
1123 } else {
1124 chip->recalc_addr = pca953x_recalc_addr;
1125 chip->check_reg = pca953x_check_register;
1126 }
1127
1128 chip->regmap = devm_regmap_init_i2c(client, regmap_config);
1129 if (IS_ERR(ptr: chip->regmap))
1130 return PTR_ERR(ptr: chip->regmap);
1131
1132 regcache_mark_dirty(map: chip->regmap);
1133
1134 mutex_init(&chip->i2c_lock);
1135 /*
1136 * In case we have an i2c-mux controlled by a GPIO provided by an
1137 * expander using the same driver higher on the device tree, read the
1138 * i2c adapter nesting depth and use the retrieved value as lockdep
1139 * subclass for chip->i2c_lock.
1140 *
1141 * REVISIT: This solution is not complete. It protects us from lockdep
1142 * false positives when the expander controlling the i2c-mux is on
1143 * a different level on the device tree, but not when it's on the same
1144 * level on a different branch (in which case the subclass number
1145 * would be the same).
1146 *
1147 * TODO: Once a correct solution is developed, a similar fix should be
1148 * applied to all other i2c-controlled GPIO expanders (and potentially
1149 * regmap-i2c).
1150 */
1151 lockdep_set_subclass(&chip->i2c_lock,
1152 i2c_adapter_depth(client->adapter));
1153
1154 /* initialize cached registers from their original values.
1155 * we can't share this chip with another i2c master.
1156 */
1157 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) {
1158 chip->regs = &pca957x_regs;
1159 ret = device_pca957x_init(chip);
1160 } else {
1161 chip->regs = &pca953x_regs;
1162 ret = device_pca95xx_init(chip);
1163 }
1164 if (ret)
1165 return ret;
1166
1167 ret = pca953x_irq_setup(chip, irq_base);
1168 if (ret)
1169 return ret;
1170
1171 return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip);
1172}
1173
1174static int pca953x_regcache_sync(struct pca953x_chip *chip)
1175{
1176 struct device *dev = &chip->client->dev;
1177 int ret;
1178 u8 regaddr;
1179
1180 /*
1181 * The ordering between direction and output is important,
1182 * sync these registers first and only then sync the rest.
1183 */
1184 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0);
1185 ret = regcache_sync_region(map: chip->regmap, min: regaddr, max: regaddr + NBANK(chip) - 1);
1186 if (ret) {
1187 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret);
1188 return ret;
1189 }
1190
1191 regaddr = chip->recalc_addr(chip, chip->regs->output, 0);
1192 ret = regcache_sync_region(map: chip->regmap, min: regaddr, max: regaddr + NBANK(chip) - 1);
1193 if (ret) {
1194 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret);
1195 return ret;
1196 }
1197
1198#ifdef CONFIG_GPIO_PCA953X_IRQ
1199 if (chip->driver_data & PCA_PCAL) {
1200 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0);
1201 ret = regcache_sync_region(map: chip->regmap, min: regaddr,
1202 max: regaddr + NBANK(chip) - 1);
1203 if (ret) {
1204 dev_err(dev, "Failed to sync INT latch registers: %d\n",
1205 ret);
1206 return ret;
1207 }
1208
1209 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0);
1210 ret = regcache_sync_region(map: chip->regmap, min: regaddr,
1211 max: regaddr + NBANK(chip) - 1);
1212 if (ret) {
1213 dev_err(dev, "Failed to sync INT mask registers: %d\n",
1214 ret);
1215 return ret;
1216 }
1217 }
1218#endif
1219
1220 return 0;
1221}
1222
1223static int pca953x_restore_context(struct pca953x_chip *chip)
1224{
1225 int ret;
1226
1227 guard(mutex)(T: &chip->i2c_lock);
1228
1229 if (chip->client->irq > 0)
1230 enable_irq(irq: chip->client->irq);
1231 regcache_cache_only(map: chip->regmap, enable: false);
1232 regcache_mark_dirty(map: chip->regmap);
1233 ret = pca953x_regcache_sync(chip);
1234 if (ret)
1235 return ret;
1236
1237 return regcache_sync(map: chip->regmap);
1238}
1239
1240static void pca953x_save_context(struct pca953x_chip *chip)
1241{
1242 guard(mutex)(T: &chip->i2c_lock);
1243
1244 /* Disable IRQ to prevent early triggering while regmap "cache only" is on */
1245 if (chip->client->irq > 0)
1246 disable_irq(irq: chip->client->irq);
1247 regcache_cache_only(map: chip->regmap, enable: true);
1248}
1249
1250static int pca953x_suspend(struct device *dev)
1251{
1252 struct pca953x_chip *chip = dev_get_drvdata(dev);
1253
1254 pca953x_save_context(chip);
1255
1256 if (atomic_read(v: &chip->wakeup_path))
1257 device_set_wakeup_path(dev);
1258 else
1259 regulator_disable(regulator: chip->regulator);
1260
1261 return 0;
1262}
1263
1264static int pca953x_resume(struct device *dev)
1265{
1266 struct pca953x_chip *chip = dev_get_drvdata(dev);
1267 int ret;
1268
1269 if (!atomic_read(v: &chip->wakeup_path)) {
1270 ret = regulator_enable(regulator: chip->regulator);
1271 if (ret) {
1272 dev_err(dev, "Failed to enable regulator: %d\n", ret);
1273 return 0;
1274 }
1275 }
1276
1277 ret = pca953x_restore_context(chip);
1278 if (ret)
1279 dev_err(dev, "Failed to restore register map: %d\n", ret);
1280
1281 return ret;
1282}
1283
1284static DEFINE_SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume);
1285
1286/* convenience to stop overlong match-table lines */
1287#define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int))
1288#define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
1289#define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
1290
1291static const struct of_device_id pca953x_dt_ids[] = {
1292 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), },
1293 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), },
1294 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
1295 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), },
1296 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
1297 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
1298 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
1299 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
1300 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
1301 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
1302 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
1303 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
1304 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
1305 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
1306 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
1307 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
1308 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
1309
1310 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), },
1311 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), },
1312 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), },
1313 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), },
1314 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), },
1315 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), },
1316 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), },
1317
1318 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
1319 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
1320 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
1321 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
1322 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), },
1323
1324 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
1325 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
1326 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
1327 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
1328 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
1329 { .compatible = "ti,tca9535", .data = OF_953X(16, PCA_INT), },
1330 { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), },
1331 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), },
1332
1333 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), },
1334 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), },
1335 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), },
1336
1337 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
1338 { }
1339};
1340
1341MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
1342
1343static struct i2c_driver pca953x_driver = {
1344 .driver = {
1345 .name = "pca953x",
1346 .pm = pm_sleep_ptr(&pca953x_pm_ops),
1347 .of_match_table = pca953x_dt_ids,
1348 .acpi_match_table = pca953x_acpi_ids,
1349 },
1350 .probe = pca953x_probe,
1351 .id_table = pca953x_id,
1352};
1353
1354static int __init pca953x_init(void)
1355{
1356 return i2c_add_driver(&pca953x_driver);
1357}
1358/* register after i2c postcore initcall and before
1359 * subsys initcalls that may rely on these GPIOs
1360 */
1361subsys_initcall(pca953x_init);
1362
1363static void __exit pca953x_exit(void)
1364{
1365 i2c_del_driver(driver: &pca953x_driver);
1366}
1367module_exit(pca953x_exit);
1368
1369MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
1370MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
1371MODULE_LICENSE("GPL");
1372

source code of linux/drivers/gpio/gpio-pca953x.c