1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "gfxhub_v3_0.h"
26
27#include "gc/gc_11_0_0_offset.h"
28#include "gc/gc_11_0_0_sh_mask.h"
29#include "gc/gc_11_0_0_default.h"
30#include "navi10_enum.h"
31#include "soc15_common.h"
32
33static const char * const gfxhub_client_ids[] = {
34 "CB/DB",
35 "Reserved",
36 "GE1",
37 "GE2",
38 "CPF",
39 "CPC",
40 "CPG",
41 "RLC",
42 "TCP",
43 "SQC (inst)",
44 "SQC (data)",
45 "SQG",
46 "Reserved",
47 "SDMA0",
48 "SDMA1",
49 "GCR",
50 "SDMA2",
51 "SDMA3",
52};
53
54static uint32_t gfxhub_v3_0_get_invalidate_req(unsigned int vmid,
55 uint32_t flush_type)
56{
57 u32 req = 0;
58
59 /* invalidate using legacy mode on vmid*/
60 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
61 PER_VMID_INVALIDATE_REQ, 1 << vmid);
62 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
63 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
64 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
65 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
66 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
67 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
68 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
69 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
70
71 return req;
72}
73
74static void
75gfxhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
76 uint32_t status)
77{
78 u32 cid = REG_GET_FIELD(status,
79 GCVM_L2_PROTECTION_FAULT_STATUS, CID);
80
81 dev_err(adev->dev,
82 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
83 status);
84 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
85 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
86 cid);
87 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
88 REG_GET_FIELD(status,
89 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
90 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
91 REG_GET_FIELD(status,
92 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
93 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
94 REG_GET_FIELD(status,
95 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
96 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
97 REG_GET_FIELD(status,
98 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
99 dev_err(adev->dev, "\t RW: 0x%lx\n",
100 REG_GET_FIELD(status,
101 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
102}
103
104static u64 gfxhub_v3_0_get_fb_location(struct amdgpu_device *adev)
105{
106 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);
107
108 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
109 base <<= 24;
110
111 return base;
112}
113
114static u64 gfxhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev)
115{
116 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;
117}
118
119static void gfxhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
120 uint64_t page_table_base)
121{
122 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
123
124 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
125 hub->ctx_addr_distance * vmid,
126 lower_32_bits(page_table_base));
127
128 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
129 hub->ctx_addr_distance * vmid,
130 upper_32_bits(page_table_base));
131}
132
133static void gfxhub_v3_0_init_gart_aperture_regs(struct amdgpu_device *adev)
134{
135 uint64_t pt_base = amdgpu_gmc_pd_addr(bo: adev->gart.bo);
136
137 gfxhub_v3_0_setup_vm_pt_regs(adev, vmid: 0, page_table_base: pt_base);
138
139 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
140 (u32)(adev->gmc.gart_start >> 12));
141 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
142 (u32)(adev->gmc.gart_start >> 44));
143
144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
145 (u32)(adev->gmc.gart_end >> 12));
146 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
147 (u32)(adev->gmc.gart_end >> 44));
148}
149
150static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)
151{
152 uint64_t value;
153
154 /* Program the AGP BAR */
155 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);
156 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
157 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
158
159
160 /* Program the system aperture low logical page number. */
161 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
162 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
163 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
164 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
165
166 /* Set default page address. */
167 value = amdgpu_gmc_vram_mc2pa(adev, mc_addr: adev->mem_scratch.gpu_addr);
168 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
169 (u32)(value >> 12));
170 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
171 (u32)(value >> 44));
172
173 /* Program "protection fault". */
174 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
175 (u32)(adev->dummy_page_addr >> 12));
176 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
177 (u32)((u64)adev->dummy_page_addr >> 44));
178
179 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
180 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
181}
182
183
184static void gfxhub_v3_0_init_tlb_regs(struct amdgpu_device *adev)
185{
186 uint32_t tmp;
187
188 /* Setup TLB control */
189 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
190
191 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
192 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
193 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
194 ENABLE_ADVANCED_DRIVER_MODEL, 1);
195 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
196 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
197 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
198 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
199 MTYPE, MTYPE_UC); /* UC, uncached */
200
201 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
202}
203
204static void gfxhub_v3_0_init_cache_regs(struct amdgpu_device *adev)
205{
206 uint32_t tmp;
207
208 /* These registers are not accessible to VF-SRIOV.
209 * The PF will program them instead.
210 */
211 if (amdgpu_sriov_vf(adev))
212 return;
213
214 /* Setup L2 cache */
215 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);
216 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
217 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
218 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
219 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
220 /* XXX for emulation, Refer to closed source code.*/
221 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
222 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
225 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
226 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);
227
228 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);
229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
230 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
231 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);
232
233 tmp = regGCVM_L2_CNTL3_DEFAULT;
234 if (adev->gmc.translate_further) {
235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
236 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
237 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
238 } else {
239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
240 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
241 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
242 }
243 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);
244
245 tmp = regGCVM_L2_CNTL4_DEFAULT;
246 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
247 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
248 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);
249
250 tmp = regGCVM_L2_CNTL5_DEFAULT;
251 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
252 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);
253}
254
255static void gfxhub_v3_0_enable_system_domain(struct amdgpu_device *adev)
256{
257 uint32_t tmp;
258
259 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);
260 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
261 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
262 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
263 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
264 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);
265}
266
267static void gfxhub_v3_0_disable_identity_aperture(struct amdgpu_device *adev)
268{
269 /* These registers are not accessible to VF-SRIOV.
270 * The PF will program them instead.
271 */
272 if (amdgpu_sriov_vf(adev))
273 return;
274
275 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
276 0xFFFFFFFF);
277 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
278 0x0000000F);
279
280 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
281 0);
282 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
283 0);
284
285 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
286 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
287
288}
289
290static void gfxhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
291{
292 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
293 int i;
294 uint32_t tmp;
295
296 for (i = 0; i <= 14; i++) {
297 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
298 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
299 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
300 adev->vm_manager.num_level);
301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
302 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
303 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
304 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
305 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
306 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
307 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
308 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
309 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
310 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
311 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
312 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
313 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
314 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
315 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
316 PAGE_TABLE_BLOCK_SIZE,
317 adev->vm_manager.block_size - 9);
318 /* Send no-retry XNACK on fault to suppress VM fault storm. */
319 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
320 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
321 !amdgpu_noretry);
322 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL,
323 i * hub->ctx_distance, tmp);
324 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
325 i * hub->ctx_addr_distance, 0);
326 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
327 i * hub->ctx_addr_distance, 0);
328 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
329 i * hub->ctx_addr_distance,
330 lower_32_bits(adev->vm_manager.max_pfn - 1));
331 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
332 i * hub->ctx_addr_distance,
333 upper_32_bits(adev->vm_manager.max_pfn - 1));
334 }
335
336 hub->vm_cntx_cntl = tmp;
337}
338
339static void gfxhub_v3_0_program_invalidation(struct amdgpu_device *adev)
340{
341 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
342 unsigned int i;
343
344 for (i = 0 ; i < 18; ++i) {
345 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
346 i * hub->eng_addr_distance, 0xffffffff);
347 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
348 i * hub->eng_addr_distance, 0x1f);
349 }
350}
351
352static int gfxhub_v3_0_gart_enable(struct amdgpu_device *adev)
353{
354 if (amdgpu_sriov_vf(adev)) {
355 /*
356 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
357 * VF copy registers so vbios post doesn't program them, for
358 * SRIOV driver need to program them
359 */
360 WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE,
361 adev->gmc.vram_start >> 24);
362 WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_TOP,
363 adev->gmc.vram_end >> 24);
364 }
365
366 /* GART Enable. */
367 gfxhub_v3_0_init_gart_aperture_regs(adev);
368 gfxhub_v3_0_init_system_aperture_regs(adev);
369 gfxhub_v3_0_init_tlb_regs(adev);
370 gfxhub_v3_0_init_cache_regs(adev);
371
372 gfxhub_v3_0_enable_system_domain(adev);
373 gfxhub_v3_0_disable_identity_aperture(adev);
374 gfxhub_v3_0_setup_vmid_config(adev);
375 gfxhub_v3_0_program_invalidation(adev);
376
377 return 0;
378}
379
380static void gfxhub_v3_0_gart_disable(struct amdgpu_device *adev)
381{
382 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
383 u32 tmp;
384 u32 i;
385
386 /* Disable all tables */
387 for (i = 0; i < 16; i++)
388 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL,
389 i * hub->ctx_distance, 0);
390
391 /* Setup TLB control */
392 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
393 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
394 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
395 ENABLE_ADVANCED_DRIVER_MODEL, 0);
396 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
397
398 /* Setup L2 cache */
399 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
400 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0);
401}
402
403/**
404 * gfxhub_v3_0_set_fault_enable_default - update GART/VM fault handling
405 *
406 * @adev: amdgpu_device pointer
407 * @value: true redirects VM faults to the default page
408 */
409static void gfxhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev,
410 bool value)
411{
412 u32 tmp;
413
414 /* NO halt CP when page fault */
415 tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);
416 tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);
417 WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);
418
419 /* These registers are not accessible to VF-SRIOV.
420 * The PF will program them instead.
421 */
422 if (amdgpu_sriov_vf(adev))
423 return;
424
425 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
426 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
427 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
428 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
429 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
430 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
431 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
432 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
433 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
434 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
435 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
436 value);
437 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
438 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
439 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
440 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
441 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
442 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
443 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
444 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
445 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
446 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
447 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
448 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
449 if (!value) {
450 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
451 CRASH_ON_NO_RETRY_FAULT, 1);
452 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
453 CRASH_ON_RETRY_FAULT, 1);
454 }
455 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
456}
457
458static const struct amdgpu_vmhub_funcs gfxhub_v3_0_vmhub_funcs = {
459 .print_l2_protection_fault_status = gfxhub_v3_0_print_l2_protection_fault_status,
460 .get_invalidate_req = gfxhub_v3_0_get_invalidate_req,
461};
462
463static void gfxhub_v3_0_init(struct amdgpu_device *adev)
464{
465 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
466
467 hub->ctx0_ptb_addr_lo32 =
468 SOC15_REG_OFFSET(GC, 0,
469 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
470 hub->ctx0_ptb_addr_hi32 =
471 SOC15_REG_OFFSET(GC, 0,
472 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
473 hub->vm_inv_eng0_sem =
474 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM);
475 hub->vm_inv_eng0_req =
476 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ);
477 hub->vm_inv_eng0_ack =
478 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK);
479 hub->vm_context0_cntl =
480 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL);
481 hub->vm_l2_pro_fault_status =
482 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS);
483 hub->vm_l2_pro_fault_cntl =
484 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
485
486 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL;
487 hub->ctx_addr_distance = regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
488 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
489 hub->eng_distance = regGCVM_INVALIDATE_ENG1_REQ -
490 regGCVM_INVALIDATE_ENG0_REQ;
491 hub->eng_addr_distance = regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
492 regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
493
494 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
495 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
496 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
497 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
498 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
499 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
500 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
501
502 hub->vmhub_funcs = &gfxhub_v3_0_vmhub_funcs;
503}
504
505const struct amdgpu_gfxhub_funcs gfxhub_v3_0_funcs = {
506 .get_fb_location = gfxhub_v3_0_get_fb_location,
507 .get_mc_fb_offset = gfxhub_v3_0_get_mc_fb_offset,
508 .setup_vm_pt_regs = gfxhub_v3_0_setup_vm_pt_regs,
509 .gart_enable = gfxhub_v3_0_gart_enable,
510 .gart_disable = gfxhub_v3_0_gart_disable,
511 .set_fault_enable_default = gfxhub_v3_0_set_fault_enable_default,
512 .init = gfxhub_v3_0_init,
513};
514

source code of linux/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c