1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "amdgpu_jpeg.h"
26#include "soc15.h"
27#include "soc15d.h"
28#include "jpeg_v2_0.h"
29#include "jpeg_v2_5.h"
30
31#include "vcn/vcn_2_5_offset.h"
32#include "vcn/vcn_2_5_sh_mask.h"
33#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
34
35#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET 0x401f
36
37#define JPEG25_MAX_HW_INSTANCES_ARCTURUS 2
38
39static const struct amdgpu_hwip_reg_entry jpeg_reg_list_2_5[] = {
40 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_POWER_STATUS),
41 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_INT_STAT),
42 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_RPTR),
43 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_WPTR),
44 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_CNTL),
45 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_RB_SIZE),
46 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JRBC_STATUS),
47 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_ADDR_MODE),
48 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG),
49 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_Y_GFX10_TILING_SURFACE),
50 SOC15_REG_ENTRY_STR(JPEG, 0, mmJPEG_DEC_UV_GFX10_TILING_SURFACE),
51 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_PITCH),
52 SOC15_REG_ENTRY_STR(JPEG, 0, mmUVD_JPEG_UV_PITCH),
53};
54
55static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
56static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
57static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
58 enum amd_powergating_state state);
59static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
60
61static int amdgpu_ih_clientid_jpeg[] = {
62 SOC15_IH_CLIENTID_VCN,
63 SOC15_IH_CLIENTID_VCN1
64};
65
66/**
67 * jpeg_v2_5_early_init - set function pointers
68 *
69 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
70 *
71 * Set ring and irq function pointers
72 */
73static int jpeg_v2_5_early_init(struct amdgpu_ip_block *ip_block)
74{
75 struct amdgpu_device *adev = ip_block->adev;
76 u32 harvest;
77 int i;
78
79 adev->jpeg.num_jpeg_rings = 1;
80 adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS;
81 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
82 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING);
83 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
84 adev->jpeg.harvest_config |= 1 << i;
85 }
86 if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 |
87 AMDGPU_JPEG_HARVEST_JPEG1))
88 return -ENOENT;
89
90 jpeg_v2_5_set_dec_ring_funcs(adev);
91 jpeg_v2_5_set_irq_funcs(adev);
92 jpeg_v2_5_set_ras_funcs(adev);
93
94 return 0;
95}
96
97/**
98 * jpeg_v2_5_sw_init - sw init for JPEG block
99 *
100 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
101 *
102 * Load firmware and sw initialization
103 */
104static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
105{
106 struct amdgpu_ring *ring;
107 int i, r;
108 struct amdgpu_device *adev = ip_block->adev;
109
110 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
111 if (adev->jpeg.harvest_config & (1 << i))
112 continue;
113
114 /* JPEG TRAP */
115 r = amdgpu_irq_add_id(adev, client_id: amdgpu_ih_clientid_jpeg[i],
116 VCN_2_0__SRCID__JPEG_DECODE, source: &adev->jpeg.inst[i].irq);
117 if (r)
118 return r;
119
120 /* JPEG DJPEG POISON EVENT */
121 r = amdgpu_irq_add_id(adev, client_id: amdgpu_ih_clientid_jpeg[i],
122 VCN_2_6__SRCID_DJPEG0_POISON, source: &adev->jpeg.inst[i].ras_poison_irq);
123 if (r)
124 return r;
125
126 /* JPEG EJPEG POISON EVENT */
127 r = amdgpu_irq_add_id(adev, client_id: amdgpu_ih_clientid_jpeg[i],
128 VCN_2_6__SRCID_EJPEG0_POISON, source: &adev->jpeg.inst[i].ras_poison_irq);
129 if (r)
130 return r;
131 }
132
133 r = amdgpu_jpeg_sw_init(adev);
134 if (r)
135 return r;
136
137 r = amdgpu_jpeg_resume(adev);
138 if (r)
139 return r;
140
141 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
142 if (adev->jpeg.harvest_config & (1 << i))
143 continue;
144
145 ring = adev->jpeg.inst[i].ring_dec;
146 ring->use_doorbell = true;
147 if (amdgpu_ip_version(adev, ip: UVD_HWIP, inst: 0) == IP_VERSION(2, 5, 0))
148 ring->vm_hub = AMDGPU_MMHUB1(0);
149 else
150 ring->vm_hub = AMDGPU_MMHUB0(0);
151 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
152 sprintf(buf: ring->name, fmt: "jpeg_dec_%d", i);
153 r = amdgpu_ring_init(adev, ring, max_dw: 512, irq_src: &adev->jpeg.inst[i].irq,
154 irq_type: 0, hw_prio: AMDGPU_RING_PRIO_DEFAULT, NULL);
155 if (r)
156 return r;
157
158 adev->jpeg.internal.jpeg_pitch[0] = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
159 adev->jpeg.inst[i].external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);
160 }
161
162 r = amdgpu_jpeg_ras_sw_init(adev);
163 if (r)
164 return r;
165
166 r = amdgpu_jpeg_reg_dump_init(adev, reg: jpeg_reg_list_2_5, ARRAY_SIZE(jpeg_reg_list_2_5));
167 if (r)
168 return r;
169
170 adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
171 r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
172
173 return r;
174}
175
176/**
177 * jpeg_v2_5_sw_fini - sw fini for JPEG block
178 *
179 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
180 *
181 * JPEG suspend and free up sw allocation
182 */
183static int jpeg_v2_5_sw_fini(struct amdgpu_ip_block *ip_block)
184{
185 int r;
186 struct amdgpu_device *adev = ip_block->adev;
187
188 r = amdgpu_jpeg_suspend(adev);
189 if (r)
190 return r;
191
192 amdgpu_jpeg_sysfs_reset_mask_fini(adev);
193
194 r = amdgpu_jpeg_sw_fini(adev);
195
196 return r;
197}
198
199/**
200 * jpeg_v2_5_hw_init - start and test JPEG block
201 *
202 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
203 *
204 */
205static int jpeg_v2_5_hw_init(struct amdgpu_ip_block *ip_block)
206{
207 struct amdgpu_device *adev = ip_block->adev;
208 struct amdgpu_ring *ring;
209 int i, r;
210
211 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
212 if (adev->jpeg.harvest_config & (1 << i))
213 continue;
214
215 ring = adev->jpeg.inst[i].ring_dec;
216 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
217 (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i);
218
219 r = amdgpu_ring_test_helper(ring);
220 if (r)
221 return r;
222 }
223
224 return 0;
225}
226
227/**
228 * jpeg_v2_5_hw_fini - stop the hardware block
229 *
230 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
231 *
232 * Stop the JPEG block, mark ring as not ready any more
233 */
234static int jpeg_v2_5_hw_fini(struct amdgpu_ip_block *ip_block)
235{
236 struct amdgpu_device *adev = ip_block->adev;
237 int i;
238
239 cancel_delayed_work_sync(dwork: &adev->jpeg.idle_work);
240
241 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
242 if (adev->jpeg.harvest_config & (1 << i))
243 continue;
244
245 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
246 RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
247 jpeg_v2_5_set_powergating_state(ip_block, state: AMD_PG_STATE_GATE);
248
249 if (amdgpu_ras_is_supported(adev, block: AMDGPU_RAS_BLOCK__JPEG))
250 amdgpu_irq_put(adev, src: &adev->jpeg.inst[i].ras_poison_irq, type: 0);
251 }
252
253 return 0;
254}
255
256/**
257 * jpeg_v2_5_suspend - suspend JPEG block
258 *
259 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
260 *
261 * HW fini and suspend JPEG block
262 */
263static int jpeg_v2_5_suspend(struct amdgpu_ip_block *ip_block)
264{
265 int r;
266
267 r = jpeg_v2_5_hw_fini(ip_block);
268 if (r)
269 return r;
270
271 r = amdgpu_jpeg_suspend(adev: ip_block->adev);
272
273 return r;
274}
275
276/**
277 * jpeg_v2_5_resume - resume JPEG block
278 *
279 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
280 *
281 * Resume firmware and hw init JPEG block
282 */
283static int jpeg_v2_5_resume(struct amdgpu_ip_block *ip_block)
284{
285 int r;
286
287 r = amdgpu_jpeg_resume(adev: ip_block->adev);
288 if (r)
289 return r;
290
291 r = jpeg_v2_5_hw_init(ip_block);
292
293 return r;
294}
295
296static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
297{
298 uint32_t data;
299
300 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
301 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
302 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
303 else
304 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
305
306 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
307 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
308 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
309
310 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
311 data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
312 | JPEG_CGC_GATE__JPEG2_DEC_MASK
313 | JPEG_CGC_GATE__JMCIF_MASK
314 | JPEG_CGC_GATE__JRBBM_MASK);
315 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
316
317 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
318 data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
319 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
320 | JPEG_CGC_CTRL__JMCIF_MODE_MASK
321 | JPEG_CGC_CTRL__JRBBM_MODE_MASK);
322 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
323}
324
325static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
326{
327 uint32_t data;
328
329 data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
330 data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
331 |JPEG_CGC_GATE__JPEG2_DEC_MASK
332 |JPEG_CGC_GATE__JPEG_ENC_MASK
333 |JPEG_CGC_GATE__JMCIF_MASK
334 |JPEG_CGC_GATE__JRBBM_MASK);
335 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
336}
337
338static void jpeg_v2_5_start_inst(struct amdgpu_device *adev, int i)
339{
340 struct amdgpu_ring *ring = adev->jpeg.inst[i].ring_dec;
341 /* disable anti hang mechanism */
342 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
343 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
344
345 /* JPEG disable CGC */
346 jpeg_v2_5_disable_clock_gating(adev, inst: i);
347
348 /* MJPEG global tiling registers */
349 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
350 adev->gfx.config.gb_addr_config);
351 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
352 adev->gfx.config.gb_addr_config);
353
354 /* enable JMI channel */
355 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
356 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
357
358 /* enable System Interrupt for JRBC */
359 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
360 JPEG_SYS_INT_EN__DJRBC_MASK,
361 ~JPEG_SYS_INT_EN__DJRBC_MASK);
362
363 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
364 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
365 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
366 lower_32_bits(ring->gpu_addr));
367 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
368 upper_32_bits(ring->gpu_addr));
369 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);
370 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);
371 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
372 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
373 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
374}
375
376/**
377 * jpeg_v2_5_start - start JPEG block
378 *
379 * @adev: amdgpu_device pointer
380 *
381 * Setup and start the JPEG block
382 */
383static int jpeg_v2_5_start(struct amdgpu_device *adev)
384{
385 int i;
386
387 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
388 if (adev->jpeg.harvest_config & (1 << i))
389 continue;
390 jpeg_v2_5_start_inst(adev, i);
391
392 }
393
394 return 0;
395}
396
397static void jpeg_v2_5_stop_inst(struct amdgpu_device *adev, int i)
398{
399 /* reset JMI */
400 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
401 UVD_JMI_CNTL__SOFT_RESET_MASK,
402 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
403
404 jpeg_v2_5_enable_clock_gating(adev, inst: i);
405
406 /* enable anti hang mechanism */
407 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
408 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
409 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
410}
411
412/**
413 * jpeg_v2_5_stop - stop JPEG block
414 *
415 * @adev: amdgpu_device pointer
416 *
417 * stop the JPEG block
418 */
419static int jpeg_v2_5_stop(struct amdgpu_device *adev)
420{
421 int i;
422
423 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
424 if (adev->jpeg.harvest_config & (1 << i))
425 continue;
426 jpeg_v2_5_stop_inst(adev, i);
427 }
428
429 return 0;
430}
431
432/**
433 * jpeg_v2_5_dec_ring_get_rptr - get read pointer
434 *
435 * @ring: amdgpu_ring pointer
436 *
437 * Returns the current hardware read pointer
438 */
439static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
440{
441 struct amdgpu_device *adev = ring->adev;
442
443 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR);
444}
445
446/**
447 * jpeg_v2_5_dec_ring_get_wptr - get write pointer
448 *
449 * @ring: amdgpu_ring pointer
450 *
451 * Returns the current hardware write pointer
452 */
453static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
454{
455 struct amdgpu_device *adev = ring->adev;
456
457 if (ring->use_doorbell)
458 return *ring->wptr_cpu_addr;
459 else
460 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);
461}
462
463/**
464 * jpeg_v2_5_dec_ring_set_wptr - set write pointer
465 *
466 * @ring: amdgpu_ring pointer
467 *
468 * Commits the write pointer to the hardware
469 */
470static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
471{
472 struct amdgpu_device *adev = ring->adev;
473
474 if (ring->use_doorbell) {
475 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
476 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
477 } else {
478 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
479 }
480}
481
482/**
483 * jpeg_v2_6_dec_ring_insert_start - insert a start command
484 *
485 * @ring: amdgpu_ring pointer
486 *
487 * Write a start command to the ring.
488 */
489static void jpeg_v2_6_dec_ring_insert_start(struct amdgpu_ring *ring)
490{
491 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
492 0, 0, PACKETJ_TYPE0));
493 amdgpu_ring_write(ring, v: 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
494
495 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
496 0, 0, PACKETJ_TYPE0));
497 amdgpu_ring_write(ring, v: 0x80000000 | (1 << (ring->me * 2 + 14)));
498}
499
500/**
501 * jpeg_v2_6_dec_ring_insert_end - insert a end command
502 *
503 * @ring: amdgpu_ring pointer
504 *
505 * Write a end command to the ring.
506 */
507static void jpeg_v2_6_dec_ring_insert_end(struct amdgpu_ring *ring)
508{
509 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
510 0, 0, PACKETJ_TYPE0));
511 amdgpu_ring_write(ring, v: 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
512
513 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
514 0, 0, PACKETJ_TYPE0));
515 amdgpu_ring_write(ring, v: (1 << (ring->me * 2 + 14)));
516}
517
518static bool jpeg_v2_5_is_idle(struct amdgpu_ip_block *ip_block)
519{
520 struct amdgpu_device *adev = ip_block->adev;
521 int i, ret = 1;
522
523 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
524 if (adev->jpeg.harvest_config & (1 << i))
525 continue;
526
527 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) &
528 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
529 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
530 }
531
532 return ret;
533}
534
535static int jpeg_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block)
536{
537 struct amdgpu_device *adev = ip_block->adev;
538 int i, ret;
539
540 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
541 if (adev->jpeg.harvest_config & (1 << i))
542 continue;
543
544 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,
545 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
546 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
547 if (ret)
548 return ret;
549 }
550
551 return 0;
552}
553
554static int jpeg_v2_5_set_clockgating_state(struct amdgpu_ip_block *ip_block,
555 enum amd_clockgating_state state)
556{
557 struct amdgpu_device *adev = ip_block->adev;
558 bool enable = (state == AMD_CG_STATE_GATE);
559 int i;
560
561 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
562 if (adev->jpeg.harvest_config & (1 << i))
563 continue;
564
565 if (enable) {
566 if (!jpeg_v2_5_is_idle(ip_block))
567 return -EBUSY;
568 jpeg_v2_5_enable_clock_gating(adev, inst: i);
569 } else {
570 jpeg_v2_5_disable_clock_gating(adev, inst: i);
571 }
572 }
573
574 return 0;
575}
576
577static int jpeg_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
578 enum amd_powergating_state state)
579{
580 struct amdgpu_device *adev = ip_block->adev;
581 int ret;
582
583 if (state == adev->jpeg.cur_state)
584 return 0;
585
586 if (state == AMD_PG_STATE_GATE)
587 ret = jpeg_v2_5_stop(adev);
588 else
589 ret = jpeg_v2_5_start(adev);
590
591 if (!ret)
592 adev->jpeg.cur_state = state;
593
594 return ret;
595}
596
597static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev,
598 struct amdgpu_irq_src *source,
599 unsigned type,
600 enum amdgpu_interrupt_state state)
601{
602 return 0;
603}
604
605static int jpeg_v2_6_set_ras_interrupt_state(struct amdgpu_device *adev,
606 struct amdgpu_irq_src *source,
607 unsigned int type,
608 enum amdgpu_interrupt_state state)
609{
610 return 0;
611}
612
613static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,
614 struct amdgpu_irq_src *source,
615 struct amdgpu_iv_entry *entry)
616{
617 uint32_t ip_instance;
618
619 switch (entry->client_id) {
620 case SOC15_IH_CLIENTID_VCN:
621 ip_instance = 0;
622 break;
623 case SOC15_IH_CLIENTID_VCN1:
624 ip_instance = 1;
625 break;
626 default:
627 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
628 return 0;
629 }
630
631 DRM_DEBUG("IH: JPEG TRAP\n");
632
633 switch (entry->src_id) {
634 case VCN_2_0__SRCID__JPEG_DECODE:
635 amdgpu_fence_process(ring: adev->jpeg.inst[ip_instance].ring_dec);
636 break;
637 default:
638 DRM_ERROR("Unhandled interrupt: %d %d\n",
639 entry->src_id, entry->src_data[0]);
640 break;
641 }
642
643 return 0;
644}
645
646static int jpeg_v2_5_ring_reset(struct amdgpu_ring *ring, unsigned int vmid)
647{
648 jpeg_v2_5_stop_inst(adev: ring->adev, i: ring->me);
649 jpeg_v2_5_start_inst(adev: ring->adev, i: ring->me);
650 return amdgpu_ring_test_helper(ring);
651}
652
653static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
654 .name = "jpeg_v2_5",
655 .early_init = jpeg_v2_5_early_init,
656 .sw_init = jpeg_v2_5_sw_init,
657 .sw_fini = jpeg_v2_5_sw_fini,
658 .hw_init = jpeg_v2_5_hw_init,
659 .hw_fini = jpeg_v2_5_hw_fini,
660 .suspend = jpeg_v2_5_suspend,
661 .resume = jpeg_v2_5_resume,
662 .is_idle = jpeg_v2_5_is_idle,
663 .wait_for_idle = jpeg_v2_5_wait_for_idle,
664 .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
665 .set_powergating_state = jpeg_v2_5_set_powergating_state,
666 .dump_ip_state = amdgpu_jpeg_dump_ip_state,
667 .print_ip_state = amdgpu_jpeg_print_ip_state,
668};
669
670static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
671 .name = "jpeg_v2_6",
672 .early_init = jpeg_v2_5_early_init,
673 .sw_init = jpeg_v2_5_sw_init,
674 .sw_fini = jpeg_v2_5_sw_fini,
675 .hw_init = jpeg_v2_5_hw_init,
676 .hw_fini = jpeg_v2_5_hw_fini,
677 .suspend = jpeg_v2_5_suspend,
678 .resume = jpeg_v2_5_resume,
679 .is_idle = jpeg_v2_5_is_idle,
680 .wait_for_idle = jpeg_v2_5_wait_for_idle,
681 .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
682 .set_powergating_state = jpeg_v2_5_set_powergating_state,
683 .dump_ip_state = amdgpu_jpeg_dump_ip_state,
684 .print_ip_state = amdgpu_jpeg_print_ip_state,
685};
686
687static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
688 .type = AMDGPU_RING_TYPE_VCN_JPEG,
689 .align_mask = 0xf,
690 .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
691 .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
692 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
693 .parse_cs = jpeg_v2_dec_ring_parse_cs,
694 .emit_frame_size =
695 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
696 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
697 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
698 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
699 8 + 16,
700 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
701 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
702 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
703 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
704 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
705 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
706 .insert_nop = jpeg_v2_0_dec_ring_nop,
707 .insert_start = jpeg_v2_0_dec_ring_insert_start,
708 .insert_end = jpeg_v2_0_dec_ring_insert_end,
709 .pad_ib = amdgpu_ring_generic_pad_ib,
710 .begin_use = amdgpu_jpeg_ring_begin_use,
711 .end_use = amdgpu_jpeg_ring_end_use,
712 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
713 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
714 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
715 .reset = jpeg_v2_5_ring_reset,
716};
717
718static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {
719 .type = AMDGPU_RING_TYPE_VCN_JPEG,
720 .align_mask = 0xf,
721 .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
722 .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
723 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
724 .parse_cs = jpeg_v2_dec_ring_parse_cs,
725 .emit_frame_size =
726 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
727 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
728 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
729 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
730 8 + 16,
731 .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
732 .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
733 .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
734 .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
735 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
736 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
737 .insert_nop = jpeg_v2_0_dec_ring_nop,
738 .insert_start = jpeg_v2_6_dec_ring_insert_start,
739 .insert_end = jpeg_v2_6_dec_ring_insert_end,
740 .pad_ib = amdgpu_ring_generic_pad_ib,
741 .begin_use = amdgpu_jpeg_ring_begin_use,
742 .end_use = amdgpu_jpeg_ring_end_use,
743 .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
744 .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
745 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
746 .reset = jpeg_v2_5_ring_reset,
747};
748
749static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
750{
751 int i;
752
753 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
754 if (adev->jpeg.harvest_config & (1 << i))
755 continue;
756 if (adev->asic_type == CHIP_ARCTURUS)
757 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_5_dec_ring_vm_funcs;
758 else /* CHIP_ALDEBARAN */
759 adev->jpeg.inst[i].ring_dec->funcs = &jpeg_v2_6_dec_ring_vm_funcs;
760 adev->jpeg.inst[i].ring_dec->me = i;
761 }
762}
763
764static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = {
765 .set = jpeg_v2_5_set_interrupt_state,
766 .process = jpeg_v2_5_process_interrupt,
767};
768
769static const struct amdgpu_irq_src_funcs jpeg_v2_6_ras_irq_funcs = {
770 .set = jpeg_v2_6_set_ras_interrupt_state,
771 .process = amdgpu_jpeg_process_poison_irq,
772};
773
774static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev)
775{
776 int i;
777
778 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
779 if (adev->jpeg.harvest_config & (1 << i))
780 continue;
781
782 adev->jpeg.inst[i].irq.num_types = 1;
783 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;
784
785 adev->jpeg.inst[i].ras_poison_irq.num_types = 1;
786 adev->jpeg.inst[i].ras_poison_irq.funcs = &jpeg_v2_6_ras_irq_funcs;
787 }
788}
789
790const struct amdgpu_ip_block_version jpeg_v2_5_ip_block = {
791 .type = AMD_IP_BLOCK_TYPE_JPEG,
792 .major = 2,
793 .minor = 5,
794 .rev = 0,
795 .funcs = &jpeg_v2_5_ip_funcs,
796};
797
798const struct amdgpu_ip_block_version jpeg_v2_6_ip_block = {
799 .type = AMD_IP_BLOCK_TYPE_JPEG,
800 .major = 2,
801 .minor = 6,
802 .rev = 0,
803 .funcs = &jpeg_v2_6_ip_funcs,
804};
805
806static uint32_t jpeg_v2_6_query_poison_by_instance(struct amdgpu_device *adev,
807 uint32_t instance, uint32_t sub_block)
808{
809 uint32_t poison_stat = 0, reg_value = 0;
810
811 switch (sub_block) {
812 case AMDGPU_JPEG_V2_6_JPEG0:
813 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS);
814 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);
815 break;
816 case AMDGPU_JPEG_V2_6_JPEG1:
817 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS);
818 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);
819 break;
820 default:
821 break;
822 }
823
824 if (poison_stat)
825 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n",
826 instance, sub_block);
827
828 return poison_stat;
829}
830
831static bool jpeg_v2_6_query_ras_poison_status(struct amdgpu_device *adev)
832{
833 uint32_t inst = 0, sub = 0, poison_stat = 0;
834
835 for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
836 for (sub = 0; sub < AMDGPU_JPEG_V2_6_MAX_SUB_BLOCK; sub++)
837 poison_stat +=
838 jpeg_v2_6_query_poison_by_instance(adev, instance: inst, sub_block: sub);
839
840 return !!poison_stat;
841}
842
843const struct amdgpu_ras_block_hw_ops jpeg_v2_6_ras_hw_ops = {
844 .query_poison_status = jpeg_v2_6_query_ras_poison_status,
845};
846
847static struct amdgpu_jpeg_ras jpeg_v2_6_ras = {
848 .ras_block = {
849 .hw_ops = &jpeg_v2_6_ras_hw_ops,
850 .ras_late_init = amdgpu_jpeg_ras_late_init,
851 },
852};
853
854static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev)
855{
856 switch (amdgpu_ip_version(adev, ip: JPEG_HWIP, inst: 0)) {
857 case IP_VERSION(2, 6, 0):
858 adev->jpeg.ras = &jpeg_v2_6_ras;
859 break;
860 default:
861 break;
862 }
863}
864

source code of linux/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c