1 | /* |
2 | * Copyright 2023 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include "amdgpu.h" |
25 | #include "mmhub_v3_3.h" |
26 | |
27 | #include "mmhub/mmhub_3_3_0_offset.h" |
28 | #include "mmhub/mmhub_3_3_0_sh_mask.h" |
29 | |
30 | #include "navi10_enum.h" |
31 | #include "soc15_common.h" |
32 | |
33 | #define regMMVM_L2_CNTL3_DEFAULT 0x80100007 |
34 | #define regMMVM_L2_CNTL4_DEFAULT 0x000000c1 |
35 | #define regMMVM_L2_CNTL5_DEFAULT 0x00003fe0 |
36 | |
37 | static const char *mmhub_client_ids_v3_3[][2] = { |
38 | [0][0] = "VMC" , |
39 | [4][0] = "DCEDMC" , |
40 | [6][0] = "MP0" , |
41 | [7][0] = "MP1" , |
42 | [8][0] = "MPM" , |
43 | [24][0] = "HDP" , |
44 | [25][0] = "LSDMA" , |
45 | [26][0] = "JPEG" , |
46 | [27][0] = "VPE" , |
47 | [29][0] = "VCNU" , |
48 | [30][0] = "VCN" , |
49 | [3][1] = "DCEDWB" , |
50 | [4][1] = "DCEDMC" , |
51 | [6][1] = "MP0" , |
52 | [7][1] = "MP1" , |
53 | [8][1] = "MPM" , |
54 | [21][1] = "OSSSYS" , |
55 | [24][1] = "HDP" , |
56 | [25][1] = "LSDMA" , |
57 | [26][1] = "JPEG" , |
58 | [27][1] = "VPE" , |
59 | [29][1] = "VCNU" , |
60 | [30][1] = "VCN" , |
61 | }; |
62 | |
63 | static uint32_t mmhub_v3_3_get_invalidate_req(unsigned int vmid, |
64 | uint32_t flush_type) |
65 | { |
66 | u32 req = 0; |
67 | |
68 | /* invalidate using legacy mode on vmid*/ |
69 | req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, |
70 | PER_VMID_INVALIDATE_REQ, 1 << vmid); |
71 | req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type ? : 1); |
72 | req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); |
73 | req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); |
74 | req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); |
75 | req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); |
76 | req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); |
77 | req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, |
78 | CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); |
79 | |
80 | return req; |
81 | } |
82 | |
83 | static void |
84 | mmhub_v3_3_print_l2_protection_fault_status(struct amdgpu_device *adev, |
85 | uint32_t status) |
86 | { |
87 | uint32_t cid, rw; |
88 | const char *mmhub_cid = NULL; |
89 | |
90 | cid = REG_GET_FIELD(status, |
91 | MMVM_L2_PROTECTION_FAULT_STATUS, CID); |
92 | rw = REG_GET_FIELD(status, |
93 | MMVM_L2_PROTECTION_FAULT_STATUS, RW); |
94 | |
95 | dev_err(adev->dev, |
96 | "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n" , |
97 | status); |
98 | |
99 | switch (amdgpu_ip_version(adev, ip: MMHUB_HWIP, inst: 0)) { |
100 | case IP_VERSION(3, 3, 0): |
101 | case IP_VERSION(3, 3, 1): |
102 | mmhub_cid = cid < ARRAY_SIZE(mmhub_client_ids_v3_3) ? |
103 | mmhub_client_ids_v3_3[cid][rw] : |
104 | cid == 0x140 ? "UMSCH" : NULL; |
105 | break; |
106 | default: |
107 | mmhub_cid = NULL; |
108 | break; |
109 | } |
110 | |
111 | dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n" , |
112 | mmhub_cid ? mmhub_cid : "unknown" , cid); |
113 | dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n" , |
114 | REG_GET_FIELD(status, |
115 | MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS)); |
116 | dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n" , |
117 | REG_GET_FIELD(status, |
118 | MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR)); |
119 | dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n" , |
120 | REG_GET_FIELD(status, |
121 | MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS)); |
122 | dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n" , |
123 | REG_GET_FIELD(status, |
124 | MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR)); |
125 | dev_err(adev->dev, "\t RW: 0x%x\n" , rw); |
126 | } |
127 | |
128 | static void mmhub_v3_3_setup_vm_pt_regs(struct amdgpu_device *adev, |
129 | uint32_t vmid, |
130 | uint64_t page_table_base) |
131 | { |
132 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; |
133 | |
134 | WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, |
135 | hub->ctx_addr_distance * vmid, |
136 | lower_32_bits(page_table_base)); |
137 | |
138 | WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, |
139 | hub->ctx_addr_distance * vmid, |
140 | upper_32_bits(page_table_base)); |
141 | |
142 | } |
143 | |
144 | static void mmhub_v3_3_init_gart_aperture_regs(struct amdgpu_device *adev) |
145 | { |
146 | uint64_t pt_base = amdgpu_gmc_pd_addr(bo: adev->gart.bo); |
147 | |
148 | mmhub_v3_3_setup_vm_pt_regs(adev, vmid: 0, page_table_base: pt_base); |
149 | |
150 | WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, |
151 | (u32)(adev->gmc.gart_start >> 12)); |
152 | WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, |
153 | (u32)(adev->gmc.gart_start >> 44)); |
154 | |
155 | WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, |
156 | (u32)(adev->gmc.gart_end >> 12)); |
157 | WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, |
158 | (u32)(adev->gmc.gart_end >> 44)); |
159 | } |
160 | |
161 | static void mmhub_v3_3_init_system_aperture_regs(struct amdgpu_device *adev) |
162 | { |
163 | uint64_t value; |
164 | uint32_t tmp; |
165 | |
166 | /* Program the AGP BAR */ |
167 | WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); |
168 | WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); |
169 | WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); |
170 | |
171 | /* |
172 | * the new L1 policy will block SRIOV guest from writing |
173 | * these regs, and they will be programed at host. |
174 | * so skip programing these regs. |
175 | */ |
176 | /* Program the system aperture low logical page number. */ |
177 | WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, |
178 | min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); |
179 | WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
180 | max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); |
181 | |
182 | /* Set default page address. */ |
183 | value = amdgpu_gmc_vram_mc2pa(adev, mc_addr: adev->mem_scratch.gpu_addr); |
184 | WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, |
185 | (u32)(value >> 12)); |
186 | WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, |
187 | (u32)(value >> 44)); |
188 | |
189 | /* Program "protection fault". */ |
190 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, |
191 | (u32)(adev->dummy_page_addr >> 12)); |
192 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, |
193 | (u32)((u64)adev->dummy_page_addr >> 44)); |
194 | |
195 | tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2); |
196 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2, |
197 | ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); |
198 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); |
199 | } |
200 | |
201 | static void mmhub_v3_3_init_tlb_regs(struct amdgpu_device *adev) |
202 | { |
203 | uint32_t tmp; |
204 | |
205 | /* Setup TLB control */ |
206 | tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); |
207 | |
208 | tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); |
209 | tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); |
210 | tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, |
211 | ENABLE_ADVANCED_DRIVER_MODEL, 1); |
212 | tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, |
213 | SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); |
214 | tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); |
215 | tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, |
216 | MTYPE, MTYPE_UC); /* UC, uncached */ |
217 | |
218 | WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); |
219 | } |
220 | |
221 | static void mmhub_v3_3_init_cache_regs(struct amdgpu_device *adev) |
222 | { |
223 | uint32_t tmp; |
224 | |
225 | /* Setup L2 cache */ |
226 | tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); |
227 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); |
228 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); |
229 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, |
230 | ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); |
231 | /* XXX for emulation, Refer to closed source code.*/ |
232 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, |
233 | 0); |
234 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); |
235 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); |
236 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); |
237 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); |
238 | |
239 | tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2); |
240 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); |
241 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); |
242 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp); |
243 | |
244 | tmp = regMMVM_L2_CNTL3_DEFAULT; |
245 | if (adev->gmc.translate_further) { |
246 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); |
247 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, |
248 | L2_CACHE_BIGK_FRAGMENT_SIZE, 9); |
249 | } else { |
250 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); |
251 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, |
252 | L2_CACHE_BIGK_FRAGMENT_SIZE, 6); |
253 | } |
254 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp); |
255 | |
256 | tmp = regMMVM_L2_CNTL4_DEFAULT; |
257 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); |
258 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); |
259 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp); |
260 | |
261 | tmp = regMMVM_L2_CNTL5_DEFAULT; |
262 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); |
263 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL5, tmp); |
264 | } |
265 | |
266 | static void mmhub_v3_3_enable_system_domain(struct amdgpu_device *adev) |
267 | { |
268 | uint32_t tmp; |
269 | |
270 | tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL); |
271 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); |
272 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); |
273 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, |
274 | RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); |
275 | |
276 | WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp); |
277 | } |
278 | |
279 | static void mmhub_v3_3_disable_identity_aperture(struct amdgpu_device *adev) |
280 | { |
281 | WREG32_SOC15(MMHUB, 0, |
282 | regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, |
283 | 0xFFFFFFFF); |
284 | WREG32_SOC15(MMHUB, 0, |
285 | regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, |
286 | 0x0000000F); |
287 | |
288 | WREG32_SOC15(MMHUB, 0, |
289 | regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); |
290 | WREG32_SOC15(MMHUB, 0, |
291 | regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); |
292 | |
293 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, |
294 | 0); |
295 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, |
296 | 0); |
297 | } |
298 | |
299 | static void mmhub_v3_3_setup_vmid_config(struct amdgpu_device *adev) |
300 | { |
301 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; |
302 | int i; |
303 | uint32_t tmp; |
304 | |
305 | for (i = 0; i <= 14; i++) { |
306 | tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); |
307 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); |
308 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, |
309 | adev->vm_manager.num_level); |
310 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, |
311 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
312 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, |
313 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, |
314 | 1); |
315 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, |
316 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
317 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, |
318 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
319 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, |
320 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
321 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, |
322 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
323 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, |
324 | EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
325 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, |
326 | PAGE_TABLE_BLOCK_SIZE, |
327 | adev->vm_manager.block_size - 9); |
328 | /* Send no-retry XNACK on fault to suppress VM fault storm. */ |
329 | tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, |
330 | RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, |
331 | !amdgpu_noretry); |
332 | WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, |
333 | i * hub->ctx_distance, tmp); |
334 | WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, |
335 | i * hub->ctx_addr_distance, 0); |
336 | WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, |
337 | i * hub->ctx_addr_distance, 0); |
338 | WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, |
339 | i * hub->ctx_addr_distance, |
340 | lower_32_bits(adev->vm_manager.max_pfn - 1)); |
341 | WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, |
342 | i * hub->ctx_addr_distance, |
343 | upper_32_bits(adev->vm_manager.max_pfn - 1)); |
344 | } |
345 | |
346 | hub->vm_cntx_cntl = tmp; |
347 | } |
348 | |
349 | static void mmhub_v3_3_program_invalidation(struct amdgpu_device *adev) |
350 | { |
351 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; |
352 | unsigned int i; |
353 | |
354 | for (i = 0; i < 18; ++i) { |
355 | WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, |
356 | i * hub->eng_addr_distance, 0xffffffff); |
357 | WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, |
358 | i * hub->eng_addr_distance, 0x1f); |
359 | } |
360 | } |
361 | |
362 | static int mmhub_v3_3_gart_enable(struct amdgpu_device *adev) |
363 | { |
364 | /* GART Enable. */ |
365 | mmhub_v3_3_init_gart_aperture_regs(adev); |
366 | mmhub_v3_3_init_system_aperture_regs(adev); |
367 | mmhub_v3_3_init_tlb_regs(adev); |
368 | mmhub_v3_3_init_cache_regs(adev); |
369 | |
370 | mmhub_v3_3_enable_system_domain(adev); |
371 | mmhub_v3_3_disable_identity_aperture(adev); |
372 | mmhub_v3_3_setup_vmid_config(adev); |
373 | mmhub_v3_3_program_invalidation(adev); |
374 | |
375 | return 0; |
376 | } |
377 | |
378 | static void mmhub_v3_3_gart_disable(struct amdgpu_device *adev) |
379 | { |
380 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; |
381 | u32 tmp; |
382 | u32 i; |
383 | |
384 | /* Disable all tables */ |
385 | for (i = 0; i < 16; i++) |
386 | WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL, |
387 | i * hub->ctx_distance, 0); |
388 | |
389 | /* Setup TLB control */ |
390 | tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL); |
391 | tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); |
392 | tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, |
393 | ENABLE_ADVANCED_DRIVER_MODEL, 0); |
394 | WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp); |
395 | |
396 | /* Setup L2 cache */ |
397 | tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL); |
398 | tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); |
399 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp); |
400 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0); |
401 | } |
402 | |
403 | /** |
404 | * mmhub_v3_3_set_fault_enable_default - update GART/VM fault handling |
405 | * |
406 | * @adev: amdgpu_device pointer |
407 | * @value: true redirects VM faults to the default page |
408 | */ |
409 | static void mmhub_v3_3_set_fault_enable_default(struct amdgpu_device *adev, |
410 | bool value) |
411 | { |
412 | u32 tmp; |
413 | |
414 | tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); |
415 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
416 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
417 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
418 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
419 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
420 | PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
421 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
422 | PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
423 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
424 | TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, |
425 | value); |
426 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
427 | NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
428 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
429 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
430 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
431 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
432 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
433 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
434 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
435 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
436 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
437 | EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); |
438 | if (!value) { |
439 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
440 | CRASH_ON_NO_RETRY_FAULT, 1); |
441 | tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL, |
442 | CRASH_ON_RETRY_FAULT, 1); |
443 | } |
444 | WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp); |
445 | } |
446 | |
447 | static const struct amdgpu_vmhub_funcs mmhub_v3_3_vmhub_funcs = { |
448 | .print_l2_protection_fault_status = mmhub_v3_3_print_l2_protection_fault_status, |
449 | .get_invalidate_req = mmhub_v3_3_get_invalidate_req, |
450 | }; |
451 | |
452 | static void mmhub_v3_3_init(struct amdgpu_device *adev) |
453 | { |
454 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; |
455 | |
456 | hub->ctx0_ptb_addr_lo32 = |
457 | SOC15_REG_OFFSET(MMHUB, 0, |
458 | regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); |
459 | hub->ctx0_ptb_addr_hi32 = |
460 | SOC15_REG_OFFSET(MMHUB, 0, |
461 | regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); |
462 | hub->vm_inv_eng0_sem = |
463 | SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM); |
464 | hub->vm_inv_eng0_req = |
465 | SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ); |
466 | hub->vm_inv_eng0_ack = |
467 | SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK); |
468 | hub->vm_context0_cntl = |
469 | SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL); |
470 | hub->vm_l2_pro_fault_status = |
471 | SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS); |
472 | hub->vm_l2_pro_fault_cntl = |
473 | SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL); |
474 | |
475 | hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL; |
476 | hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - |
477 | regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; |
478 | hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ - |
479 | regMMVM_INVALIDATE_ENG0_REQ; |
480 | hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - |
481 | regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; |
482 | |
483 | hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
484 | MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
485 | MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
486 | MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
487 | MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
488 | MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | |
489 | MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; |
490 | |
491 | hub->vmhub_funcs = &mmhub_v3_3_vmhub_funcs; |
492 | } |
493 | |
494 | static u64 mmhub_v3_3_get_fb_location(struct amdgpu_device *adev) |
495 | { |
496 | u64 base; |
497 | |
498 | base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE); |
499 | base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; |
500 | base <<= 24; |
501 | |
502 | return base; |
503 | } |
504 | |
505 | static u64 mmhub_v3_3_get_mc_fb_offset(struct amdgpu_device *adev) |
506 | { |
507 | u64 offset; |
508 | |
509 | offset = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET); |
510 | offset &= MMMC_VM_FB_OFFSET__FB_OFFSET_MASK; |
511 | offset <<= 24; |
512 | |
513 | return offset; |
514 | } |
515 | |
516 | static void mmhub_v3_3_update_medium_grain_clock_gating(struct amdgpu_device *adev, |
517 | bool enable) |
518 | { |
519 | uint32_t def, data; |
520 | |
521 | def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); |
522 | |
523 | if (enable) |
524 | data |= MM_ATC_L2_MISC_CG__ENABLE_MASK; |
525 | else |
526 | data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK; |
527 | |
528 | if (def != data) |
529 | WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); |
530 | } |
531 | |
532 | static void mmhub_v3_3_update_medium_grain_light_sleep(struct amdgpu_device *adev, |
533 | bool enable) |
534 | { |
535 | uint32_t def, data; |
536 | |
537 | def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); |
538 | |
539 | if (enable) |
540 | data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; |
541 | else |
542 | data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; |
543 | |
544 | if (def != data) |
545 | WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data); |
546 | } |
547 | |
548 | static int mmhub_v3_3_set_clockgating(struct amdgpu_device *adev, |
549 | enum amd_clockgating_state state) |
550 | { |
551 | if (amdgpu_sriov_vf(adev)) |
552 | return 0; |
553 | |
554 | mmhub_v3_3_update_medium_grain_clock_gating(adev, |
555 | enable: state == AMD_CG_STATE_GATE); |
556 | mmhub_v3_3_update_medium_grain_light_sleep(adev, |
557 | enable: state == AMD_CG_STATE_GATE); |
558 | return 0; |
559 | } |
560 | |
561 | static void mmhub_v3_3_get_clockgating(struct amdgpu_device *adev, u64 *flags) |
562 | { |
563 | int data; |
564 | |
565 | if (amdgpu_sriov_vf(adev)) |
566 | *flags = 0; |
567 | |
568 | data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG); |
569 | |
570 | /* AMD_CG_SUPPORT_MC_MGCG */ |
571 | if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK) |
572 | *flags |= AMD_CG_SUPPORT_MC_MGCG; |
573 | |
574 | /* AMD_CG_SUPPORT_MC_LS */ |
575 | if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) |
576 | *flags |= AMD_CG_SUPPORT_MC_LS; |
577 | } |
578 | |
579 | const struct amdgpu_mmhub_funcs mmhub_v3_3_funcs = { |
580 | .init = mmhub_v3_3_init, |
581 | .get_fb_location = mmhub_v3_3_get_fb_location, |
582 | .get_mc_fb_offset = mmhub_v3_3_get_mc_fb_offset, |
583 | .gart_enable = mmhub_v3_3_gart_enable, |
584 | .set_fault_enable_default = mmhub_v3_3_set_fault_enable_default, |
585 | .gart_disable = mmhub_v3_3_gart_disable, |
586 | .set_clockgating = mmhub_v3_3_set_clockgating, |
587 | .get_clockgating = mmhub_v3_3_get_clockgating, |
588 | .setup_vm_pt_regs = mmhub_v3_3_setup_vm_pt_regs, |
589 | }; |
590 | |