1	/* Copyright 2016 Advanced Micro Devices, Inc.
2	*
3	* Permission is hereby granted, free of charge, to any person obtaining a
4	* copy of this software and associated documentation files (the "Software"),
5	* to deal in the Software without restriction, including without limitation
6	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
7	* and/or sell copies of the Software, and to permit persons to whom the
8	* Software is furnished to do so, subject to the following conditions:
9	*
10	* The above copyright notice and this permission notice shall be included in
11	* all copies or substantial portions of the Software.
12	*
13	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19	* OTHER DEALINGS IN THE SOFTWARE.
20	*
21	* Authors: AMD
22	*
23	*/
24
25	#ifndef __DAL_DPP_DCN10_H__
26	#define __DAL_DPP_DCN10_H__
27
28	#include "dpp.h"
29
30	#define TO_DCN10_DPP(dpp)\
31	container_of(dpp, struct dcn10_dpp, base)
32
33	/* TODO: Use correct number of taps. Using polaris values for now */
34	#define LB_TOTAL_NUMBER_OF_ENTRIES 5124
35	#define LB_BITS_PER_ENTRY 144
36
37	#define TF_SF(reg_name, field_name, post_fix)\
38	.field_name = reg_name ## __ ## field_name ## post_fix
39
40	//Used to resolve corner case
41	#define TF2_SF(reg_name, field_name, post_fix)\
42	.field_name = reg_name ## _ ## field_name ## post_fix
43
44	#define TF_REG_LIST_DCN(id) \
45	SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
46	SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
47	SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
48	SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
49	SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
50	SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
51	SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
52	SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
53	SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
54	SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \
55	SRI(DSCL_MEM_PWR_CTRL, DSCL, id), \
56	SRI(OTG_H_BLANK, DSCL, id), \
57	SRI(OTG_V_BLANK, DSCL, id), \
58	SRI(SCL_MODE, DSCL, id), \
59	SRI(LB_DATA_FORMAT, DSCL, id), \
60	SRI(LB_MEMORY_CTRL, DSCL, id), \
61	SRI(DSCL_AUTOCAL, DSCL, id), \
62	SRI(DSCL_CONTROL, DSCL, id), \
63	SRI(SCL_BLACK_OFFSET, DSCL, id), \
64	SRI(SCL_TAP_CONTROL, DSCL, id), \
65	SRI(SCL_COEF_RAM_TAP_SELECT, DSCL, id), \
66	SRI(SCL_COEF_RAM_TAP_DATA, DSCL, id), \
67	SRI(DSCL_2TAP_CONTROL, DSCL, id), \
68	SRI(MPC_SIZE, DSCL, id), \
69	SRI(SCL_HORZ_FILTER_SCALE_RATIO, DSCL, id), \
70	SRI(SCL_VERT_FILTER_SCALE_RATIO, DSCL, id), \
71	SRI(SCL_HORZ_FILTER_SCALE_RATIO_C, DSCL, id), \
72	SRI(SCL_VERT_FILTER_SCALE_RATIO_C, DSCL, id), \
73	SRI(SCL_HORZ_FILTER_INIT, DSCL, id), \
74	SRI(SCL_HORZ_FILTER_INIT_C, DSCL, id), \
75	SRI(SCL_VERT_FILTER_INIT, DSCL, id), \
76	SRI(SCL_VERT_FILTER_INIT_BOT, DSCL, id), \
77	SRI(SCL_VERT_FILTER_INIT_C, DSCL, id), \
78	SRI(SCL_VERT_FILTER_INIT_BOT_C, DSCL, id), \
79	SRI(RECOUT_START, DSCL, id), \
80	SRI(RECOUT_SIZE, DSCL, id), \
81	SRI(CM_ICSC_CONTROL, CM, id), \
82	SRI(CM_ICSC_C11_C12, CM, id), \
83	SRI(CM_ICSC_C33_C34, CM, id), \
84	SRI(CM_DGAM_RAMB_START_CNTL_B, CM, id), \
85	SRI(CM_DGAM_RAMB_START_CNTL_G, CM, id), \
86	SRI(CM_DGAM_RAMB_START_CNTL_R, CM, id), \
87	SRI(CM_DGAM_RAMB_SLOPE_CNTL_B, CM, id), \
88	SRI(CM_DGAM_RAMB_SLOPE_CNTL_G, CM, id), \
89	SRI(CM_DGAM_RAMB_SLOPE_CNTL_R, CM, id), \
90	SRI(CM_DGAM_RAMB_END_CNTL1_B, CM, id), \
91	SRI(CM_DGAM_RAMB_END_CNTL2_B, CM, id), \
92	SRI(CM_DGAM_RAMB_END_CNTL1_G, CM, id), \
93	SRI(CM_DGAM_RAMB_END_CNTL2_G, CM, id), \
94	SRI(CM_DGAM_RAMB_END_CNTL1_R, CM, id), \
95	SRI(CM_DGAM_RAMB_END_CNTL2_R, CM, id), \
96	SRI(CM_DGAM_RAMB_REGION_0_1, CM, id), \
97	SRI(CM_DGAM_RAMB_REGION_14_15, CM, id), \
98	SRI(CM_DGAM_RAMA_START_CNTL_B, CM, id), \
99	SRI(CM_DGAM_RAMA_START_CNTL_G, CM, id), \
100	SRI(CM_DGAM_RAMA_START_CNTL_R, CM, id), \
101	SRI(CM_DGAM_RAMA_SLOPE_CNTL_B, CM, id), \
102	SRI(CM_DGAM_RAMA_SLOPE_CNTL_G, CM, id), \
103	SRI(CM_DGAM_RAMA_SLOPE_CNTL_R, CM, id), \
104	SRI(CM_DGAM_RAMA_END_CNTL1_B, CM, id), \
105	SRI(CM_DGAM_RAMA_END_CNTL2_B, CM, id), \
106	SRI(CM_DGAM_RAMA_END_CNTL1_G, CM, id), \
107	SRI(CM_DGAM_RAMA_END_CNTL2_G, CM, id), \
108	SRI(CM_DGAM_RAMA_END_CNTL1_R, CM, id), \
109	SRI(CM_DGAM_RAMA_END_CNTL2_R, CM, id), \
110	SRI(CM_DGAM_RAMA_REGION_0_1, CM, id), \
111	SRI(CM_DGAM_RAMA_REGION_14_15, CM, id), \
112	SRI(CM_MEM_PWR_CTRL, CM, id), \
113	SRI(CM_DGAM_LUT_WRITE_EN_MASK, CM, id), \
114	SRI(CM_DGAM_LUT_INDEX, CM, id), \
115	SRI(CM_DGAM_LUT_DATA, CM, id), \
116	SRI(CM_CONTROL, CM, id), \
117	SRI(CM_DGAM_CONTROL, CM, id), \
118	SRI(CM_TEST_DEBUG_INDEX, CM, id), \
119	SRI(CM_TEST_DEBUG_DATA, CM, id), \
120	SRI(FORMAT_CONTROL, CNVC_CFG, id), \
121	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
122	SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
123	SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
124	SRI(CURSOR0_COLOR1, CNVC_CUR, id), \
125	SRI(CURSOR0_FP_SCALE_BIAS, CNVC_CUR, id), \
126	SRI(DPP_CONTROL, DPP_TOP, id), \
127	SRI(CM_HDR_MULT_COEF, CM, id)
128
129
130
131	#define TF_REG_LIST_DCN10(id) \
132	TF_REG_LIST_DCN(id), \
133	SRI(CM_COMA_C11_C12, CM, id),\
134	SRI(CM_COMA_C33_C34, CM, id),\
135	SRI(CM_COMB_C11_C12, CM, id),\
136	SRI(CM_COMB_C33_C34, CM, id),\
137	SRI(CM_OCSC_CONTROL, CM, id), \
138	SRI(CM_OCSC_C11_C12, CM, id), \
139	SRI(CM_OCSC_C33_C34, CM, id), \
140	SRI(CM_BNS_VALUES_R, CM, id), \
141	SRI(CM_BNS_VALUES_G, CM, id), \
142	SRI(CM_BNS_VALUES_B, CM, id), \
143	SRI(CM_MEM_PWR_CTRL, CM, id), \
144	SRI(CM_RGAM_LUT_DATA, CM, id), \
145	SRI(CM_RGAM_LUT_WRITE_EN_MASK, CM, id),\
146	SRI(CM_RGAM_LUT_INDEX, CM, id), \
147	SRI(CM_RGAM_RAMB_START_CNTL_B, CM, id), \
148	SRI(CM_RGAM_RAMB_START_CNTL_G, CM, id), \
149	SRI(CM_RGAM_RAMB_START_CNTL_R, CM, id), \
150	SRI(CM_RGAM_RAMB_SLOPE_CNTL_B, CM, id), \
151	SRI(CM_RGAM_RAMB_SLOPE_CNTL_G, CM, id), \
152	SRI(CM_RGAM_RAMB_SLOPE_CNTL_R, CM, id), \
153	SRI(CM_RGAM_RAMB_END_CNTL1_B, CM, id), \
154	SRI(CM_RGAM_RAMB_END_CNTL2_B, CM, id), \
155	SRI(CM_RGAM_RAMB_END_CNTL1_G, CM, id), \
156	SRI(CM_RGAM_RAMB_END_CNTL2_G, CM, id), \
157	SRI(CM_RGAM_RAMB_END_CNTL1_R, CM, id), \
158	SRI(CM_RGAM_RAMB_END_CNTL2_R, CM, id), \
159	SRI(CM_RGAM_RAMB_REGION_0_1, CM, id), \
160	SRI(CM_RGAM_RAMB_REGION_32_33, CM, id), \
161	SRI(CM_RGAM_RAMA_START_CNTL_B, CM, id), \
162	SRI(CM_RGAM_RAMA_START_CNTL_G, CM, id), \
163	SRI(CM_RGAM_RAMA_START_CNTL_R, CM, id), \
164	SRI(CM_RGAM_RAMA_SLOPE_CNTL_B, CM, id), \
165	SRI(CM_RGAM_RAMA_SLOPE_CNTL_G, CM, id), \
166	SRI(CM_RGAM_RAMA_SLOPE_CNTL_R, CM, id), \
167	SRI(CM_RGAM_RAMA_END_CNTL1_B, CM, id), \
168	SRI(CM_RGAM_RAMA_END_CNTL2_B, CM, id), \
169	SRI(CM_RGAM_RAMA_END_CNTL1_G, CM, id), \
170	SRI(CM_RGAM_RAMA_END_CNTL2_G, CM, id), \
171	SRI(CM_RGAM_RAMA_END_CNTL1_R, CM, id), \
172	SRI(CM_RGAM_RAMA_END_CNTL2_R, CM, id), \
173	SRI(CM_RGAM_RAMA_REGION_0_1, CM, id), \
174	SRI(CM_RGAM_RAMA_REGION_32_33, CM, id), \
175	SRI(CM_RGAM_CONTROL, CM, id), \
176	SRI(CM_IGAM_CONTROL, CM, id), \
177	SRI(CM_IGAM_LUT_RW_CONTROL, CM, id), \
178	SRI(CM_IGAM_LUT_RW_INDEX, CM, id), \
179	SRI(CM_IGAM_LUT_SEQ_COLOR, CM, id), \
180	SRI(CURSOR_CONTROL, CURSOR, id), \
181	SRI(CM_CMOUT_CONTROL, CM, id)
182
183
184	#define TF_REG_LIST_SH_MASK_DCN(mask_sh)\
185	TF_SF(CM0_CM_GAMUT_REMAP_CONTROL, CM_GAMUT_REMAP_MODE, mask_sh),\
186	TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C11, mask_sh),\
187	TF_SF(CM0_CM_GAMUT_REMAP_C11_C12, CM_GAMUT_REMAP_C12, mask_sh),\
188	TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C13, mask_sh),\
189	TF_SF(CM0_CM_GAMUT_REMAP_C13_C14, CM_GAMUT_REMAP_C14, mask_sh),\
190	TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C21, mask_sh),\
191	TF_SF(CM0_CM_GAMUT_REMAP_C21_C22, CM_GAMUT_REMAP_C22, mask_sh),\
192	TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C23, mask_sh),\
193	TF_SF(CM0_CM_GAMUT_REMAP_C23_C24, CM_GAMUT_REMAP_C24, mask_sh),\
194	TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C31, mask_sh),\
195	TF_SF(CM0_CM_GAMUT_REMAP_C31_C32, CM_GAMUT_REMAP_C32, mask_sh),\
196	TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C33, mask_sh),\
197	TF_SF(CM0_CM_GAMUT_REMAP_C33_C34, CM_GAMUT_REMAP_C34, mask_sh),\
198	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh),\
199	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh),\
200	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh),\
201	TF_SF(DSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh),\
202	TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_START, mask_sh),\
203	TF_SF(DSCL0_OTG_H_BLANK, OTG_H_BLANK_END, mask_sh),\
204	TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_START, mask_sh),\
205	TF_SF(DSCL0_OTG_V_BLANK, OTG_V_BLANK_END, mask_sh),\
206	TF_SF(DSCL0_LB_DATA_FORMAT, INTERLEAVE_EN, mask_sh),\
207	TF2_SF(DSCL0, LB_DATA_FORMAT__ALPHA_EN, mask_sh),\
208	TF_SF(DSCL0_LB_MEMORY_CTRL, MEMORY_CONFIG, mask_sh),\
209	TF_SF(DSCL0_LB_MEMORY_CTRL, LB_MAX_PARTITIONS, mask_sh),\
210	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_MODE, mask_sh),\
211	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_NUM_PIPE, mask_sh),\
212	TF_SF(DSCL0_DSCL_AUTOCAL, AUTOCAL_PIPE_ID, mask_sh),\
213	TF_SF(DSCL0_DSCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh),\
214	TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_RGB_Y, mask_sh),\
215	TF_SF(DSCL0_SCL_BLACK_OFFSET, SCL_BLACK_OFFSET_CBCR, mask_sh),\
216	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS, mask_sh),\
217	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS, mask_sh),\
218	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_V_NUM_TAPS_C, mask_sh),\
219	TF_SF(DSCL0_SCL_TAP_CONTROL, SCL_H_NUM_TAPS_C, mask_sh),\
220	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
221	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_PHASE, mask_sh),\
222	TF_SF(DSCL0_SCL_COEF_RAM_TAP_SELECT, SCL_COEF_RAM_FILTER_TYPE, mask_sh),\
223	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
224	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
225	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
226	TF_SF(DSCL0_SCL_COEF_RAM_TAP_DATA, SCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
227	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh),\
228	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_EN, mask_sh),\
229	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_H_2TAP_SHARP_FACTOR, mask_sh),\
230	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh),\
231	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_EN, mask_sh),\
232	TF_SF(DSCL0_DSCL_2TAP_CONTROL, SCL_V_2TAP_SHARP_FACTOR, mask_sh),\
233	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT, mask_sh),\
234	TF_SF(DSCL0_SCL_MODE, DSCL_MODE, mask_sh),\
235	TF_SF(DSCL0_RECOUT_START, RECOUT_START_X, mask_sh),\
236	TF_SF(DSCL0_RECOUT_START, RECOUT_START_Y, mask_sh),\
237	TF_SF(DSCL0_RECOUT_SIZE, RECOUT_WIDTH, mask_sh),\
238	TF_SF(DSCL0_RECOUT_SIZE, RECOUT_HEIGHT, mask_sh),\
239	TF_SF(DSCL0_MPC_SIZE, MPC_WIDTH, mask_sh),\
240	TF_SF(DSCL0_MPC_SIZE, MPC_HEIGHT, mask_sh),\
241	TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh),\
242	TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh),\
243	TF_SF(DSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C, SCL_H_SCALE_RATIO_C, mask_sh),\
244	TF_SF(DSCL0_SCL_VERT_FILTER_SCALE_RATIO_C, SCL_V_SCALE_RATIO_C, mask_sh),\
245	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh),\
246	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh),\
247	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_FRAC_C, mask_sh),\
248	TF_SF(DSCL0_SCL_HORZ_FILTER_INIT_C, SCL_H_INIT_INT_C, mask_sh),\
249	TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh),\
250	TF_SF(DSCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh),\
251	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_FRAC_BOT, mask_sh),\
252	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT, SCL_V_INIT_INT_BOT, mask_sh),\
253	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_FRAC_C, mask_sh),\
254	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_C, SCL_V_INIT_INT_C, mask_sh),\
255	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_FRAC_BOT_C, mask_sh),\
256	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\
257	TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\
258	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \
259	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh), \
260	TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh), \
261	TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \
262	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \
263	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
264	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C33, mask_sh), \
265	TF_SF(CM0_CM_ICSC_C33_C34, CM_ICSC_C34, mask_sh), \
266	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_B, mask_sh), \
267	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_B, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
268	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_G, mask_sh), \
269	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_G, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
270	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_R, mask_sh), \
271	TF_SF(CM0_CM_DGAM_RAMB_START_CNTL_R, CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
272	TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_B, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
273	TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_G, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
274	TF_SF(CM0_CM_DGAM_RAMB_SLOPE_CNTL_R, CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
275	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_B, CM_DGAM_RAMB_EXP_REGION_END_B, mask_sh), \
276	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
277	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_B, CM_DGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
278	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_G, CM_DGAM_RAMB_EXP_REGION_END_G, mask_sh), \
279	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
280	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_G, CM_DGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
281	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL1_R, CM_DGAM_RAMB_EXP_REGION_END_R, mask_sh), \
282	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
283	TF_SF(CM0_CM_DGAM_RAMB_END_CNTL2_R, CM_DGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
284	TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
285	TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
286	TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
287	TF_SF(CM0_CM_DGAM_RAMB_REGION_0_1, CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
288	TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh), \
289	TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
290	TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh), \
291	TF_SF(CM0_CM_DGAM_RAMB_REGION_14_15, CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
292	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_B, mask_sh), \
293	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_B, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
294	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_G, mask_sh), \
295	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_G, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
296	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_R, mask_sh), \
297	TF_SF(CM0_CM_DGAM_RAMA_START_CNTL_R, CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
298	TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_B, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
299	TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_G, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
300	TF_SF(CM0_CM_DGAM_RAMA_SLOPE_CNTL_R, CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
301	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_B, CM_DGAM_RAMA_EXP_REGION_END_B, mask_sh), \
302	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
303	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_B, CM_DGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
304	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_G, CM_DGAM_RAMA_EXP_REGION_END_G, mask_sh), \
305	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
306	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_G, CM_DGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
307	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL1_R, CM_DGAM_RAMA_EXP_REGION_END_R, mask_sh), \
308	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
309	TF_SF(CM0_CM_DGAM_RAMA_END_CNTL2_R, CM_DGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
310	TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
311	TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
312	TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
313	TF_SF(CM0_CM_DGAM_RAMA_REGION_0_1, CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
314	TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh), \
315	TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh), \
316	TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh), \
317	TF_SF(CM0_CM_DGAM_RAMA_REGION_14_15, CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh), \
318	TF_SF(CM0_CM_MEM_PWR_CTRL, SHARED_MEM_PWR_DIS, mask_sh), \
319	TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_EN_MASK, mask_sh), \
320	TF_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
321	TF_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
322	TF_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
323	TF_SF(CM0_CM_DGAM_CONTROL, CM_DGAM_LUT_MODE, mask_sh), \
324	TF_SF(CM0_CM_TEST_DEBUG_INDEX, CM_TEST_DEBUG_INDEX, mask_sh), \
325	TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
326	TF2_SF(CNVC_CFG0, FORMAT_CONTROL__ALPHA_EN, mask_sh), \
327	TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \
328	TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
329	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \
330	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \
331	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \
332	TF_SF(CNVC_CUR0_CURSOR0_COLOR0, CUR0_COLOR0, mask_sh), \
333	TF_SF(CNVC_CUR0_CURSOR0_COLOR1, CUR0_COLOR1, mask_sh), \
334	TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, mask_sh), \
335	TF_SF(CNVC_CUR0_CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, mask_sh), \
336	TF_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
337	TF_SF(CM0_CM_HDR_MULT_COEF, CM_HDR_MULT_COEF, mask_sh)
338
339	#define TF_REG_LIST_SH_MASK_DCN10(mask_sh)\
340	TF_REG_LIST_SH_MASK_DCN(mask_sh),\
341	TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh),\
342	TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh),\
343	TF_SF(DSCL0_LB_DATA_FORMAT, PIXEL_REDUCE_MODE, mask_sh),\
344	TF_SF(DSCL0_LB_DATA_FORMAT, DYNAMIC_PIXEL_DEPTH, mask_sh),\
345	TF_SF(DSCL0_LB_DATA_FORMAT, DITHER_EN, mask_sh),\
346	TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C11, mask_sh),\
347	TF_SF(CM0_CM_COMA_C11_C12, CM_COMA_C12, mask_sh),\
348	TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C33, mask_sh),\
349	TF_SF(CM0_CM_COMA_C33_C34, CM_COMA_C34, mask_sh),\
350	TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C11, mask_sh),\
351	TF_SF(CM0_CM_COMB_C11_C12, CM_COMB_C12, mask_sh),\
352	TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C33, mask_sh),\
353	TF_SF(CM0_CM_COMB_C33_C34, CM_COMB_C34, mask_sh),\
354	TF_SF(CM0_CM_OCSC_CONTROL, CM_OCSC_MODE, mask_sh), \
355	TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C11, mask_sh), \
356	TF_SF(CM0_CM_OCSC_C11_C12, CM_OCSC_C12, mask_sh), \
357	TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C33, mask_sh), \
358	TF_SF(CM0_CM_OCSC_C33_C34, CM_OCSC_C34, mask_sh), \
359	TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_BIAS_R, mask_sh), \
360	TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_BIAS_G, mask_sh), \
361	TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_BIAS_B, mask_sh), \
362	TF_SF(CM0_CM_BNS_VALUES_R, CM_BNS_SCALE_R, mask_sh), \
363	TF_SF(CM0_CM_BNS_VALUES_G, CM_BNS_SCALE_G, mask_sh), \
364	TF_SF(CM0_CM_BNS_VALUES_B, CM_BNS_SCALE_B, mask_sh), \
365	TF_SF(CM0_CM_MEM_PWR_CTRL, RGAM_MEM_PWR_FORCE, mask_sh), \
366	TF_SF(CM0_CM_RGAM_LUT_DATA, CM_RGAM_LUT_DATA, mask_sh), \
367	TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_EN_MASK, mask_sh), \
368	TF_SF(CM0_CM_RGAM_LUT_WRITE_EN_MASK, CM_RGAM_LUT_WRITE_SEL, mask_sh), \
369	TF_SF(CM0_CM_RGAM_LUT_INDEX, CM_RGAM_LUT_INDEX, mask_sh), \
370	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_B, mask_sh), \
371	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_B, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh), \
372	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_G, mask_sh), \
373	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_G, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh), \
374	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_R, mask_sh), \
375	TF_SF(CM0_CM_RGAM_RAMB_START_CNTL_R, CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh), \
376	TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_B, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
377	TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_G, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
378	TF_SF(CM0_CM_RGAM_RAMB_SLOPE_CNTL_R, CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
379	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_B, CM_RGAM_RAMB_EXP_REGION_END_B, mask_sh), \
380	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh), \
381	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_B, CM_RGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh), \
382	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_G, CM_RGAM_RAMB_EXP_REGION_END_G, mask_sh), \
383	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh), \
384	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_G, CM_RGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh), \
385	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL1_R, CM_RGAM_RAMB_EXP_REGION_END_R, mask_sh), \
386	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh), \
387	TF_SF(CM0_CM_RGAM_RAMB_END_CNTL2_R, CM_RGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh), \
388	TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh), \
389	TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
390	TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh), \
391	TF_SF(CM0_CM_RGAM_RAMB_REGION_0_1, CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
392	TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh), \
393	TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
394	TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh), \
395	TF_SF(CM0_CM_RGAM_RAMB_REGION_32_33, CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
396	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_B, mask_sh), \
397	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_B, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh), \
398	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_G, mask_sh), \
399	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_G, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh), \
400	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_R, mask_sh), \
401	TF_SF(CM0_CM_RGAM_RAMA_START_CNTL_R, CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh), \
402	TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_B, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, mask_sh), \
403	TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_G, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, mask_sh), \
404	TF_SF(CM0_CM_RGAM_RAMA_SLOPE_CNTL_R, CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, mask_sh), \
405	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_B, CM_RGAM_RAMA_EXP_REGION_END_B, mask_sh), \
406	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh), \
407	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_B, CM_RGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh), \
408	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_G, CM_RGAM_RAMA_EXP_REGION_END_G, mask_sh), \
409	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh), \
410	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_G, CM_RGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh), \
411	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL1_R, CM_RGAM_RAMA_EXP_REGION_END_R, mask_sh), \
412	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh), \
413	TF_SF(CM0_CM_RGAM_RAMA_END_CNTL2_R, CM_RGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh), \
414	TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh), \
415	TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh), \
416	TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh), \
417	TF_SF(CM0_CM_RGAM_RAMA_REGION_0_1, CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh), \
418	TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh), \
419	TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh), \
420	TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh), \
421	TF_SF(CM0_CM_RGAM_RAMA_REGION_32_33, CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh), \
422	TF_SF(CM0_CM_RGAM_CONTROL, CM_RGAM_LUT_MODE, mask_sh), \
423	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, mask_sh), \
424	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_R, mask_sh), \
425	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_G, mask_sh), \
426	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_LUT_FORMAT_B, mask_sh), \
427	TF_SF(CM0_CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, mask_sh), \
428	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, mask_sh), \
429	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_HOST_EN, mask_sh), \
430	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_RW_MODE, mask_sh), \
431	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_SEL, mask_sh), \
432	TF_SF(CM0_CM_IGAM_LUT_RW_CONTROL, CM_IGAM_LUT_WRITE_EN_MASK, mask_sh), \
433	TF_SF(CM0_CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, mask_sh), \
434	TF_SF(CM0_CM_CONTROL, CM_BYPASS_EN, mask_sh), \
435	TF_SF(CM0_CM_IGAM_LUT_SEQ_COLOR, CM_IGAM_LUT_SEQ_COLOR, mask_sh), \
436	TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \
437	TF_SF(CM0_CM_CMOUT_CONTROL, CM_CMOUT_ROUND_TRUNC_MODE, mask_sh), \
438	TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
439	TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
440	TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
441	TF_SF(CURSOR0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
442	TF_SF(DPP_TOP0_DPP_CONTROL, DPPCLK_RATE_CONTROL, mask_sh)
443
444	/*
445	*
446	DCN1 CM debug status register definition
447
448	register :ID9_CM_STATUS do
449	implement_ref :cm
450	map to: :cmdebugind, at: j
451	width 32
452	disclosure NEVER
453
454	field :ID9_VUPDATE_CFG, [0], R
455	field :ID9_IGAM_LUT_MODE, [2..1], R
456	field :ID9_BNS_BYPASS, [3], R
457	field :ID9_ICSC_MODE, [5..4], R
458	field :ID9_DGAM_LUT_MODE, [8..6], R
459	field :ID9_HDR_BYPASS, [9], R
460	field :ID9_GAMUT_REMAP_MODE, [11..10], R
461	field :ID9_RGAM_LUT_MODE, [14..12], R
462	#1 free bit
463	field :ID9_OCSC_MODE, [18..16], R
464	field :ID9_DENORM_MODE, [21..19], R
465	field :ID9_ROUND_TRUNC_MODE, [25..22], R
466	field :ID9_DITHER_EN, [26], R
467	field :ID9_DITHER_MODE, [28..27], R
468	end
469	*/
470
471	#define TF_DEBUG_REG_LIST_SH_DCN10 \
472	.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 4, \
473	.CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 16
474
475	#define TF_DEBUG_REG_LIST_MASK_DCN10 \
476	.CM_TEST_DEBUG_DATA_ID9_ICSC_MODE = 0x30, \
477	.CM_TEST_DEBUG_DATA_ID9_OCSC_MODE = 0x70000
478
479	#define TF_REG_FIELD_LIST(type) \
480	type EXT_OVERSCAN_LEFT; \
481	type EXT_OVERSCAN_RIGHT; \
482	type EXT_OVERSCAN_BOTTOM; \
483	type EXT_OVERSCAN_TOP; \
484	type OTG_H_BLANK_START; \
485	type OTG_H_BLANK_END; \
486	type OTG_V_BLANK_START; \
487	type OTG_V_BLANK_END; \
488	type PIXEL_DEPTH; \
489	type PIXEL_EXPAN_MODE; \
490	type PIXEL_REDUCE_MODE; \
491	type DYNAMIC_PIXEL_DEPTH; \
492	type DITHER_EN; \
493	type INTERLEAVE_EN; \
494	type LB_DATA_FORMAT__ALPHA_EN; \
495	type MEMORY_CONFIG; \
496	type LB_MAX_PARTITIONS; \
497	type AUTOCAL_MODE; \
498	type AUTOCAL_NUM_PIPE; \
499	type AUTOCAL_PIPE_ID; \
500	type SCL_BOUNDARY_MODE; \
501	type SCL_BLACK_OFFSET_RGB_Y; \
502	type SCL_BLACK_OFFSET_CBCR; \
503	type SCL_V_NUM_TAPS; \
504	type SCL_H_NUM_TAPS; \
505	type SCL_V_NUM_TAPS_C; \
506	type SCL_H_NUM_TAPS_C; \
507	type SCL_COEF_RAM_TAP_PAIR_IDX; \
508	type SCL_COEF_RAM_PHASE; \
509	type SCL_COEF_RAM_FILTER_TYPE; \
510	type SCL_COEF_RAM_EVEN_TAP_COEF; \
511	type SCL_COEF_RAM_EVEN_TAP_COEF_EN; \
512	type SCL_COEF_RAM_ODD_TAP_COEF; \
513	type SCL_COEF_RAM_ODD_TAP_COEF_EN; \
514	type SCL_H_2TAP_HARDCODE_COEF_EN; \
515	type SCL_H_2TAP_SHARP_EN; \
516	type SCL_H_2TAP_SHARP_FACTOR; \
517	type SCL_V_2TAP_HARDCODE_COEF_EN; \
518	type SCL_V_2TAP_SHARP_EN; \
519	type SCL_V_2TAP_SHARP_FACTOR; \
520	type SCL_COEF_RAM_SELECT; \
521	type DSCL_MODE; \
522	type RECOUT_START_X; \
523	type RECOUT_START_Y; \
524	type RECOUT_WIDTH; \
525	type RECOUT_HEIGHT; \
526	type MPC_WIDTH; \
527	type MPC_HEIGHT; \
528	type SCL_H_SCALE_RATIO; \
529	type SCL_V_SCALE_RATIO; \
530	type SCL_H_SCALE_RATIO_C; \
531	type SCL_V_SCALE_RATIO_C; \
532	type SCL_H_INIT_FRAC; \
533	type SCL_H_INIT_INT; \
534	type SCL_H_INIT_FRAC_C; \
535	type SCL_H_INIT_INT_C; \
536	type SCL_V_INIT_FRAC; \
537	type SCL_V_INIT_INT; \
538	type SCL_V_INIT_FRAC_BOT; \
539	type SCL_V_INIT_INT_BOT; \
540	type SCL_V_INIT_FRAC_C; \
541	type SCL_V_INIT_INT_C; \
542	type SCL_V_INIT_FRAC_BOT_C; \
543	type SCL_V_INIT_INT_BOT_C; \
544	type SCL_CHROMA_COEF_MODE; \
545	type SCL_COEF_RAM_SELECT_CURRENT; \
546	type LUT_MEM_PWR_FORCE; \
547	type LUT_MEM_PWR_STATE; \
548	type CM_GAMUT_REMAP_MODE; \
549	type CM_GAMUT_REMAP_C11; \
550	type CM_GAMUT_REMAP_C12; \
551	type CM_GAMUT_REMAP_C13; \
552	type CM_GAMUT_REMAP_C14; \
553	type CM_GAMUT_REMAP_C21; \
554	type CM_GAMUT_REMAP_C22; \
555	type CM_GAMUT_REMAP_C23; \
556	type CM_GAMUT_REMAP_C24; \
557	type CM_GAMUT_REMAP_C31; \
558	type CM_GAMUT_REMAP_C32; \
559	type CM_GAMUT_REMAP_C33; \
560	type CM_GAMUT_REMAP_C34; \
561	type CM_COMA_C11; \
562	type CM_COMA_C12; \
563	type CM_COMA_C33; \
564	type CM_COMA_C34; \
565	type CM_COMB_C11; \
566	type CM_COMB_C12; \
567	type CM_COMB_C33; \
568	type CM_COMB_C34; \
569	type CM_OCSC_MODE; \
570	type CM_OCSC_C11; \
571	type CM_OCSC_C12; \
572	type CM_OCSC_C33; \
573	type CM_OCSC_C34; \
574	type RGAM_MEM_PWR_FORCE; \
575	type CM_RGAM_LUT_DATA; \
576	type CM_RGAM_LUT_WRITE_EN_MASK; \
577	type CM_RGAM_LUT_WRITE_SEL; \
578	type CM_RGAM_LUT_INDEX; \
579	type CM_RGAM_RAMB_EXP_REGION_START_B; \
580	type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
581	type CM_RGAM_RAMB_EXP_REGION_START_G; \
582	type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
583	type CM_RGAM_RAMB_EXP_REGION_START_R; \
584	type CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
585	type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
586	type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
587	type CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
588	type CM_RGAM_RAMB_EXP_REGION_END_B; \
589	type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; \
590	type CM_RGAM_RAMB_EXP_REGION_END_BASE_B; \
591	type CM_RGAM_RAMB_EXP_REGION_END_G; \
592	type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G; \
593	type CM_RGAM_RAMB_EXP_REGION_END_BASE_G; \
594	type CM_RGAM_RAMB_EXP_REGION_END_R; \
595	type CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R; \
596	type CM_RGAM_RAMB_EXP_REGION_END_BASE_R; \
597	type CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
598	type CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
599	type CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
600	type CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
601	type CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
602	type CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
603	type CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
604	type CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
605	type CM_RGAM_RAMA_EXP_REGION_START_B; \
606	type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
607	type CM_RGAM_RAMA_EXP_REGION_START_G; \
608	type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
609	type CM_RGAM_RAMA_EXP_REGION_START_R; \
610	type CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
611	type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
612	type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
613	type CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
614	type CM_RGAM_RAMA_EXP_REGION_END_B; \
615	type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B; \
616	type CM_RGAM_RAMA_EXP_REGION_END_BASE_B; \
617	type CM_RGAM_RAMA_EXP_REGION_END_G; \
618	type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G; \
619	type CM_RGAM_RAMA_EXP_REGION_END_BASE_G; \
620	type CM_RGAM_RAMA_EXP_REGION_END_R; \
621	type CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R; \
622	type CM_RGAM_RAMA_EXP_REGION_END_BASE_R; \
623	type CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
624	type CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
625	type CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
626	type CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
627	type CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
628	type CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
629	type CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
630	type CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
631	type CM_RGAM_LUT_MODE; \
632	type CM_CMOUT_ROUND_TRUNC_MODE; \
633	type CM_BLNDGAM_LUT_MODE; \
634	type CM_BLNDGAM_RAMB_EXP_REGION_START_B; \
635	type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
636	type CM_BLNDGAM_RAMB_EXP_REGION_START_G; \
637	type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
638	type CM_BLNDGAM_RAMB_EXP_REGION_START_R; \
639	type CM_BLNDGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
640	type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
641	type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
642	type CM_BLNDGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
643	type CM_BLNDGAM_RAMB_EXP_REGION_END_B; \
644	type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_B; \
645	type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_B; \
646	type CM_BLNDGAM_RAMB_EXP_REGION_END_G; \
647	type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_G; \
648	type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_G; \
649	type CM_BLNDGAM_RAMB_EXP_REGION_END_R; \
650	type CM_BLNDGAM_RAMB_EXP_REGION_END_SLOPE_R; \
651	type CM_BLNDGAM_RAMB_EXP_REGION_END_BASE_R; \
652	type CM_BLNDGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
653	type CM_BLNDGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
654	type CM_BLNDGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
655	type CM_BLNDGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
656	type CM_BLNDGAM_RAMB_EXP_REGION2_LUT_OFFSET; \
657	type CM_BLNDGAM_RAMB_EXP_REGION2_NUM_SEGMENTS; \
658	type CM_BLNDGAM_RAMB_EXP_REGION3_LUT_OFFSET; \
659	type CM_BLNDGAM_RAMB_EXP_REGION3_NUM_SEGMENTS; \
660	type CM_BLNDGAM_RAMB_EXP_REGION4_LUT_OFFSET; \
661	type CM_BLNDGAM_RAMB_EXP_REGION4_NUM_SEGMENTS; \
662	type CM_BLNDGAM_RAMB_EXP_REGION5_LUT_OFFSET; \
663	type CM_BLNDGAM_RAMB_EXP_REGION5_NUM_SEGMENTS; \
664	type CM_BLNDGAM_RAMB_EXP_REGION6_LUT_OFFSET; \
665	type CM_BLNDGAM_RAMB_EXP_REGION6_NUM_SEGMENTS; \
666	type CM_BLNDGAM_RAMB_EXP_REGION7_LUT_OFFSET; \
667	type CM_BLNDGAM_RAMB_EXP_REGION7_NUM_SEGMENTS; \
668	type CM_BLNDGAM_RAMB_EXP_REGION8_LUT_OFFSET; \
669	type CM_BLNDGAM_RAMB_EXP_REGION8_NUM_SEGMENTS; \
670	type CM_BLNDGAM_RAMB_EXP_REGION9_LUT_OFFSET; \
671	type CM_BLNDGAM_RAMB_EXP_REGION9_NUM_SEGMENTS; \
672	type CM_BLNDGAM_RAMB_EXP_REGION10_LUT_OFFSET; \
673	type CM_BLNDGAM_RAMB_EXP_REGION10_NUM_SEGMENTS; \
674	type CM_BLNDGAM_RAMB_EXP_REGION11_LUT_OFFSET; \
675	type CM_BLNDGAM_RAMB_EXP_REGION11_NUM_SEGMENTS; \
676	type CM_BLNDGAM_RAMB_EXP_REGION12_LUT_OFFSET; \
677	type CM_BLNDGAM_RAMB_EXP_REGION12_NUM_SEGMENTS; \
678	type CM_BLNDGAM_RAMB_EXP_REGION13_LUT_OFFSET; \
679	type CM_BLNDGAM_RAMB_EXP_REGION13_NUM_SEGMENTS; \
680	type CM_BLNDGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
681	type CM_BLNDGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
682	type CM_BLNDGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
683	type CM_BLNDGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
684	type CM_BLNDGAM_RAMB_EXP_REGION16_LUT_OFFSET; \
685	type CM_BLNDGAM_RAMB_EXP_REGION16_NUM_SEGMENTS; \
686	type CM_BLNDGAM_RAMB_EXP_REGION17_LUT_OFFSET; \
687	type CM_BLNDGAM_RAMB_EXP_REGION17_NUM_SEGMENTS; \
688	type CM_BLNDGAM_RAMB_EXP_REGION18_LUT_OFFSET; \
689	type CM_BLNDGAM_RAMB_EXP_REGION18_NUM_SEGMENTS; \
690	type CM_BLNDGAM_RAMB_EXP_REGION19_LUT_OFFSET; \
691	type CM_BLNDGAM_RAMB_EXP_REGION19_NUM_SEGMENTS; \
692	type CM_BLNDGAM_RAMB_EXP_REGION20_LUT_OFFSET; \
693	type CM_BLNDGAM_RAMB_EXP_REGION20_NUM_SEGMENTS; \
694	type CM_BLNDGAM_RAMB_EXP_REGION21_LUT_OFFSET; \
695	type CM_BLNDGAM_RAMB_EXP_REGION21_NUM_SEGMENTS; \
696	type CM_BLNDGAM_RAMB_EXP_REGION22_LUT_OFFSET; \
697	type CM_BLNDGAM_RAMB_EXP_REGION22_NUM_SEGMENTS; \
698	type CM_BLNDGAM_RAMB_EXP_REGION23_LUT_OFFSET; \
699	type CM_BLNDGAM_RAMB_EXP_REGION23_NUM_SEGMENTS; \
700	type CM_BLNDGAM_RAMB_EXP_REGION24_LUT_OFFSET; \
701	type CM_BLNDGAM_RAMB_EXP_REGION24_NUM_SEGMENTS; \
702	type CM_BLNDGAM_RAMB_EXP_REGION25_LUT_OFFSET; \
703	type CM_BLNDGAM_RAMB_EXP_REGION25_NUM_SEGMENTS; \
704	type CM_BLNDGAM_RAMB_EXP_REGION26_LUT_OFFSET; \
705	type CM_BLNDGAM_RAMB_EXP_REGION26_NUM_SEGMENTS; \
706	type CM_BLNDGAM_RAMB_EXP_REGION27_LUT_OFFSET; \
707	type CM_BLNDGAM_RAMB_EXP_REGION27_NUM_SEGMENTS; \
708	type CM_BLNDGAM_RAMB_EXP_REGION28_LUT_OFFSET; \
709	type CM_BLNDGAM_RAMB_EXP_REGION28_NUM_SEGMENTS; \
710	type CM_BLNDGAM_RAMB_EXP_REGION29_LUT_OFFSET; \
711	type CM_BLNDGAM_RAMB_EXP_REGION29_NUM_SEGMENTS; \
712	type CM_BLNDGAM_RAMB_EXP_REGION30_LUT_OFFSET; \
713	type CM_BLNDGAM_RAMB_EXP_REGION30_NUM_SEGMENTS; \
714	type CM_BLNDGAM_RAMB_EXP_REGION31_LUT_OFFSET; \
715	type CM_BLNDGAM_RAMB_EXP_REGION31_NUM_SEGMENTS; \
716	type CM_BLNDGAM_RAMB_EXP_REGION32_LUT_OFFSET; \
717	type CM_BLNDGAM_RAMB_EXP_REGION32_NUM_SEGMENTS; \
718	type CM_BLNDGAM_RAMB_EXP_REGION33_LUT_OFFSET; \
719	type CM_BLNDGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; \
720	type CM_BLNDGAM_RAMA_EXP_REGION_START_B; \
721	type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
722	type CM_BLNDGAM_RAMA_EXP_REGION_START_G; \
723	type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
724	type CM_BLNDGAM_RAMA_EXP_REGION_START_R; \
725	type CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
726	type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
727	type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
728	type CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
729	type CM_BLNDGAM_RAMA_EXP_REGION_END_B; \
730	type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; \
731	type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; \
732	type CM_BLNDGAM_RAMA_EXP_REGION_END_G; \
733	type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_G; \
734	type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_G; \
735	type CM_BLNDGAM_RAMA_EXP_REGION_END_R; \
736	type CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_R; \
737	type CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_R; \
738	type CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
739	type CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
740	type CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
741	type CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
742	type CM_BLNDGAM_RAMA_EXP_REGION2_LUT_OFFSET; \
743	type CM_BLNDGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \
744	type CM_BLNDGAM_RAMA_EXP_REGION3_LUT_OFFSET; \
745	type CM_BLNDGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \
746	type CM_BLNDGAM_RAMA_EXP_REGION4_LUT_OFFSET; \
747	type CM_BLNDGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \
748	type CM_BLNDGAM_RAMA_EXP_REGION5_LUT_OFFSET; \
749	type CM_BLNDGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \
750	type CM_BLNDGAM_RAMA_EXP_REGION6_LUT_OFFSET; \
751	type CM_BLNDGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \
752	type CM_BLNDGAM_RAMA_EXP_REGION7_LUT_OFFSET; \
753	type CM_BLNDGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \
754	type CM_BLNDGAM_RAMA_EXP_REGION8_LUT_OFFSET; \
755	type CM_BLNDGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \
756	type CM_BLNDGAM_RAMA_EXP_REGION9_LUT_OFFSET; \
757	type CM_BLNDGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \
758	type CM_BLNDGAM_RAMA_EXP_REGION10_LUT_OFFSET; \
759	type CM_BLNDGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \
760	type CM_BLNDGAM_RAMA_EXP_REGION11_LUT_OFFSET; \
761	type CM_BLNDGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \
762	type CM_BLNDGAM_RAMA_EXP_REGION12_LUT_OFFSET; \
763	type CM_BLNDGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \
764	type CM_BLNDGAM_RAMA_EXP_REGION13_LUT_OFFSET; \
765	type CM_BLNDGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \
766	type CM_BLNDGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
767	type CM_BLNDGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
768	type CM_BLNDGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
769	type CM_BLNDGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
770	type CM_BLNDGAM_RAMA_EXP_REGION16_LUT_OFFSET; \
771	type CM_BLNDGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \
772	type CM_BLNDGAM_RAMA_EXP_REGION17_LUT_OFFSET; \
773	type CM_BLNDGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \
774	type CM_BLNDGAM_RAMA_EXP_REGION18_LUT_OFFSET; \
775	type CM_BLNDGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \
776	type CM_BLNDGAM_RAMA_EXP_REGION19_LUT_OFFSET; \
777	type CM_BLNDGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \
778	type CM_BLNDGAM_RAMA_EXP_REGION20_LUT_OFFSET; \
779	type CM_BLNDGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \
780	type CM_BLNDGAM_RAMA_EXP_REGION21_LUT_OFFSET; \
781	type CM_BLNDGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \
782	type CM_BLNDGAM_RAMA_EXP_REGION22_LUT_OFFSET; \
783	type CM_BLNDGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \
784	type CM_BLNDGAM_RAMA_EXP_REGION23_LUT_OFFSET; \
785	type CM_BLNDGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \
786	type CM_BLNDGAM_RAMA_EXP_REGION24_LUT_OFFSET; \
787	type CM_BLNDGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \
788	type CM_BLNDGAM_RAMA_EXP_REGION25_LUT_OFFSET; \
789	type CM_BLNDGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \
790	type CM_BLNDGAM_RAMA_EXP_REGION26_LUT_OFFSET; \
791	type CM_BLNDGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \
792	type CM_BLNDGAM_RAMA_EXP_REGION27_LUT_OFFSET; \
793	type CM_BLNDGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \
794	type CM_BLNDGAM_RAMA_EXP_REGION28_LUT_OFFSET; \
795	type CM_BLNDGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \
796	type CM_BLNDGAM_RAMA_EXP_REGION29_LUT_OFFSET; \
797	type CM_BLNDGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \
798	type CM_BLNDGAM_RAMA_EXP_REGION30_LUT_OFFSET; \
799	type CM_BLNDGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \
800	type CM_BLNDGAM_RAMA_EXP_REGION31_LUT_OFFSET; \
801	type CM_BLNDGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \
802	type CM_BLNDGAM_RAMA_EXP_REGION32_LUT_OFFSET; \
803	type CM_BLNDGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \
804	type CM_BLNDGAM_RAMA_EXP_REGION33_LUT_OFFSET; \
805	type CM_BLNDGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \
806	type CM_BLNDGAM_LUT_WRITE_EN_MASK; \
807	type CM_BLNDGAM_LUT_WRITE_SEL; \
808	type CM_BLNDGAM_CONFIG_STATUS; \
809	type CM_BLNDGAM_LUT_INDEX; \
810	type BLNDGAM_MEM_PWR_FORCE; \
811	type CM_3DLUT_MODE; \
812	type CM_3DLUT_SIZE; \
813	type CM_3DLUT_INDEX; \
814	type CM_3DLUT_DATA0; \
815	type CM_3DLUT_DATA1; \
816	type CM_3DLUT_DATA_30BIT; \
817	type CM_3DLUT_WRITE_EN_MASK; \
818	type CM_3DLUT_RAM_SEL; \
819	type CM_3DLUT_30BIT_EN; \
820	type CM_3DLUT_CONFIG_STATUS; \
821	type CM_3DLUT_READ_SEL; \
822	type CM_SHAPER_LUT_MODE; \
823	type CM_SHAPER_RAMB_EXP_REGION_START_B; \
824	type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_B; \
825	type CM_SHAPER_RAMB_EXP_REGION_START_G; \
826	type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_G; \
827	type CM_SHAPER_RAMB_EXP_REGION_START_R; \
828	type CM_SHAPER_RAMB_EXP_REGION_START_SEGMENT_R; \
829	type CM_SHAPER_RAMB_EXP_REGION_END_B; \
830	type CM_SHAPER_RAMB_EXP_REGION_END_BASE_B; \
831	type CM_SHAPER_RAMB_EXP_REGION_END_G; \
832	type CM_SHAPER_RAMB_EXP_REGION_END_BASE_G; \
833	type CM_SHAPER_RAMB_EXP_REGION_END_R; \
834	type CM_SHAPER_RAMB_EXP_REGION_END_BASE_R; \
835	type CM_SHAPER_RAMB_EXP_REGION0_LUT_OFFSET; \
836	type CM_SHAPER_RAMB_EXP_REGION0_NUM_SEGMENTS; \
837	type CM_SHAPER_RAMB_EXP_REGION1_LUT_OFFSET; \
838	type CM_SHAPER_RAMB_EXP_REGION1_NUM_SEGMENTS; \
839	type CM_SHAPER_RAMB_EXP_REGION2_LUT_OFFSET; \
840	type CM_SHAPER_RAMB_EXP_REGION2_NUM_SEGMENTS; \
841	type CM_SHAPER_RAMB_EXP_REGION3_LUT_OFFSET; \
842	type CM_SHAPER_RAMB_EXP_REGION3_NUM_SEGMENTS; \
843	type CM_SHAPER_RAMB_EXP_REGION4_LUT_OFFSET; \
844	type CM_SHAPER_RAMB_EXP_REGION4_NUM_SEGMENTS; \
845	type CM_SHAPER_RAMB_EXP_REGION5_LUT_OFFSET; \
846	type CM_SHAPER_RAMB_EXP_REGION5_NUM_SEGMENTS; \
847	type CM_SHAPER_RAMB_EXP_REGION6_LUT_OFFSET; \
848	type CM_SHAPER_RAMB_EXP_REGION6_NUM_SEGMENTS; \
849	type CM_SHAPER_RAMB_EXP_REGION7_LUT_OFFSET; \
850	type CM_SHAPER_RAMB_EXP_REGION7_NUM_SEGMENTS; \
851	type CM_SHAPER_RAMB_EXP_REGION8_LUT_OFFSET; \
852	type CM_SHAPER_RAMB_EXP_REGION8_NUM_SEGMENTS; \
853	type CM_SHAPER_RAMB_EXP_REGION9_LUT_OFFSET; \
854	type CM_SHAPER_RAMB_EXP_REGION9_NUM_SEGMENTS; \
855	type CM_SHAPER_RAMB_EXP_REGION10_LUT_OFFSET; \
856	type CM_SHAPER_RAMB_EXP_REGION10_NUM_SEGMENTS; \
857	type CM_SHAPER_RAMB_EXP_REGION11_LUT_OFFSET; \
858	type CM_SHAPER_RAMB_EXP_REGION11_NUM_SEGMENTS; \
859	type CM_SHAPER_RAMB_EXP_REGION12_LUT_OFFSET; \
860	type CM_SHAPER_RAMB_EXP_REGION12_NUM_SEGMENTS; \
861	type CM_SHAPER_RAMB_EXP_REGION13_LUT_OFFSET; \
862	type CM_SHAPER_RAMB_EXP_REGION13_NUM_SEGMENTS; \
863	type CM_SHAPER_RAMB_EXP_REGION14_LUT_OFFSET; \
864	type CM_SHAPER_RAMB_EXP_REGION14_NUM_SEGMENTS; \
865	type CM_SHAPER_RAMB_EXP_REGION15_LUT_OFFSET; \
866	type CM_SHAPER_RAMB_EXP_REGION15_NUM_SEGMENTS; \
867	type CM_SHAPER_RAMB_EXP_REGION16_LUT_OFFSET; \
868	type CM_SHAPER_RAMB_EXP_REGION16_NUM_SEGMENTS; \
869	type CM_SHAPER_RAMB_EXP_REGION17_LUT_OFFSET; \
870	type CM_SHAPER_RAMB_EXP_REGION17_NUM_SEGMENTS; \
871	type CM_SHAPER_RAMB_EXP_REGION18_LUT_OFFSET; \
872	type CM_SHAPER_RAMB_EXP_REGION18_NUM_SEGMENTS; \
873	type CM_SHAPER_RAMB_EXP_REGION19_LUT_OFFSET; \
874	type CM_SHAPER_RAMB_EXP_REGION19_NUM_SEGMENTS; \
875	type CM_SHAPER_RAMB_EXP_REGION20_LUT_OFFSET; \
876	type CM_SHAPER_RAMB_EXP_REGION20_NUM_SEGMENTS; \
877	type CM_SHAPER_RAMB_EXP_REGION21_LUT_OFFSET; \
878	type CM_SHAPER_RAMB_EXP_REGION21_NUM_SEGMENTS; \
879	type CM_SHAPER_RAMB_EXP_REGION22_LUT_OFFSET; \
880	type CM_SHAPER_RAMB_EXP_REGION22_NUM_SEGMENTS; \
881	type CM_SHAPER_RAMB_EXP_REGION23_LUT_OFFSET; \
882	type CM_SHAPER_RAMB_EXP_REGION23_NUM_SEGMENTS; \
883	type CM_SHAPER_RAMB_EXP_REGION24_LUT_OFFSET; \
884	type CM_SHAPER_RAMB_EXP_REGION24_NUM_SEGMENTS; \
885	type CM_SHAPER_RAMB_EXP_REGION25_LUT_OFFSET; \
886	type CM_SHAPER_RAMB_EXP_REGION25_NUM_SEGMENTS; \
887	type CM_SHAPER_RAMB_EXP_REGION26_LUT_OFFSET; \
888	type CM_SHAPER_RAMB_EXP_REGION26_NUM_SEGMENTS; \
889	type CM_SHAPER_RAMB_EXP_REGION27_LUT_OFFSET; \
890	type CM_SHAPER_RAMB_EXP_REGION27_NUM_SEGMENTS; \
891	type CM_SHAPER_RAMB_EXP_REGION28_LUT_OFFSET; \
892	type CM_SHAPER_RAMB_EXP_REGION28_NUM_SEGMENTS; \
893	type CM_SHAPER_RAMB_EXP_REGION29_LUT_OFFSET; \
894	type CM_SHAPER_RAMB_EXP_REGION29_NUM_SEGMENTS; \
895	type CM_SHAPER_RAMB_EXP_REGION30_LUT_OFFSET; \
896	type CM_SHAPER_RAMB_EXP_REGION30_NUM_SEGMENTS; \
897	type CM_SHAPER_RAMB_EXP_REGION31_LUT_OFFSET; \
898	type CM_SHAPER_RAMB_EXP_REGION31_NUM_SEGMENTS; \
899	type CM_SHAPER_RAMB_EXP_REGION32_LUT_OFFSET; \
900	type CM_SHAPER_RAMB_EXP_REGION32_NUM_SEGMENTS; \
901	type CM_SHAPER_RAMB_EXP_REGION33_LUT_OFFSET; \
902	type CM_SHAPER_RAMB_EXP_REGION33_NUM_SEGMENTS; \
903	type CM_SHAPER_RAMA_EXP_REGION_START_B; \
904	type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \
905	type CM_SHAPER_RAMA_EXP_REGION_START_G; \
906	type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G; \
907	type CM_SHAPER_RAMA_EXP_REGION_START_R; \
908	type CM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R; \
909	type CM_SHAPER_RAMA_EXP_REGION_END_B; \
910	type CM_SHAPER_RAMA_EXP_REGION_END_BASE_B; \
911	type CM_SHAPER_RAMA_EXP_REGION_END_G; \
912	type CM_SHAPER_RAMA_EXP_REGION_END_BASE_G; \
913	type CM_SHAPER_RAMA_EXP_REGION_END_R; \
914	type CM_SHAPER_RAMA_EXP_REGION_END_BASE_R; \
915	type CM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET; \
916	type CM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS; \
917	type CM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \
918	type CM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \
919	type CM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \
920	type CM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \
921	type CM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET; \
922	type CM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS; \
923	type CM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET; \
924	type CM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS; \
925	type CM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET; \
926	type CM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS; \
927	type CM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \
928	type CM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \
929	type CM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \
930	type CM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \
931	type CM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET; \
932	type CM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS; \
933	type CM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET; \
934	type CM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS; \
935	type CM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET; \
936	type CM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS; \
937	type CM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \
938	type CM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \
939	type CM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \
940	type CM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \
941	type CM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET; \
942	type CM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS; \
943	type CM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET; \
944	type CM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS; \
945	type CM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET; \
946	type CM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS; \
947	type CM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \
948	type CM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \
949	type CM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \
950	type CM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \
951	type CM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET; \
952	type CM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS; \
953	type CM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET; \
954	type CM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS; \
955	type CM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET; \
956	type CM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS; \
957	type CM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \
958	type CM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \
959	type CM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \
960	type CM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \
961	type CM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET; \
962	type CM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS; \
963	type CM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET; \
964	type CM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS; \
965	type CM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET; \
966	type CM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS; \
967	type CM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \
968	type CM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \
969	type CM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \
970	type CM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \
971	type CM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET; \
972	type CM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS; \
973	type CM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET; \
974	type CM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS; \
975	type CM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET; \
976	type CM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS; \
977	type CM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \
978	type CM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \
979	type CM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \
980	type CM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \
981	type CM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET; \
982	type CM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS; \
983	type CM_SHAPER_LUT_WRITE_EN_MASK; \
984	type CM_SHAPER_CONFIG_STATUS; \
985	type CM_SHAPER_LUT_WRITE_SEL; \
986	type CM_SHAPER_LUT_INDEX; \
987	type CM_SHAPER_LUT_DATA; \
988	type CM_DGAM_CONFIG_STATUS; \
989	type CM_ICSC_MODE; \
990	type CM_ICSC_C11; \
991	type CM_ICSC_C12; \
992	type CM_ICSC_C33; \
993	type CM_ICSC_C34; \
994	type CM_BNS_BIAS_R; \
995	type CM_BNS_BIAS_G; \
996	type CM_BNS_BIAS_B; \
997	type CM_BNS_SCALE_R; \
998	type CM_BNS_SCALE_G; \
999	type CM_BNS_SCALE_B; \
1000	type CM_DGAM_RAMB_EXP_REGION_START_B; \
1001	type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B; \
1002	type CM_DGAM_RAMB_EXP_REGION_START_G; \
1003	type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_G; \
1004	type CM_DGAM_RAMB_EXP_REGION_START_R; \
1005	type CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_R; \
1006	type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B; \
1007	type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G; \
1008	type CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R; \
1009	type CM_DGAM_RAMB_EXP_REGION_END_B; \
1010	type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B; \
1011	type CM_DGAM_RAMB_EXP_REGION_END_BASE_B; \
1012	type CM_DGAM_RAMB_EXP_REGION_END_G; \
1013	type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_G; \
1014	type CM_DGAM_RAMB_EXP_REGION_END_BASE_G; \
1015	type CM_DGAM_RAMB_EXP_REGION_END_R; \
1016	type CM_DGAM_RAMB_EXP_REGION_END_SLOPE_R; \
1017	type CM_DGAM_RAMB_EXP_REGION_END_BASE_R; \
1018	type CM_DGAM_RAMB_EXP_REGION0_LUT_OFFSET; \
1019	type CM_DGAM_RAMB_EXP_REGION0_NUM_SEGMENTS; \
1020	type CM_DGAM_RAMB_EXP_REGION1_LUT_OFFSET; \
1021	type CM_DGAM_RAMB_EXP_REGION1_NUM_SEGMENTS; \
1022	type CM_DGAM_RAMB_EXP_REGION14_LUT_OFFSET; \
1023	type CM_DGAM_RAMB_EXP_REGION14_NUM_SEGMENTS; \
1024	type CM_DGAM_RAMB_EXP_REGION15_LUT_OFFSET; \
1025	type CM_DGAM_RAMB_EXP_REGION15_NUM_SEGMENTS; \
1026	type CM_DGAM_RAMA_EXP_REGION_START_B; \
1027	type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_B; \
1028	type CM_DGAM_RAMA_EXP_REGION_START_G; \
1029	type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_G; \
1030	type CM_DGAM_RAMA_EXP_REGION_START_R; \
1031	type CM_DGAM_RAMA_EXP_REGION_START_SEGMENT_R; \
1032	type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; \
1033	type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G; \
1034	type CM_DGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R; \
1035	type CM_DGAM_RAMA_EXP_REGION_END_B; \
1036	type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_B; \
1037	type CM_DGAM_RAMA_EXP_REGION_END_BASE_B; \
1038	type CM_DGAM_RAMA_EXP_REGION_END_G; \
1039	type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_G; \
1040	type CM_DGAM_RAMA_EXP_REGION_END_BASE_G; \
1041	type CM_DGAM_RAMA_EXP_REGION_END_R; \
1042	type CM_DGAM_RAMA_EXP_REGION_END_SLOPE_R; \
1043	type CM_DGAM_RAMA_EXP_REGION_END_BASE_R; \
1044	type CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET; \
1045	type CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \
1046	type CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET; \
1047	type CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \
1048	type CM_DGAM_RAMA_EXP_REGION14_LUT_OFFSET; \
1049	type CM_DGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \
1050	type CM_DGAM_RAMA_EXP_REGION15_LUT_OFFSET; \
1051	type CM_DGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \
1052	type SHARED_MEM_PWR_DIS; \
1053	type CM_IGAM_LUT_FORMAT_R; \
1054	type CM_IGAM_LUT_FORMAT_G; \
1055	type CM_IGAM_LUT_FORMAT_B; \
1056	type CM_IGAM_LUT_HOST_EN; \
1057	type CM_IGAM_LUT_RW_MODE; \
1058	type CM_IGAM_LUT_WRITE_EN_MASK; \
1059	type CM_IGAM_LUT_SEL; \
1060	type CM_IGAM_LUT_SEQ_COLOR; \
1061	type CM_IGAM_DGAM_CONFIG_STATUS; \
1062	type CM_DGAM_LUT_WRITE_EN_MASK; \
1063	type CM_DGAM_LUT_WRITE_SEL; \
1064	type CM_DGAM_LUT_INDEX; \
1065	type CM_DGAM_LUT_DATA; \
1066	type CM_DGAM_LUT_MODE; \
1067	type CM_IGAM_LUT_MODE; \
1068	type CM_IGAM_INPUT_FORMAT; \
1069	type CM_IGAM_LUT_RW_INDEX; \
1070	type CM_BYPASS_EN; \
1071	type FORMAT_EXPANSION_MODE; \
1072	type CNVC_BYPASS; \
1073	type OUTPUT_FP; \
1074	type CNVC_SURFACE_PIXEL_FORMAT; \
1075	type CURSOR_MODE; \
1076	type CURSOR_PITCH; \
1077	type CURSOR_LINES_PER_CHUNK; \
1078	type CURSOR_ENABLE; \
1079	type CUR0_MODE; \
1080	type CUR0_EXPANSION_MODE; \
1081	type CUR0_ENABLE; \
1082	type CM_BYPASS; \
1083	type CM_TEST_DEBUG_INDEX; \
1084	type CM_TEST_DEBUG_DATA_ID9_ICSC_MODE; \
1085	type CM_TEST_DEBUG_DATA_ID9_OCSC_MODE;\
1086	type FORMAT_CONTROL__ALPHA_EN; \
1087	type CUR0_COLOR0; \
1088	type CUR0_COLOR1; \
1089	type DPPCLK_RATE_CONTROL; \
1090	type DPP_CLOCK_ENABLE; \
1091	type CM_HDR_MULT_COEF; \
1092	type CUR0_FP_BIAS; \
1093	type CUR0_FP_SCALE;
1094
1095	struct dcn_dpp_shift {
1096	TF_REG_FIELD_LIST(uint8_t)
1097	};
1098
1099	struct dcn_dpp_mask {
1100	TF_REG_FIELD_LIST(uint32_t)
1101	};
1102
1103	#define DPP_COMMON_REG_VARIABLE_LIST \
1104	uint32_t DSCL_EXT_OVERSCAN_LEFT_RIGHT; \
1105	uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \
1106	uint32_t OTG_H_BLANK; \
1107	uint32_t OTG_V_BLANK; \
1108	uint32_t DSCL_MEM_PWR_CTRL; \
1109	uint32_t DSCL_MEM_PWR_STATUS; \
1110	uint32_t SCL_MODE; \
1111	uint32_t LB_DATA_FORMAT; \
1112	uint32_t LB_MEMORY_CTRL; \
1113	uint32_t DSCL_AUTOCAL; \
1114	uint32_t DSCL_CONTROL; \
1115	uint32_t SCL_BLACK_OFFSET; \
1116	uint32_t SCL_TAP_CONTROL; \
1117	uint32_t SCL_COEF_RAM_TAP_SELECT; \
1118	uint32_t SCL_COEF_RAM_TAP_DATA; \
1119	uint32_t DSCL_2TAP_CONTROL; \
1120	uint32_t MPC_SIZE; \
1121	uint32_t SCL_HORZ_FILTER_SCALE_RATIO; \
1122	uint32_t SCL_VERT_FILTER_SCALE_RATIO; \
1123	uint32_t SCL_HORZ_FILTER_SCALE_RATIO_C; \
1124	uint32_t SCL_VERT_FILTER_SCALE_RATIO_C; \
1125	uint32_t SCL_HORZ_FILTER_INIT; \
1126	uint32_t SCL_HORZ_FILTER_INIT_C; \
1127	uint32_t SCL_VERT_FILTER_INIT; \
1128	uint32_t SCL_VERT_FILTER_INIT_BOT; \
1129	uint32_t SCL_VERT_FILTER_INIT_C; \
1130	uint32_t SCL_VERT_FILTER_INIT_BOT_C; \
1131	uint32_t RECOUT_START; \
1132	uint32_t RECOUT_SIZE; \
1133	uint32_t CM_GAMUT_REMAP_CONTROL; \
1134	uint32_t CM_GAMUT_REMAP_C11_C12; \
1135	uint32_t CM_GAMUT_REMAP_C13_C14; \
1136	uint32_t CM_GAMUT_REMAP_C21_C22; \
1137	uint32_t CM_GAMUT_REMAP_C23_C24; \
1138	uint32_t CM_GAMUT_REMAP_C31_C32; \
1139	uint32_t CM_GAMUT_REMAP_C33_C34; \
1140	uint32_t CM_COMA_C11_C12; \
1141	uint32_t CM_COMA_C33_C34; \
1142	uint32_t CM_COMB_C11_C12; \
1143	uint32_t CM_COMB_C33_C34; \
1144	uint32_t CM_OCSC_CONTROL; \
1145	uint32_t CM_OCSC_C11_C12; \
1146	uint32_t CM_OCSC_C33_C34; \
1147	uint32_t CM_MEM_PWR_CTRL; \
1148	uint32_t CM_RGAM_LUT_DATA; \
1149	uint32_t CM_RGAM_LUT_WRITE_EN_MASK; \
1150	uint32_t CM_RGAM_LUT_INDEX; \
1151	uint32_t CM_RGAM_RAMB_START_CNTL_B; \
1152	uint32_t CM_RGAM_RAMB_START_CNTL_G; \
1153	uint32_t CM_RGAM_RAMB_START_CNTL_R; \
1154	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_B; \
1155	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_G; \
1156	uint32_t CM_RGAM_RAMB_SLOPE_CNTL_R; \
1157	uint32_t CM_RGAM_RAMB_END_CNTL1_B; \
1158	uint32_t CM_RGAM_RAMB_END_CNTL2_B; \
1159	uint32_t CM_RGAM_RAMB_END_CNTL1_G; \
1160	uint32_t CM_RGAM_RAMB_END_CNTL2_G; \
1161	uint32_t CM_RGAM_RAMB_END_CNTL1_R; \
1162	uint32_t CM_RGAM_RAMB_END_CNTL2_R; \
1163	uint32_t CM_RGAM_RAMB_REGION_0_1; \
1164	uint32_t CM_RGAM_RAMB_REGION_32_33; \
1165	uint32_t CM_RGAM_RAMA_START_CNTL_B; \
1166	uint32_t CM_RGAM_RAMA_START_CNTL_G; \
1167	uint32_t CM_RGAM_RAMA_START_CNTL_R; \
1168	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_B; \
1169	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_G; \
1170	uint32_t CM_RGAM_RAMA_SLOPE_CNTL_R; \
1171	uint32_t CM_RGAM_RAMA_END_CNTL1_B; \
1172	uint32_t CM_RGAM_RAMA_END_CNTL2_B; \
1173	uint32_t CM_RGAM_RAMA_END_CNTL1_G; \
1174	uint32_t CM_RGAM_RAMA_END_CNTL2_G; \
1175	uint32_t CM_RGAM_RAMA_END_CNTL1_R; \
1176	uint32_t CM_RGAM_RAMA_END_CNTL2_R; \
1177	uint32_t CM_RGAM_RAMA_REGION_0_1; \
1178	uint32_t CM_RGAM_RAMA_REGION_32_33; \
1179	uint32_t CM_RGAM_CONTROL; \
1180	uint32_t CM_CMOUT_CONTROL; \
1181	uint32_t CM_BLNDGAM_LUT_WRITE_EN_MASK; \
1182	uint32_t CM_BLNDGAM_CONTROL; \
1183	uint32_t CM_BLNDGAM_RAMB_START_CNTL_B; \
1184	uint32_t CM_BLNDGAM_RAMB_START_CNTL_G; \
1185	uint32_t CM_BLNDGAM_RAMB_START_CNTL_R; \
1186	uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_B; \
1187	uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_G; \
1188	uint32_t CM_BLNDGAM_RAMB_SLOPE_CNTL_R; \
1189	uint32_t CM_BLNDGAM_RAMB_END_CNTL1_B; \
1190	uint32_t CM_BLNDGAM_RAMB_END_CNTL2_B; \
1191	uint32_t CM_BLNDGAM_RAMB_END_CNTL1_G; \
1192	uint32_t CM_BLNDGAM_RAMB_END_CNTL2_G; \
1193	uint32_t CM_BLNDGAM_RAMB_END_CNTL1_R; \
1194	uint32_t CM_BLNDGAM_RAMB_END_CNTL2_R; \
1195	uint32_t CM_BLNDGAM_RAMB_REGION_0_1; \
1196	uint32_t CM_BLNDGAM_RAMB_REGION_2_3; \
1197	uint32_t CM_BLNDGAM_RAMB_REGION_4_5; \
1198	uint32_t CM_BLNDGAM_RAMB_REGION_6_7; \
1199	uint32_t CM_BLNDGAM_RAMB_REGION_8_9; \
1200	uint32_t CM_BLNDGAM_RAMB_REGION_10_11; \
1201	uint32_t CM_BLNDGAM_RAMB_REGION_12_13; \
1202	uint32_t CM_BLNDGAM_RAMB_REGION_14_15; \
1203	uint32_t CM_BLNDGAM_RAMB_REGION_16_17; \
1204	uint32_t CM_BLNDGAM_RAMB_REGION_18_19; \
1205	uint32_t CM_BLNDGAM_RAMB_REGION_20_21; \
1206	uint32_t CM_BLNDGAM_RAMB_REGION_22_23; \
1207	uint32_t CM_BLNDGAM_RAMB_REGION_24_25; \
1208	uint32_t CM_BLNDGAM_RAMB_REGION_26_27; \
1209	uint32_t CM_BLNDGAM_RAMB_REGION_28_29; \
1210	uint32_t CM_BLNDGAM_RAMB_REGION_30_31; \
1211	uint32_t CM_BLNDGAM_RAMB_REGION_32_33; \
1212	uint32_t CM_BLNDGAM_RAMA_START_CNTL_B; \
1213	uint32_t CM_BLNDGAM_RAMA_START_CNTL_G; \
1214	uint32_t CM_BLNDGAM_RAMA_START_CNTL_R; \
1215	uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_B; \
1216	uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_G; \
1217	uint32_t CM_BLNDGAM_RAMA_SLOPE_CNTL_R; \
1218	uint32_t CM_BLNDGAM_RAMA_END_CNTL1_B; \
1219	uint32_t CM_BLNDGAM_RAMA_END_CNTL2_B; \
1220	uint32_t CM_BLNDGAM_RAMA_END_CNTL1_G; \
1221	uint32_t CM_BLNDGAM_RAMA_END_CNTL2_G; \
1222	uint32_t CM_BLNDGAM_RAMA_END_CNTL1_R; \
1223	uint32_t CM_BLNDGAM_RAMA_END_CNTL2_R; \
1224	uint32_t CM_BLNDGAM_RAMA_REGION_0_1; \
1225	uint32_t CM_BLNDGAM_RAMA_REGION_2_3; \
1226	uint32_t CM_BLNDGAM_RAMA_REGION_4_5; \
1227	uint32_t CM_BLNDGAM_RAMA_REGION_6_7; \
1228	uint32_t CM_BLNDGAM_RAMA_REGION_8_9; \
1229	uint32_t CM_BLNDGAM_RAMA_REGION_10_11; \
1230	uint32_t CM_BLNDGAM_RAMA_REGION_12_13; \
1231	uint32_t CM_BLNDGAM_RAMA_REGION_14_15; \
1232	uint32_t CM_BLNDGAM_RAMA_REGION_16_17; \
1233	uint32_t CM_BLNDGAM_RAMA_REGION_18_19; \
1234	uint32_t CM_BLNDGAM_RAMA_REGION_20_21; \
1235	uint32_t CM_BLNDGAM_RAMA_REGION_22_23; \
1236	uint32_t CM_BLNDGAM_RAMA_REGION_24_25; \
1237	uint32_t CM_BLNDGAM_RAMA_REGION_26_27; \
1238	uint32_t CM_BLNDGAM_RAMA_REGION_28_29; \
1239	uint32_t CM_BLNDGAM_RAMA_REGION_30_31; \
1240	uint32_t CM_BLNDGAM_RAMA_REGION_32_33; \
1241	uint32_t CM_BLNDGAM_LUT_INDEX; \
1242	uint32_t CM_3DLUT_MODE; \
1243	uint32_t CM_3DLUT_INDEX; \
1244	uint32_t CM_3DLUT_DATA; \
1245	uint32_t CM_3DLUT_DATA_30BIT; \
1246	uint32_t CM_3DLUT_READ_WRITE_CONTROL; \
1247	uint32_t CM_SHAPER_LUT_WRITE_EN_MASK; \
1248	uint32_t CM_SHAPER_CONTROL; \
1249	uint32_t CM_SHAPER_RAMB_START_CNTL_B; \
1250	uint32_t CM_SHAPER_RAMB_START_CNTL_G; \
1251	uint32_t CM_SHAPER_RAMB_START_CNTL_R; \
1252	uint32_t CM_SHAPER_RAMB_END_CNTL_B; \
1253	uint32_t CM_SHAPER_RAMB_END_CNTL_G; \
1254	uint32_t CM_SHAPER_RAMB_END_CNTL_R; \
1255	uint32_t CM_SHAPER_RAMB_REGION_0_1; \
1256	uint32_t CM_SHAPER_RAMB_REGION_2_3; \
1257	uint32_t CM_SHAPER_RAMB_REGION_4_5; \
1258	uint32_t CM_SHAPER_RAMB_REGION_6_7; \
1259	uint32_t CM_SHAPER_RAMB_REGION_8_9; \
1260	uint32_t CM_SHAPER_RAMB_REGION_10_11; \
1261	uint32_t CM_SHAPER_RAMB_REGION_12_13; \
1262	uint32_t CM_SHAPER_RAMB_REGION_14_15; \
1263	uint32_t CM_SHAPER_RAMB_REGION_16_17; \
1264	uint32_t CM_SHAPER_RAMB_REGION_18_19; \
1265	uint32_t CM_SHAPER_RAMB_REGION_20_21; \
1266	uint32_t CM_SHAPER_RAMB_REGION_22_23; \
1267	uint32_t CM_SHAPER_RAMB_REGION_24_25; \
1268	uint32_t CM_SHAPER_RAMB_REGION_26_27; \
1269	uint32_t CM_SHAPER_RAMB_REGION_28_29; \
1270	uint32_t CM_SHAPER_RAMB_REGION_30_31; \
1271	uint32_t CM_SHAPER_RAMB_REGION_32_33; \
1272	uint32_t CM_SHAPER_RAMA_START_CNTL_B; \
1273	uint32_t CM_SHAPER_RAMA_START_CNTL_G; \
1274	uint32_t CM_SHAPER_RAMA_START_CNTL_R; \
1275	uint32_t CM_SHAPER_RAMA_END_CNTL_B; \
1276	uint32_t CM_SHAPER_RAMA_END_CNTL_G; \
1277	uint32_t CM_SHAPER_RAMA_END_CNTL_R; \
1278	uint32_t CM_SHAPER_RAMA_REGION_0_1; \
1279	uint32_t CM_SHAPER_RAMA_REGION_2_3; \
1280	uint32_t CM_SHAPER_RAMA_REGION_4_5; \
1281	uint32_t CM_SHAPER_RAMA_REGION_6_7; \
1282	uint32_t CM_SHAPER_RAMA_REGION_8_9; \
1283	uint32_t CM_SHAPER_RAMA_REGION_10_11; \
1284	uint32_t CM_SHAPER_RAMA_REGION_12_13; \
1285	uint32_t CM_SHAPER_RAMA_REGION_14_15; \
1286	uint32_t CM_SHAPER_RAMA_REGION_16_17; \
1287	uint32_t CM_SHAPER_RAMA_REGION_18_19; \
1288	uint32_t CM_SHAPER_RAMA_REGION_20_21; \
1289	uint32_t CM_SHAPER_RAMA_REGION_22_23; \
1290	uint32_t CM_SHAPER_RAMA_REGION_24_25; \
1291	uint32_t CM_SHAPER_RAMA_REGION_26_27; \
1292	uint32_t CM_SHAPER_RAMA_REGION_28_29; \
1293	uint32_t CM_SHAPER_RAMA_REGION_30_31; \
1294	uint32_t CM_SHAPER_RAMA_REGION_32_33; \
1295	uint32_t CM_SHAPER_LUT_INDEX; \
1296	uint32_t CM_SHAPER_LUT_DATA; \
1297	uint32_t CM_ICSC_CONTROL; \
1298	uint32_t CM_ICSC_C11_C12; \
1299	uint32_t CM_ICSC_C33_C34; \
1300	uint32_t CM_BNS_VALUES_R; \
1301	uint32_t CM_BNS_VALUES_G; \
1302	uint32_t CM_BNS_VALUES_B; \
1303	uint32_t CM_DGAM_RAMB_START_CNTL_B; \
1304	uint32_t CM_DGAM_RAMB_START_CNTL_G; \
1305	uint32_t CM_DGAM_RAMB_START_CNTL_R; \
1306	uint32_t CM_DGAM_RAMB_SLOPE_CNTL_B; \
1307	uint32_t CM_DGAM_RAMB_SLOPE_CNTL_G; \
1308	uint32_t CM_DGAM_RAMB_SLOPE_CNTL_R; \
1309	uint32_t CM_DGAM_RAMB_END_CNTL1_B; \
1310	uint32_t CM_DGAM_RAMB_END_CNTL2_B; \
1311	uint32_t CM_DGAM_RAMB_END_CNTL1_G; \
1312	uint32_t CM_DGAM_RAMB_END_CNTL2_G; \
1313	uint32_t CM_DGAM_RAMB_END_CNTL1_R; \
1314	uint32_t CM_DGAM_RAMB_END_CNTL2_R; \
1315	uint32_t CM_DGAM_RAMB_REGION_0_1; \
1316	uint32_t CM_DGAM_RAMB_REGION_14_15; \
1317	uint32_t CM_DGAM_RAMA_START_CNTL_B; \
1318	uint32_t CM_DGAM_RAMA_START_CNTL_G; \
1319	uint32_t CM_DGAM_RAMA_START_CNTL_R; \
1320	uint32_t CM_DGAM_RAMA_SLOPE_CNTL_B; \
1321	uint32_t CM_DGAM_RAMA_SLOPE_CNTL_G; \
1322	uint32_t CM_DGAM_RAMA_SLOPE_CNTL_R; \
1323	uint32_t CM_DGAM_RAMA_END_CNTL1_B; \
1324	uint32_t CM_DGAM_RAMA_END_CNTL2_B; \
1325	uint32_t CM_DGAM_RAMA_END_CNTL1_G; \
1326	uint32_t CM_DGAM_RAMA_END_CNTL2_G; \
1327	uint32_t CM_DGAM_RAMA_END_CNTL1_R; \
1328	uint32_t CM_DGAM_RAMA_END_CNTL2_R; \
1329	uint32_t CM_DGAM_RAMA_REGION_0_1; \
1330	uint32_t CM_DGAM_RAMA_REGION_14_15; \
1331	uint32_t CM_DGAM_LUT_WRITE_EN_MASK; \
1332	uint32_t CM_DGAM_LUT_INDEX; \
1333	uint32_t CM_DGAM_LUT_DATA; \
1334	uint32_t CM_CONTROL; \
1335	uint32_t CM_DGAM_CONTROL; \
1336	uint32_t CM_IGAM_CONTROL; \
1337	uint32_t CM_IGAM_LUT_RW_CONTROL; \
1338	uint32_t CM_IGAM_LUT_RW_INDEX; \
1339	uint32_t CM_IGAM_LUT_SEQ_COLOR; \
1340	uint32_t CM_TEST_DEBUG_INDEX; \
1341	uint32_t CM_TEST_DEBUG_DATA; \
1342	uint32_t FORMAT_CONTROL; \
1343	uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
1344	uint32_t CURSOR_CONTROL; \
1345	uint32_t CURSOR0_CONTROL; \
1346	uint32_t CURSOR0_COLOR0; \
1347	uint32_t CURSOR0_COLOR1; \
1348	uint32_t DPP_CONTROL; \
1349	uint32_t CM_HDR_MULT_COEF; \
1350	uint32_t CURSOR0_FP_SCALE_BIAS;
1351
1352	struct dcn_dpp_registers {
1353	DPP_COMMON_REG_VARIABLE_LIST
1354	};
1355
1356	struct dcn10_dpp {
1357	struct dpp base;
1358
1359	const struct dcn_dpp_registers *tf_regs;
1360	const struct dcn_dpp_shift *tf_shift;
1361	const struct dcn_dpp_mask *tf_mask;
1362
1363	const uint16_t *filter_v;
1364	const uint16_t *filter_h;
1365	const uint16_t *filter_v_c;
1366	const uint16_t *filter_h_c;
1367	int lb_pixel_depth_supported;
1368	int lb_memory_size;
1369	int lb_bits_per_entry;
1370	bool is_write_to_ram_a_safe;
1371	struct scaler_data scl_data;
1372	struct pwl_params pwl_data;
1373	};
1374
1375	enum dcn10_input_csc_select {
1376	INPUT_CSC_SELECT_BYPASS = 0,
1377	INPUT_CSC_SELECT_ICSC = 1,
1378	INPUT_CSC_SELECT_COMA = 2
1379	};
1380
1381	void dpp1_set_cursor_attributes(
1382	struct dpp *dpp_base,
1383	struct dc_cursor_attributes *cursor_attributes);
1384
1385	void dpp1_set_cursor_position(
1386	struct dpp *dpp_base,
1387	const struct dc_cursor_position *pos,
1388	const struct dc_cursor_mi_param *param,
1389	uint32_t width,
1390	uint32_t height);
1391
1392	void dpp1_cnv_set_optional_cursor_attributes(
1393	struct dpp *dpp_base,
1394	struct dpp_cursor_attributes *attr);
1395
1396	bool dpp1_dscl_is_lb_conf_valid(
1397	int ceil_vratio,
1398	int num_partitions,
1399	int vtaps);
1400
1401	void dpp1_dscl_calc_lb_num_partitions(
1402	const struct scaler_data *scl_data,
1403	enum lb_memory_config lb_config,
1404	int *num_part_y,
1405	int *num_part_c);
1406
1407	void dpp1_degamma_ram_select(
1408	struct dpp *dpp_base,
1409	bool use_ram_a);
1410
1411	void dpp1_program_degamma_luta_settings(
1412	struct dpp *dpp_base,
1413	const struct pwl_params *params);
1414
1415	void dpp1_program_degamma_lutb_settings(
1416	struct dpp *dpp_base,
1417	const struct pwl_params *params);
1418
1419	void dpp1_program_degamma_lut(
1420	struct dpp *dpp_base,
1421	const struct pwl_result_data *rgb,
1422	uint32_t num,
1423	bool is_ram_a);
1424
1425	void dpp1_power_on_degamma_lut(
1426	struct dpp *dpp_base,
1427	bool power_on);
1428
1429	void dpp1_program_input_csc(
1430	struct dpp *dpp_base,
1431	enum dc_color_space color_space,
1432	enum dcn10_input_csc_select select,
1433	const struct out_csc_color_matrix *tbl_entry);
1434
1435	void dpp1_program_bias_and_scale(
1436	struct dpp *dpp_base,
1437	struct dc_bias_and_scale *params);
1438
1439	void dpp1_program_input_lut(
1440	struct dpp *dpp_base,
1441	const struct dc_gamma *gamma);
1442
1443	void dpp1_full_bypass(struct dpp *dpp_base);
1444
1445	void dpp1_set_degamma(
1446	struct dpp *dpp_base,
1447	enum ipp_degamma_mode mode);
1448
1449	void dpp1_set_degamma_pwl(struct dpp *dpp_base,
1450	const struct pwl_params *params);
1451
1452
1453	void dpp_read_state(struct dpp *dpp_base,
1454	struct dcn_dpp_state *s);
1455
1456	void dpp_reset(struct dpp *dpp_base);
1457
1458	void dpp1_cm_program_regamma_lut(
1459	struct dpp *dpp_base,
1460	const struct pwl_result_data *rgb,
1461	uint32_t num);
1462
1463	void dpp1_cm_power_on_regamma_lut(
1464	struct dpp *dpp_base,
1465	bool power_on);
1466
1467	void dpp1_cm_configure_regamma_lut(
1468	struct dpp *dpp_base,
1469	bool is_ram_a);
1470
1471	/*program re gamma RAM A*/
1472	void dpp1_cm_program_regamma_luta_settings(
1473	struct dpp *dpp_base,
1474	const struct pwl_params *params);
1475
1476	/*program re gamma RAM B*/
1477	void dpp1_cm_program_regamma_lutb_settings(
1478	struct dpp *dpp_base,
1479	const struct pwl_params *params);
1480	void dpp1_cm_set_output_csc_adjustment(
1481	struct dpp *dpp_base,
1482	const uint16_t *regval);
1483
1484	void dpp1_cm_set_output_csc_default(
1485	struct dpp *dpp_base,
1486	enum dc_color_space colorspace);
1487
1488	void dpp1_cm_set_gamut_remap(
1489	struct dpp *dpp,
1490	const struct dpp_grph_csc_adjustment *adjust);
1491
1492	void dpp1_dscl_set_scaler_manual_scale(
1493	struct dpp *dpp_base,
1494	const struct scaler_data *scl_data);
1495
1496	void dpp1_cnv_setup (
1497	struct dpp *dpp_base,
1498	enum surface_pixel_format format,
1499	enum expansion_mode mode,
1500	struct dc_csc_transform input_csc_color_matrix,
1501	enum dc_color_space input_color_space,
1502	struct cnv_alpha_2bit_lut *alpha_2bit_lut);
1503
1504	void dpp1_dppclk_control(
1505	struct dpp *dpp_base,
1506	bool dppclk_div,
1507	bool enable);
1508
1509	void dpp1_set_hdr_multiplier(
1510	struct dpp *dpp_base,
1511	uint32_t multiplier);
1512
1513	bool dpp1_get_optimal_number_of_taps(
1514	struct dpp *dpp,
1515	struct scaler_data *scl_data,
1516	const struct scaling_taps *in_taps);
1517
1518	void dpp1_construct(struct dcn10_dpp *dpp1,
1519	struct dc_context *ctx,
1520	uint32_t inst,
1521	const struct dcn_dpp_registers *tf_regs,
1522	const struct dcn_dpp_shift *tf_shift,
1523	const struct dcn_dpp_mask *tf_mask);
1524	#endif
1525