1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "reg_helper.h"
27
28#include "core_types.h"
29#include "link_encoder.h"
30#include "dcn10_link_encoder.h"
31#include "stream_encoder.h"
32#include "dc_bios_types.h"
33
34#include "gpio_service_interface.h"
35
36#define CTX \
37 enc10->base.ctx
38#define DC_LOGGER \
39 enc10->base.ctx->logger
40
41#define REG(reg)\
42 (enc10->link_regs->reg)
43
44#undef FN
45#define FN(reg_name, field_name) \
46 enc10->link_shift->field_name, enc10->link_mask->field_name
47
48
49/*
50 * @brief
51 * Trigger Source Select
52 * ASIC-dependent, actual values for register programming
53 */
54#define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0
55#define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1
56#define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2
57#define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4
58#define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08
59#define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10
60#define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20
61#define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40
62
63enum {
64 DP_MST_UPDATE_MAX_RETRY = 50
65};
66
67static const struct link_encoder_funcs dcn10_lnk_enc_funcs = {
68 .validate_output_with_stream =
69 dcn10_link_encoder_validate_output_with_stream,
70 .hw_init = dcn10_link_encoder_hw_init,
71 .setup = dcn10_link_encoder_setup,
72 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
73 .enable_dp_output = dcn10_link_encoder_enable_dp_output,
74 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output,
75 .disable_output = dcn10_link_encoder_disable_output,
76 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
77 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
78 .update_mst_stream_allocation_table =
79 dcn10_link_encoder_update_mst_stream_allocation_table,
80 .psr_program_dp_dphy_fast_training =
81 dcn10_psr_program_dp_dphy_fast_training,
82 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
83 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
84 .enable_hpd = dcn10_link_encoder_enable_hpd,
85 .disable_hpd = dcn10_link_encoder_disable_hpd,
86 .is_dig_enabled = dcn10_is_dig_enabled,
87 .get_dig_frontend = dcn10_get_dig_frontend,
88 .get_dig_mode = dcn10_get_dig_mode,
89 .destroy = dcn10_link_encoder_destroy,
90 .get_max_link_cap = dcn10_link_encoder_get_max_link_cap,
91};
92
93static enum bp_result link_transmitter_control(
94 struct dcn10_link_encoder *enc10,
95 struct bp_transmitter_control *cntl)
96{
97 enum bp_result result;
98 struct dc_bios *bp = enc10->base.ctx->dc_bios;
99
100 result = bp->funcs->transmitter_control(bp, cntl);
101
102 return result;
103}
104
105static void enable_phy_bypass_mode(
106 struct dcn10_link_encoder *enc10,
107 bool enable)
108{
109 /* This register resides in DP back end block;
110 * transmitter is used for the offset
111 */
112 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable);
113
114}
115
116static void disable_prbs_symbols(
117 struct dcn10_link_encoder *enc10,
118 bool disable)
119{
120 /* This register resides in DP back end block;
121 * transmitter is used for the offset
122 */
123 REG_UPDATE_4(DP_DPHY_CNTL,
124 DPHY_ATEST_SEL_LANE0, disable,
125 DPHY_ATEST_SEL_LANE1, disable,
126 DPHY_ATEST_SEL_LANE2, disable,
127 DPHY_ATEST_SEL_LANE3, disable);
128}
129
130static void disable_prbs_mode(
131 struct dcn10_link_encoder *enc10)
132{
133 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0);
134}
135
136static void program_pattern_symbols(
137 struct dcn10_link_encoder *enc10,
138 uint16_t pattern_symbols[8])
139{
140 /* This register resides in DP back end block;
141 * transmitter is used for the offset
142 */
143 REG_SET_3(DP_DPHY_SYM0, 0,
144 DPHY_SYM1, pattern_symbols[0],
145 DPHY_SYM2, pattern_symbols[1],
146 DPHY_SYM3, pattern_symbols[2]);
147
148 /* This register resides in DP back end block;
149 * transmitter is used for the offset
150 */
151 REG_SET_3(DP_DPHY_SYM1, 0,
152 DPHY_SYM4, pattern_symbols[3],
153 DPHY_SYM5, pattern_symbols[4],
154 DPHY_SYM6, pattern_symbols[5]);
155
156 /* This register resides in DP back end block;
157 * transmitter is used for the offset
158 */
159 REG_SET_2(DP_DPHY_SYM2, 0,
160 DPHY_SYM7, pattern_symbols[6],
161 DPHY_SYM8, pattern_symbols[7]);
162}
163
164static void set_dp_phy_pattern_d102(
165 struct dcn10_link_encoder *enc10)
166{
167 /* Disable PHY Bypass mode to setup the test pattern */
168 enable_phy_bypass_mode(enc10, enable: false);
169
170 /* For 10-bit PRBS or debug symbols
171 * please use the following sequence:
172 *
173 * Enable debug symbols on the lanes
174 */
175 disable_prbs_symbols(enc10, disable: true);
176
177 /* Disable PRBS mode */
178 disable_prbs_mode(enc10);
179
180 /* Program debug symbols to be output */
181 {
182 uint16_t pattern_symbols[8] = {
183 0x2AA, 0x2AA, 0x2AA, 0x2AA,
184 0x2AA, 0x2AA, 0x2AA, 0x2AA
185 };
186
187 program_pattern_symbols(enc10, pattern_symbols);
188 }
189
190 /* Enable phy bypass mode to enable the test pattern */
191
192 enable_phy_bypass_mode(enc10, enable: true);
193}
194
195static void set_link_training_complete(
196 struct dcn10_link_encoder *enc10,
197 bool complete)
198{
199 /* This register resides in DP back end block;
200 * transmitter is used for the offset
201 */
202 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete);
203
204}
205
206void dcn10_link_encoder_set_dp_phy_pattern_training_pattern(
207 struct link_encoder *enc,
208 uint32_t index)
209{
210 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
211 /* Write Training Pattern */
212
213 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index);
214
215 /* Set HW Register Training Complete to false */
216
217 set_link_training_complete(enc10, complete: false);
218
219 /* Disable PHY Bypass mode to output Training Pattern */
220
221 enable_phy_bypass_mode(enc10, enable: false);
222
223 /* Disable PRBS mode */
224 disable_prbs_mode(enc10);
225}
226
227static void setup_panel_mode(
228 struct dcn10_link_encoder *enc10,
229 enum dp_panel_mode panel_mode)
230{
231 uint32_t value;
232
233 if (!REG(DP_DPHY_INTERNAL_CTRL))
234 return;
235
236 value = REG_READ(DP_DPHY_INTERNAL_CTRL);
237
238 switch (panel_mode) {
239 case DP_PANEL_MODE_EDP:
240 value = 0x1;
241 break;
242 case DP_PANEL_MODE_SPECIAL:
243 value = 0x11;
244 break;
245 default:
246 value = 0x0;
247 break;
248 }
249
250 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value);
251}
252
253static void set_dp_phy_pattern_symbol_error(
254 struct dcn10_link_encoder *enc10)
255{
256 /* Disable PHY Bypass mode to setup the test pattern */
257 enable_phy_bypass_mode(enc10, enable: false);
258
259 /* program correct panel mode*/
260 setup_panel_mode(enc10, panel_mode: DP_PANEL_MODE_DEFAULT);
261
262 /* A PRBS23 pattern is used for most DP electrical measurements. */
263
264 /* Enable PRBS symbols on the lanes */
265 disable_prbs_symbols(enc10, disable: false);
266
267 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */
268 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
269 DPHY_PRBS_SEL, 1,
270 DPHY_PRBS_EN, 1);
271
272 /* Enable phy bypass mode to enable the test pattern */
273 enable_phy_bypass_mode(enc10, enable: true);
274}
275
276static void set_dp_phy_pattern_prbs7(
277 struct dcn10_link_encoder *enc10)
278{
279 /* Disable PHY Bypass mode to setup the test pattern */
280 enable_phy_bypass_mode(enc10, enable: false);
281
282 /* A PRBS7 pattern is used for most DP electrical measurements. */
283
284 /* Enable PRBS symbols on the lanes */
285 disable_prbs_symbols(enc10, disable: false);
286
287 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */
288 REG_UPDATE_2(DP_DPHY_PRBS_CNTL,
289 DPHY_PRBS_SEL, 0,
290 DPHY_PRBS_EN, 1);
291
292 /* Enable phy bypass mode to enable the test pattern */
293 enable_phy_bypass_mode(enc10, enable: true);
294}
295
296static void set_dp_phy_pattern_80bit_custom(
297 struct dcn10_link_encoder *enc10,
298 const uint8_t *pattern)
299{
300 /* Disable PHY Bypass mode to setup the test pattern */
301 enable_phy_bypass_mode(enc10, enable: false);
302
303 /* Enable debug symbols on the lanes */
304
305 disable_prbs_symbols(enc10, disable: true);
306
307 /* Enable PHY bypass mode to enable the test pattern */
308 /* TODO is it really needed ? */
309
310 enable_phy_bypass_mode(enc10, enable: true);
311
312 /* Program 80 bit custom pattern */
313 {
314 uint16_t pattern_symbols[8];
315
316 pattern_symbols[0] =
317 ((pattern[1] & 0x03) << 8) | pattern[0];
318 pattern_symbols[1] =
319 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f);
320 pattern_symbols[2] =
321 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f);
322 pattern_symbols[3] =
323 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03);
324 pattern_symbols[4] =
325 ((pattern[6] & 0x03) << 8) | pattern[5];
326 pattern_symbols[5] =
327 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f);
328 pattern_symbols[6] =
329 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f);
330 pattern_symbols[7] =
331 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03);
332
333 program_pattern_symbols(enc10, pattern_symbols);
334 }
335
336 /* Enable phy bypass mode to enable the test pattern */
337
338 enable_phy_bypass_mode(enc10, enable: true);
339}
340
341static void set_dp_phy_pattern_hbr2_compliance_cp2520_2(
342 struct dcn10_link_encoder *enc10,
343 unsigned int cp2520_pattern)
344{
345
346 /* previously there is a register DP_HBR2_EYE_PATTERN
347 * that is enabled to get the pattern.
348 * But it does not work with the latest spec change,
349 * so we are programming the following registers manually.
350 *
351 * The following settings have been confirmed
352 * by Nick Chorney and Sandra Liu
353 */
354
355 /* Disable PHY Bypass mode to setup the test pattern */
356
357 enable_phy_bypass_mode(enc10, enable: false);
358
359 /* Setup DIG encoder in DP SST mode */
360 enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT);
361
362 /* ensure normal panel mode. */
363 setup_panel_mode(enc10, panel_mode: DP_PANEL_MODE_DEFAULT);
364
365 /* no vbid after BS (SR)
366 * DP_LINK_FRAMING_CNTL changed history Sandra Liu
367 * 11000260 / 11000104 / 110000FC
368 */
369 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
370 DP_IDLE_BS_INTERVAL, 0xFC,
371 DP_VBID_DISABLE, 1,
372 DP_VID_ENHANCED_FRAME_MODE, 1);
373
374 /* swap every BS with SR */
375 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0);
376
377 /* select cp2520 patterns */
378 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL))
379 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL,
380 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern);
381 else
382 /* pre-DCE11 can only generate CP2520 pattern 2 */
383 ASSERT(cp2520_pattern == 2);
384
385 /* set link training complete */
386 set_link_training_complete(enc10, complete: true);
387
388 /* disable video stream */
389 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
390
391 /* Disable PHY Bypass mode to setup the test pattern */
392 enable_phy_bypass_mode(enc10, enable: false);
393}
394
395static void set_dp_phy_pattern_passthrough_mode(
396 struct dcn10_link_encoder *enc10,
397 enum dp_panel_mode panel_mode)
398{
399 /* program correct panel mode */
400 setup_panel_mode(enc10, panel_mode);
401
402 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT
403 * in case we were doing HBR2 compliance pattern before
404 */
405 REG_UPDATE_3(DP_LINK_FRAMING_CNTL,
406 DP_IDLE_BS_INTERVAL, 0x2000,
407 DP_VBID_DISABLE, 0,
408 DP_VID_ENHANCED_FRAME_MODE, 1);
409
410 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF);
411
412 /* set link training complete */
413 set_link_training_complete(enc10, complete: true);
414
415 /* Disable PHY Bypass mode to setup the test pattern */
416 enable_phy_bypass_mode(enc10, enable: false);
417
418 /* Disable PRBS mode */
419 disable_prbs_mode(enc10);
420}
421
422/* return value is bit-vector */
423static uint8_t get_frontend_source(
424 enum engine_id engine)
425{
426 switch (engine) {
427 case ENGINE_ID_DIGA:
428 return DCN10_DIG_FE_SOURCE_SELECT_DIGA;
429 case ENGINE_ID_DIGB:
430 return DCN10_DIG_FE_SOURCE_SELECT_DIGB;
431 case ENGINE_ID_DIGC:
432 return DCN10_DIG_FE_SOURCE_SELECT_DIGC;
433 case ENGINE_ID_DIGD:
434 return DCN10_DIG_FE_SOURCE_SELECT_DIGD;
435 case ENGINE_ID_DIGE:
436 return DCN10_DIG_FE_SOURCE_SELECT_DIGE;
437 case ENGINE_ID_DIGF:
438 return DCN10_DIG_FE_SOURCE_SELECT_DIGF;
439 case ENGINE_ID_DIGG:
440 return DCN10_DIG_FE_SOURCE_SELECT_DIGG;
441 default:
442 ASSERT_CRITICAL(false);
443 return DCN10_DIG_FE_SOURCE_SELECT_INVALID;
444 }
445}
446
447unsigned int dcn10_get_dig_frontend(struct link_encoder *enc)
448{
449 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
450 int32_t value;
451 enum engine_id result;
452
453 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value);
454
455 switch (value) {
456 case DCN10_DIG_FE_SOURCE_SELECT_DIGA:
457 result = ENGINE_ID_DIGA;
458 break;
459 case DCN10_DIG_FE_SOURCE_SELECT_DIGB:
460 result = ENGINE_ID_DIGB;
461 break;
462 case DCN10_DIG_FE_SOURCE_SELECT_DIGC:
463 result = ENGINE_ID_DIGC;
464 break;
465 case DCN10_DIG_FE_SOURCE_SELECT_DIGD:
466 result = ENGINE_ID_DIGD;
467 break;
468 case DCN10_DIG_FE_SOURCE_SELECT_DIGE:
469 result = ENGINE_ID_DIGE;
470 break;
471 case DCN10_DIG_FE_SOURCE_SELECT_DIGF:
472 result = ENGINE_ID_DIGF;
473 break;
474 case DCN10_DIG_FE_SOURCE_SELECT_DIGG:
475 result = ENGINE_ID_DIGG;
476 break;
477 default:
478 // invalid source select DIG
479 result = ENGINE_ID_UNKNOWN;
480 }
481
482 return result;
483
484}
485
486void enc1_configure_encoder(
487 struct dcn10_link_encoder *enc10,
488 const struct dc_link_settings *link_settings)
489{
490 /* set number of lanes */
491 REG_SET(DP_CONFIG, 0,
492 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE);
493
494 /* setup scrambler */
495 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1);
496}
497
498void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc,
499 bool exit_link_training_required)
500{
501 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
502
503 if (exit_link_training_required)
504 REG_UPDATE(DP_DPHY_FAST_TRAINING,
505 DPHY_RX_FAST_TRAINING_CAPABLE, 1);
506 else {
507 REG_UPDATE(DP_DPHY_FAST_TRAINING,
508 DPHY_RX_FAST_TRAINING_CAPABLE, 0);
509 /*In DCE 11, we are able to pre-program a Force SR register
510 * to be able to trigger SR symbol after 5 idle patterns
511 * transmitted. Upon PSR Exit, DMCU can trigger
512 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to
513 * DPHY_LOAD_BS_COUNT_START and the internal counter
514 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be
515 * replaced by SR symbol once.
516 */
517
518 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5);
519 }
520}
521
522void dcn10_psr_program_secondary_packet(struct link_encoder *enc,
523 unsigned int sdp_transmit_line_num_deadline)
524{
525 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
526
527 REG_UPDATE_2(DP_SEC_CNTL1,
528 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline,
529 DP_SEC_GSP0_PRIORITY, 1);
530}
531
532bool dcn10_is_dig_enabled(struct link_encoder *enc)
533{
534 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
535 uint32_t value;
536
537 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);
538 return value;
539}
540
541static void link_encoder_disable(struct dcn10_link_encoder *enc10)
542{
543 /* reset training pattern */
544 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0,
545 DPHY_TRAINING_PATTERN_SEL, 0);
546
547 /* reset training complete */
548 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0);
549
550 /* reset panel mode */
551 setup_panel_mode(enc10, panel_mode: DP_PANEL_MODE_DEFAULT);
552}
553
554static void hpd_initialize(
555 struct dcn10_link_encoder *enc10)
556{
557 /* Associate HPD with DIG_BE */
558 enum hpd_source_id hpd_source = enc10->base.hpd_source;
559
560 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source);
561}
562
563bool dcn10_link_encoder_validate_dvi_output(
564 const struct dcn10_link_encoder *enc10,
565 enum signal_type connector_signal,
566 enum signal_type signal,
567 const struct dc_crtc_timing *crtc_timing)
568{
569 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK;
570
571 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK)
572 max_pixel_clock *= 2;
573
574 /* This handles the case of HDMI downgrade to DVI we don't want to
575 * we don't want to cap the pixel clock if the DDI is not DVI.
576 */
577 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK &&
578 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK)
579 max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock;
580
581 /* DVI only support RGB pixel encoding */
582 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB)
583 return false;
584
585 /*connect DVI via adpater's HDMI connector*/
586 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
587 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) &&
588 signal != SIGNAL_TYPE_HDMI_TYPE_A &&
589 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10))
590 return false;
591 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
592 return false;
593
594 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10))
595 return false;
596
597 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */
598 switch (crtc_timing->display_color_depth) {
599 case COLOR_DEPTH_666:
600 case COLOR_DEPTH_888:
601 break;
602 case COLOR_DEPTH_101010:
603 case COLOR_DEPTH_161616:
604 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK)
605 return false;
606 break;
607 default:
608 return false;
609 }
610
611 return true;
612}
613
614static bool dcn10_link_encoder_validate_hdmi_output(
615 const struct dcn10_link_encoder *enc10,
616 const struct dc_crtc_timing *crtc_timing,
617 const struct dc_edid_caps *edid_caps,
618 int adjusted_pix_clk_100hz)
619{
620 enum dc_color_depth max_deep_color =
621 enc10->base.features.max_hdmi_deep_color;
622
623 // check pixel clock against edid specified max TMDS clk
624 if (edid_caps->max_tmds_clk_mhz != 0 &&
625 adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000)
626 return false;
627
628 if (max_deep_color < crtc_timing->display_color_depth)
629 return false;
630
631 if (crtc_timing->display_color_depth < COLOR_DEPTH_888)
632 return false;
633 if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10))
634 return false;
635
636 if ((adjusted_pix_clk_100hz == 0) ||
637 (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10)))
638 return false;
639
640 /* DCE11 HW does not support 420 */
641 if (!enc10->base.features.hdmi_ycbcr420_supported &&
642 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
643 return false;
644
645 if ((!enc10->base.features.flags.bits.HDMI_6GB_EN ||
646 enc10->base.ctx->dc->debug.hdmi20_disable) &&
647 adjusted_pix_clk_100hz >= 3000000)
648 return false;
649 if (enc10->base.ctx->dc->debug.hdmi20_disable &&
650 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
651 return false;
652 return true;
653}
654
655bool dcn10_link_encoder_validate_dp_output(
656 const struct dcn10_link_encoder *enc10,
657 const struct dc_crtc_timing *crtc_timing)
658{
659 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
660 if (!enc10->base.features.dp_ycbcr420_supported)
661 return false;
662 }
663
664 return true;
665}
666
667void dcn10_link_encoder_construct(
668 struct dcn10_link_encoder *enc10,
669 const struct encoder_init_data *init_data,
670 const struct encoder_feature_support *enc_features,
671 const struct dcn10_link_enc_registers *link_regs,
672 const struct dcn10_link_enc_aux_registers *aux_regs,
673 const struct dcn10_link_enc_hpd_registers *hpd_regs,
674 const struct dcn10_link_enc_shift *link_shift,
675 const struct dcn10_link_enc_mask *link_mask)
676{
677 struct bp_encoder_cap_info bp_cap_info = {0};
678 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
679 enum bp_result result = BP_RESULT_OK;
680
681 enc10->base.funcs = &dcn10_lnk_enc_funcs;
682 enc10->base.ctx = init_data->ctx;
683 enc10->base.id = init_data->encoder;
684
685 enc10->base.hpd_source = init_data->hpd_source;
686 enc10->base.connector = init_data->connector;
687
688 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
689
690 enc10->base.features = *enc_features;
691
692 enc10->base.transmitter = init_data->transmitter;
693
694 /* set the flag to indicate whether driver poll the I2C data pin
695 * while doing the DP sink detect
696 */
697
698/* if (dal_adapter_service_is_feature_supported(as,
699 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
700 enc10->base.features.flags.bits.
701 DP_SINK_DETECT_POLL_DATA_PIN = true;*/
702
703 enc10->base.output_signals =
704 SIGNAL_TYPE_DVI_SINGLE_LINK |
705 SIGNAL_TYPE_DVI_DUAL_LINK |
706 SIGNAL_TYPE_LVDS |
707 SIGNAL_TYPE_DISPLAY_PORT |
708 SIGNAL_TYPE_DISPLAY_PORT_MST |
709 SIGNAL_TYPE_EDP |
710 SIGNAL_TYPE_HDMI_TYPE_A;
711
712 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
713 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
714 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
715 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
716 * Prefer DIG assignment is decided by board design.
717 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
718 * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
719 * By this, adding DIGG should not hurt DCE 8.0.
720 * This will let DCE 8.1 share DCE 8.0 as much as possible
721 */
722
723 enc10->link_regs = link_regs;
724 enc10->aux_regs = aux_regs;
725 enc10->hpd_regs = hpd_regs;
726 enc10->link_shift = link_shift;
727 enc10->link_mask = link_mask;
728
729 switch (enc10->base.transmitter) {
730 case TRANSMITTER_UNIPHY_A:
731 enc10->base.preferred_engine = ENGINE_ID_DIGA;
732 break;
733 case TRANSMITTER_UNIPHY_B:
734 enc10->base.preferred_engine = ENGINE_ID_DIGB;
735 break;
736 case TRANSMITTER_UNIPHY_C:
737 enc10->base.preferred_engine = ENGINE_ID_DIGC;
738 break;
739 case TRANSMITTER_UNIPHY_D:
740 enc10->base.preferred_engine = ENGINE_ID_DIGD;
741 break;
742 case TRANSMITTER_UNIPHY_E:
743 enc10->base.preferred_engine = ENGINE_ID_DIGE;
744 break;
745 case TRANSMITTER_UNIPHY_F:
746 enc10->base.preferred_engine = ENGINE_ID_DIGF;
747 break;
748 case TRANSMITTER_UNIPHY_G:
749 enc10->base.preferred_engine = ENGINE_ID_DIGG;
750 break;
751 default:
752 ASSERT_CRITICAL(false);
753 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
754 }
755
756 /* default to one to mirror Windows behavior */
757 enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
758
759 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
760 enc10->base.id, &bp_cap_info);
761
762 /* Override features with DCE-specific values */
763 if (result == BP_RESULT_OK) {
764 enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
765 bp_cap_info.DP_HBR2_EN;
766 enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
767 bp_cap_info.DP_HBR3_EN;
768 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
769 enc10->base.features.flags.bits.DP_IS_USB_C =
770 bp_cap_info.DP_IS_USB_C;
771 } else {
772 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
773 __func__,
774 result);
775 }
776 if (enc10->base.ctx->dc->debug.hdmi20_disable) {
777 enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
778 }
779}
780
781bool dcn10_link_encoder_validate_output_with_stream(
782 struct link_encoder *enc,
783 const struct dc_stream_state *stream)
784{
785 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
786 bool is_valid;
787
788 //if SCDC (340-600MHz) is disabled, set to HDMI 1.4 timing limit
789 if (stream->sink->edid_caps.panel_patch.skip_scdc_overwrite &&
790 enc10->base.features.max_hdmi_pixel_clock > 300000)
791 enc10->base.features.max_hdmi_pixel_clock = 300000;
792
793 switch (stream->signal) {
794 case SIGNAL_TYPE_DVI_SINGLE_LINK:
795 case SIGNAL_TYPE_DVI_DUAL_LINK:
796 is_valid = dcn10_link_encoder_validate_dvi_output(
797 enc10,
798 connector_signal: stream->link->connector_signal,
799 signal: stream->signal,
800 crtc_timing: &stream->timing);
801 break;
802 case SIGNAL_TYPE_HDMI_TYPE_A:
803 is_valid = dcn10_link_encoder_validate_hdmi_output(
804 enc10,
805 crtc_timing: &stream->timing,
806 edid_caps: &stream->sink->edid_caps,
807 adjusted_pix_clk_100hz: stream->phy_pix_clk * 10);
808 break;
809 case SIGNAL_TYPE_DISPLAY_PORT:
810 case SIGNAL_TYPE_DISPLAY_PORT_MST:
811 is_valid = dcn10_link_encoder_validate_dp_output(
812 enc10, crtc_timing: &stream->timing);
813 break;
814 case SIGNAL_TYPE_EDP:
815 is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
816 break;
817 case SIGNAL_TYPE_VIRTUAL:
818 is_valid = true;
819 break;
820 default:
821 is_valid = false;
822 break;
823 }
824
825 return is_valid;
826}
827
828void dcn10_link_encoder_hw_init(
829 struct link_encoder *enc)
830{
831 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
832 struct bp_transmitter_control cntl = { 0 };
833 enum bp_result result;
834
835 cntl.action = TRANSMITTER_CONTROL_INIT;
836 cntl.engine_id = ENGINE_ID_UNKNOWN;
837 cntl.transmitter = enc10->base.transmitter;
838 cntl.connector_obj_id = enc10->base.connector;
839 cntl.lanes_number = LANE_COUNT_FOUR;
840 cntl.coherent = false;
841 cntl.hpd_sel = enc10->base.hpd_source;
842
843 if (enc10->base.connector.id == CONNECTOR_ID_EDP)
844 cntl.signal = SIGNAL_TYPE_EDP;
845
846 result = link_transmitter_control(enc10, cntl: &cntl);
847
848 if (result != BP_RESULT_OK) {
849 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
850 __func__);
851 BREAK_TO_DEBUGGER();
852 return;
853 }
854
855 if (enc10->base.connector.id == CONNECTOR_ID_LVDS) {
856 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS;
857
858 result = link_transmitter_control(enc10, cntl: &cntl);
859
860 ASSERT(result == BP_RESULT_OK);
861
862 }
863 dcn10_aux_initialize(enc10);
864
865 /* reinitialize HPD.
866 * hpd_initialize() will pass DIG_FE id to HW context.
867 * All other routine within HW context will use fe_engine_offset
868 * as DIG_FE id even caller pass DIG_FE id.
869 * So this routine must be called first.
870 */
871 hpd_initialize(enc10);
872}
873
874void dcn10_link_encoder_destroy(struct link_encoder **enc)
875{
876 kfree(TO_DCN10_LINK_ENC(*enc));
877 *enc = NULL;
878}
879
880void dcn10_link_encoder_setup(
881 struct link_encoder *enc,
882 enum signal_type signal)
883{
884 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
885
886 switch (signal) {
887 case SIGNAL_TYPE_EDP:
888 case SIGNAL_TYPE_DISPLAY_PORT:
889 /* DP SST */
890 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0);
891 break;
892 case SIGNAL_TYPE_LVDS:
893 /* LVDS */
894 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1);
895 break;
896 case SIGNAL_TYPE_DVI_SINGLE_LINK:
897 case SIGNAL_TYPE_DVI_DUAL_LINK:
898 /* TMDS-DVI */
899 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2);
900 break;
901 case SIGNAL_TYPE_HDMI_TYPE_A:
902 /* TMDS-HDMI */
903 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3);
904 break;
905 case SIGNAL_TYPE_DISPLAY_PORT_MST:
906 /* DP MST */
907 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5);
908 break;
909 default:
910 ASSERT_CRITICAL(false);
911 /* invalid mode ! */
912 break;
913 }
914
915}
916
917/* TODO: still need depth or just pass in adjusted pixel clock? */
918void dcn10_link_encoder_enable_tmds_output(
919 struct link_encoder *enc,
920 enum clock_source_id clock_source,
921 enum dc_color_depth color_depth,
922 enum signal_type signal,
923 uint32_t pixel_clock)
924{
925 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
926 struct bp_transmitter_control cntl = { 0 };
927 enum bp_result result;
928
929 /* Enable the PHY */
930
931 cntl.action = TRANSMITTER_CONTROL_ENABLE;
932 cntl.engine_id = enc->preferred_engine;
933 cntl.transmitter = enc10->base.transmitter;
934 cntl.pll_id = clock_source;
935 cntl.signal = signal;
936 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK)
937 cntl.lanes_number = 8;
938 else
939 cntl.lanes_number = 4;
940
941 cntl.hpd_sel = enc10->base.hpd_source;
942
943 cntl.pixel_clock = pixel_clock;
944 cntl.color_depth = color_depth;
945
946 result = link_transmitter_control(enc10, cntl: &cntl);
947
948 if (result != BP_RESULT_OK) {
949 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
950 __func__);
951 BREAK_TO_DEBUGGER();
952 }
953}
954
955void dcn10_link_encoder_enable_tmds_output_with_clk_pattern_wa(
956 struct link_encoder *enc,
957 enum clock_source_id clock_source,
958 enum dc_color_depth color_depth,
959 enum signal_type signal,
960 uint32_t pixel_clock)
961{
962 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
963
964 dcn10_link_encoder_enable_tmds_output(
965 enc, clock_source, color_depth, signal, pixel_clock);
966
967 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
968}
969
970/* enables DP PHY output */
971void dcn10_link_encoder_enable_dp_output(
972 struct link_encoder *enc,
973 const struct dc_link_settings *link_settings,
974 enum clock_source_id clock_source)
975{
976 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
977 struct bp_transmitter_control cntl = { 0 };
978 enum bp_result result;
979
980 /* Enable the PHY */
981
982 /* number_of_lanes is used for pixel clock adjust,
983 * but it's not passed to asic_control.
984 * We need to set number of lanes manually.
985 */
986 enc1_configure_encoder(enc10, link_settings);
987
988 cntl.action = TRANSMITTER_CONTROL_ENABLE;
989 cntl.engine_id = enc->preferred_engine;
990 cntl.transmitter = enc10->base.transmitter;
991 cntl.pll_id = clock_source;
992 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT;
993 cntl.lanes_number = link_settings->lane_count;
994 cntl.hpd_sel = enc10->base.hpd_source;
995 cntl.pixel_clock = link_settings->link_rate
996 * LINK_RATE_REF_FREQ_IN_KHZ;
997 /* TODO: check if undefined works */
998 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
999
1000 result = link_transmitter_control(enc10, cntl: &cntl);
1001
1002 if (result != BP_RESULT_OK) {
1003 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1004 __func__);
1005 BREAK_TO_DEBUGGER();
1006 }
1007}
1008
1009/* enables DP PHY output in MST mode */
1010void dcn10_link_encoder_enable_dp_mst_output(
1011 struct link_encoder *enc,
1012 const struct dc_link_settings *link_settings,
1013 enum clock_source_id clock_source)
1014{
1015 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1016 struct bp_transmitter_control cntl = { 0 };
1017 enum bp_result result;
1018
1019 /* Enable the PHY */
1020
1021 /* number_of_lanes is used for pixel clock adjust,
1022 * but it's not passed to asic_control.
1023 * We need to set number of lanes manually.
1024 */
1025 enc1_configure_encoder(enc10, link_settings);
1026
1027 cntl.action = TRANSMITTER_CONTROL_ENABLE;
1028 cntl.engine_id = ENGINE_ID_UNKNOWN;
1029 cntl.transmitter = enc10->base.transmitter;
1030 cntl.pll_id = clock_source;
1031 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
1032 cntl.lanes_number = link_settings->lane_count;
1033 cntl.hpd_sel = enc10->base.hpd_source;
1034 cntl.pixel_clock = link_settings->link_rate
1035 * LINK_RATE_REF_FREQ_IN_KHZ;
1036 /* TODO: check if undefined works */
1037 cntl.color_depth = COLOR_DEPTH_UNDEFINED;
1038
1039 result = link_transmitter_control(enc10, cntl: &cntl);
1040
1041 if (result != BP_RESULT_OK) {
1042 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1043 __func__);
1044 BREAK_TO_DEBUGGER();
1045 }
1046}
1047/*
1048 * @brief
1049 * Disable transmitter and its encoder
1050 */
1051void dcn10_link_encoder_disable_output(
1052 struct link_encoder *enc,
1053 enum signal_type signal)
1054{
1055 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1056 struct bp_transmitter_control cntl = { 0 };
1057 enum bp_result result;
1058
1059 if (enc->funcs->is_dig_enabled && !enc->funcs->is_dig_enabled(enc)) {
1060 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */
1061 /*in DP_Alt_No_Connect case, we turn off the dig already,
1062 after excuation the PHY w/a sequence, not allow touch PHY any more*/
1063 return;
1064 }
1065 /* Power-down RX and disable GPU PHY should be paired.
1066 * Disabling PHY without powering down RX may cause
1067 * symbol lock loss, on which we will get DP Sink interrupt.
1068 */
1069
1070 /* There is a case for the DP active dongles
1071 * where we want to disable the PHY but keep RX powered,
1072 * for those we need to ignore DP Sink interrupt
1073 * by checking lane count that has been set
1074 * on the last do_enable_output().
1075 */
1076
1077 /* disable transmitter */
1078 cntl.action = TRANSMITTER_CONTROL_DISABLE;
1079 cntl.transmitter = enc10->base.transmitter;
1080 cntl.hpd_sel = enc10->base.hpd_source;
1081 cntl.signal = signal;
1082 cntl.connector_obj_id = enc10->base.connector;
1083
1084 result = link_transmitter_control(enc10, cntl: &cntl);
1085
1086 if (result != BP_RESULT_OK) {
1087 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n",
1088 __func__);
1089 BREAK_TO_DEBUGGER();
1090 return;
1091 }
1092
1093 /* disable encoder */
1094 if (dc_is_dp_signal(signal))
1095 link_encoder_disable(enc10);
1096}
1097
1098void dcn10_link_encoder_dp_set_lane_settings(
1099 struct link_encoder *enc,
1100 const struct dc_link_settings *link_settings,
1101 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
1102{
1103 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1104 union dpcd_training_lane_set training_lane_set = { { 0 } };
1105 int32_t lane = 0;
1106 struct bp_transmitter_control cntl = { 0 };
1107
1108 if (!link_settings) {
1109 BREAK_TO_DEBUGGER();
1110 return;
1111 }
1112
1113 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
1114 cntl.transmitter = enc10->base.transmitter;
1115 cntl.connector_obj_id = enc10->base.connector;
1116 cntl.lanes_number = link_settings->lane_count;
1117 cntl.hpd_sel = enc10->base.hpd_source;
1118 cntl.pixel_clock = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1119
1120 for (lane = 0; lane < link_settings->lane_count; lane++) {
1121 /* translate lane settings */
1122
1123 training_lane_set.bits.VOLTAGE_SWING_SET =
1124 lane_settings[lane].VOLTAGE_SWING;
1125 training_lane_set.bits.PRE_EMPHASIS_SET =
1126 lane_settings[lane].PRE_EMPHASIS;
1127
1128 /* post cursor 2 setting only applies to HBR2 link rate */
1129 if (link_settings->link_rate == LINK_RATE_HIGH2) {
1130 /* this is passed to VBIOS
1131 * to program post cursor 2 level
1132 */
1133 training_lane_set.bits.POST_CURSOR2_SET =
1134 lane_settings[lane].POST_CURSOR2;
1135 }
1136
1137 cntl.lane_select = lane;
1138 cntl.lane_settings = training_lane_set.raw;
1139
1140 /* call VBIOS table to set voltage swing and pre-emphasis */
1141 link_transmitter_control(enc10, cntl: &cntl);
1142 }
1143}
1144
1145/* set DP PHY test and training patterns */
1146void dcn10_link_encoder_dp_set_phy_pattern(
1147 struct link_encoder *enc,
1148 const struct encoder_set_dp_phy_pattern_param *param)
1149{
1150 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1151
1152 switch (param->dp_phy_pattern) {
1153 case DP_TEST_PATTERN_TRAINING_PATTERN1:
1154 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, index: 0);
1155 break;
1156 case DP_TEST_PATTERN_TRAINING_PATTERN2:
1157 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, index: 1);
1158 break;
1159 case DP_TEST_PATTERN_TRAINING_PATTERN3:
1160 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, index: 2);
1161 break;
1162 case DP_TEST_PATTERN_TRAINING_PATTERN4:
1163 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, index: 3);
1164 break;
1165 case DP_TEST_PATTERN_D102:
1166 set_dp_phy_pattern_d102(enc10);
1167 break;
1168 case DP_TEST_PATTERN_SYMBOL_ERROR:
1169 set_dp_phy_pattern_symbol_error(enc10);
1170 break;
1171 case DP_TEST_PATTERN_PRBS7:
1172 set_dp_phy_pattern_prbs7(enc10);
1173 break;
1174 case DP_TEST_PATTERN_80BIT_CUSTOM:
1175 set_dp_phy_pattern_80bit_custom(
1176 enc10, pattern: param->custom_pattern);
1177 break;
1178 case DP_TEST_PATTERN_CP2520_1:
1179 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, cp2520_pattern: 1);
1180 break;
1181 case DP_TEST_PATTERN_CP2520_2:
1182 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, cp2520_pattern: 2);
1183 break;
1184 case DP_TEST_PATTERN_CP2520_3:
1185 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, cp2520_pattern: 3);
1186 break;
1187 case DP_TEST_PATTERN_VIDEO_MODE: {
1188 set_dp_phy_pattern_passthrough_mode(
1189 enc10, panel_mode: param->dp_panel_mode);
1190 break;
1191 }
1192
1193 default:
1194 /* invalid phy pattern */
1195 ASSERT_CRITICAL(false);
1196 break;
1197 }
1198}
1199
1200static void fill_stream_allocation_row_info(
1201 const struct link_mst_stream_allocation *stream_allocation,
1202 uint32_t *src,
1203 uint32_t *slots)
1204{
1205 const struct stream_encoder *stream_enc = stream_allocation->stream_enc;
1206
1207 if (stream_enc) {
1208 *src = stream_enc->id;
1209 *slots = stream_allocation->slot_count;
1210 } else {
1211 *src = 0;
1212 *slots = 0;
1213 }
1214}
1215
1216/* programs DP MST VC payload allocation */
1217void dcn10_link_encoder_update_mst_stream_allocation_table(
1218 struct link_encoder *enc,
1219 const struct link_mst_stream_allocation_table *table)
1220{
1221 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1222 uint32_t value1 = 0;
1223 uint32_t value2 = 0;
1224 uint32_t slots = 0;
1225 uint32_t src = 0;
1226 uint32_t retries = 0;
1227
1228 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/
1229
1230 /* --- Set MSE Stream Attribute -
1231 * Setup VC Payload Table on Tx Side,
1232 * Issue allocation change trigger
1233 * to commit payload on both tx and rx side
1234 */
1235
1236 /* we should clean-up table each time */
1237
1238 if (table->stream_count >= 1) {
1239 fill_stream_allocation_row_info(
1240 stream_allocation: &table->stream_allocations[0],
1241 src: &src,
1242 slots: &slots);
1243 } else {
1244 src = 0;
1245 slots = 0;
1246 }
1247
1248 REG_UPDATE_2(DP_MSE_SAT0,
1249 DP_MSE_SAT_SRC0, src,
1250 DP_MSE_SAT_SLOT_COUNT0, slots);
1251
1252 if (table->stream_count >= 2) {
1253 fill_stream_allocation_row_info(
1254 stream_allocation: &table->stream_allocations[1],
1255 src: &src,
1256 slots: &slots);
1257 } else {
1258 src = 0;
1259 slots = 0;
1260 }
1261
1262 REG_UPDATE_2(DP_MSE_SAT0,
1263 DP_MSE_SAT_SRC1, src,
1264 DP_MSE_SAT_SLOT_COUNT1, slots);
1265
1266 if (table->stream_count >= 3) {
1267 fill_stream_allocation_row_info(
1268 stream_allocation: &table->stream_allocations[2],
1269 src: &src,
1270 slots: &slots);
1271 } else {
1272 src = 0;
1273 slots = 0;
1274 }
1275
1276 REG_UPDATE_2(DP_MSE_SAT1,
1277 DP_MSE_SAT_SRC2, src,
1278 DP_MSE_SAT_SLOT_COUNT2, slots);
1279
1280 if (table->stream_count >= 4) {
1281 fill_stream_allocation_row_info(
1282 stream_allocation: &table->stream_allocations[3],
1283 src: &src,
1284 slots: &slots);
1285 } else {
1286 src = 0;
1287 slots = 0;
1288 }
1289
1290 REG_UPDATE_2(DP_MSE_SAT1,
1291 DP_MSE_SAT_SRC3, src,
1292 DP_MSE_SAT_SLOT_COUNT3, slots);
1293
1294 /* --- wait for transaction finish */
1295
1296 /* send allocation change trigger (ACT) ?
1297 * this step first sends the ACT,
1298 * then double buffers the SAT into the hardware
1299 * making the new allocation active on the DP MST mode link
1300 */
1301
1302 /* DP_MSE_SAT_UPDATE:
1303 * 0 - No Action
1304 * 1 - Update SAT with trigger
1305 * 2 - Update SAT without trigger
1306 */
1307 REG_UPDATE(DP_MSE_SAT_UPDATE,
1308 DP_MSE_SAT_UPDATE, 1);
1309
1310 /* wait for update to complete
1311 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0)
1312 * then wait for the transmission
1313 * of at least 16 MTP headers on immediate local link.
1314 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0
1315 * a value of 1 indicates that DP MST mode
1316 * is in the 16 MTP keepout region after a VC has been added.
1317 * MST stream bandwidth (VC rate) can be configured
1318 * after this bit is cleared
1319 */
1320 do {
1321 udelay(10);
1322
1323 REG_READ(DP_MSE_SAT_UPDATE);
1324
1325 REG_GET(DP_MSE_SAT_UPDATE,
1326 DP_MSE_SAT_UPDATE, &value1);
1327
1328 REG_GET(DP_MSE_SAT_UPDATE,
1329 DP_MSE_16_MTP_KEEPOUT, &value2);
1330
1331 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */
1332 if (!value1 && !value2)
1333 break;
1334 ++retries;
1335 } while (retries < DP_MST_UPDATE_MAX_RETRY);
1336}
1337
1338void dcn10_link_encoder_connect_dig_be_to_fe(
1339 struct link_encoder *enc,
1340 enum engine_id engine,
1341 bool connect)
1342{
1343 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1344 uint32_t field;
1345
1346 if (engine != ENGINE_ID_UNKNOWN) {
1347
1348 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);
1349
1350 if (connect)
1351 field |= get_frontend_source(engine);
1352 else
1353 field &= ~get_frontend_source(engine);
1354
1355 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field);
1356 }
1357}
1358
1359
1360#define HPD_REG(reg)\
1361 (enc10->hpd_regs->reg)
1362
1363#define HPD_REG_READ(reg_name) \
1364 dm_read_reg(CTX, HPD_REG(reg_name))
1365
1366#define HPD_REG_UPDATE_N(reg_name, n, ...) \
1367 generic_reg_update_ex(CTX, \
1368 HPD_REG(reg_name), \
1369 n, __VA_ARGS__)
1370
1371#define HPD_REG_UPDATE(reg_name, field, val) \
1372 HPD_REG_UPDATE_N(reg_name, 1, \
1373 FN(reg_name, field), val)
1374
1375void dcn10_link_encoder_enable_hpd(struct link_encoder *enc)
1376{
1377 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1378
1379 HPD_REG_UPDATE(DC_HPD_CONTROL,
1380 DC_HPD_EN, 1);
1381}
1382
1383void dcn10_link_encoder_disable_hpd(struct link_encoder *enc)
1384{
1385 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1386
1387 HPD_REG_UPDATE(DC_HPD_CONTROL,
1388 DC_HPD_EN, 0);
1389}
1390
1391#define AUX_REG(reg)\
1392 (enc10->aux_regs->reg)
1393
1394#define AUX_REG_READ(reg_name) \
1395 dm_read_reg(CTX, AUX_REG(reg_name))
1396
1397#define AUX_REG_UPDATE_N(reg_name, n, ...) \
1398 generic_reg_update_ex(CTX, \
1399 AUX_REG(reg_name), \
1400 n, __VA_ARGS__)
1401
1402#define AUX_REG_UPDATE(reg_name, field, val) \
1403 AUX_REG_UPDATE_N(reg_name, 1, \
1404 FN(reg_name, field), val)
1405
1406#define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \
1407 AUX_REG_UPDATE_N(reg, 2,\
1408 FN(reg, f1), v1,\
1409 FN(reg, f2), v2)
1410
1411void dcn10_aux_initialize(struct dcn10_link_encoder *enc10)
1412{
1413 enum hpd_source_id hpd_source = enc10->base.hpd_source;
1414
1415 AUX_REG_UPDATE_2(AUX_CONTROL,
1416 AUX_HPD_SEL, hpd_source,
1417 AUX_LS_READ_EN, 0);
1418
1419 /* 1/4 window (the maximum allowed) */
1420 AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0,
1421 AUX_RX_RECEIVE_WINDOW, 0);
1422}
1423
1424enum signal_type dcn10_get_dig_mode(
1425 struct link_encoder *enc)
1426{
1427 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
1428 uint32_t value;
1429 REG_GET(DIG_BE_CNTL, DIG_MODE, &value);
1430 switch (value) {
1431 case 1:
1432 return SIGNAL_TYPE_DISPLAY_PORT;
1433 case 2:
1434 return SIGNAL_TYPE_DVI_SINGLE_LINK;
1435 case 3:
1436 return SIGNAL_TYPE_HDMI_TYPE_A;
1437 case 5:
1438 return SIGNAL_TYPE_DISPLAY_PORT_MST;
1439 default:
1440 return SIGNAL_TYPE_NONE;
1441 }
1442 return SIGNAL_TYPE_NONE;
1443}
1444
1445void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
1446 struct dc_link_settings *link_settings)
1447{
1448 /* Set Default link settings */
1449 struct dc_link_settings max_link_cap = {LANE_COUNT_FOUR, LINK_RATE_HIGH,
1450 LINK_SPREAD_05_DOWNSPREAD_30KHZ, false, 0};
1451
1452 /* Higher link settings based on feature supported */
1453 if (enc->features.flags.bits.IS_HBR2_CAPABLE)
1454 max_link_cap.link_rate = LINK_RATE_HIGH2;
1455
1456 if (enc->features.flags.bits.IS_HBR3_CAPABLE)
1457 max_link_cap.link_rate = LINK_RATE_HIGH3;
1458
1459 if (enc->features.flags.bits.IS_UHBR10_CAPABLE)
1460 max_link_cap.link_rate = LINK_RATE_UHBR10;
1461
1462 if (enc->features.flags.bits.IS_UHBR13_5_CAPABLE)
1463 max_link_cap.link_rate = LINK_RATE_UHBR13_5;
1464
1465 if (enc->features.flags.bits.IS_UHBR20_CAPABLE)
1466 max_link_cap.link_rate = LINK_RATE_UHBR20;
1467
1468 *link_settings = max_link_cap;
1469}
1470

source code of linux/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c