1 | /* |
2 | * Copyright 2012-17 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef __DC_MEM_INPUT_DCN20_H__ |
27 | #define __DC_MEM_INPUT_DCN20_H__ |
28 | |
29 | #include "../dcn10/dcn10_hubp.h" |
30 | |
31 | #define TO_DCN20_HUBP(hubp)\ |
32 | container_of(hubp, struct dcn20_hubp, base) |
33 | |
34 | #define HUBP_REG_LIST_DCN2_COMMON(id)\ |
35 | HUBP_REG_LIST_DCN(id),\ |
36 | HUBP_REG_LIST_DCN_VM(id),\ |
37 | SRI(PREFETCH_SETTINGS, HUBPREQ, id),\ |
38 | SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\ |
39 | SRI(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, HUBPREQ, id),\ |
40 | SRI(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, HUBPREQ, id),\ |
41 | SRI(CURSOR_SETTINGS, HUBPREQ, id), \ |
42 | SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \ |
43 | SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \ |
44 | SRI(CURSOR_SIZE, CURSOR0_, id), \ |
45 | SRI(CURSOR_CONTROL, CURSOR0_, id), \ |
46 | SRI(CURSOR_POSITION, CURSOR0_, id), \ |
47 | SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \ |
48 | SRI(CURSOR_DST_OFFSET, CURSOR0_, id), \ |
49 | SRI(DMDATA_ADDRESS_HIGH, CURSOR0_, id), \ |
50 | SRI(DMDATA_ADDRESS_LOW, CURSOR0_, id), \ |
51 | SRI(DMDATA_CNTL, CURSOR0_, id), \ |
52 | SRI(DMDATA_SW_CNTL, CURSOR0_, id), \ |
53 | SRI(DMDATA_QOS_CNTL, CURSOR0_, id), \ |
54 | SRI(DMDATA_SW_DATA, CURSOR0_, id), \ |
55 | SRI(DMDATA_STATUS, CURSOR0_, id),\ |
56 | SRI(FLIP_PARAMETERS_0, HUBPREQ, id),\ |
57 | SRI(FLIP_PARAMETERS_1, HUBPREQ, id),\ |
58 | SRI(FLIP_PARAMETERS_2, HUBPREQ, id),\ |
59 | SRI(DCN_CUR1_TTU_CNTL0, HUBPREQ, id),\ |
60 | SRI(DCN_CUR1_TTU_CNTL1, HUBPREQ, id),\ |
61 | SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \ |
62 | SRI(VMID_SETTINGS_0, HUBPREQ, id) |
63 | |
64 | #define HUBP_REG_LIST_DCN20(id)\ |
65 | HUBP_REG_LIST_DCN2_COMMON(id),\ |
66 | SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ |
67 | SR(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB) |
68 | |
69 | #define HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh)\ |
70 | HUBP_MASK_SH_LIST_DCN_SHARE_COMMON(mask_sh),\ |
71 | HUBP_MASK_SH_LIST_DCN_VM(mask_sh),\ |
72 | HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, ROTATION_ANGLE, mask_sh),\ |
73 | HUBP_SF(HUBP0_DCSURF_SURFACE_CONFIG, H_MIRROR_EN, mask_sh),\ |
74 | HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, DST_Y_PREFETCH, mask_sh),\ |
75 | HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS, VRATIO_PREFETCH, mask_sh),\ |
76 | HUBP_SF(HUBPREQ0_PREFETCH_SETTINGS_C, VRATIO_PREFETCH_C, mask_sh),\ |
77 | HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR, MC_VM_SYSTEM_APERTURE_LOW_ADDR, mask_sh),\ |
78 | HUBP_SF(HUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mask_sh),\ |
79 | HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \ |
80 | HUBP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \ |
81 | HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH, CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \ |
82 | HUBP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS, mask_sh), \ |
83 | HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \ |
84 | HUBP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \ |
85 | HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \ |
86 | HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \ |
87 | HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \ |
88 | HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \ |
89 | HUBP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \ |
90 | HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \ |
91 | HUBP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \ |
92 | HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \ |
93 | HUBP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \ |
94 | HUBP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \ |
95 | HUBP_SF(CURSOR0_0_DMDATA_ADDRESS_HIGH, DMDATA_ADDRESS_HIGH, mask_sh), \ |
96 | HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_MODE, mask_sh), \ |
97 | HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_UPDATED, mask_sh), \ |
98 | HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_REPEAT, mask_sh), \ |
99 | HUBP_SF(CURSOR0_0_DMDATA_CNTL, DMDATA_SIZE, mask_sh), \ |
100 | HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_UPDATED, mask_sh), \ |
101 | HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_REPEAT, mask_sh), \ |
102 | HUBP_SF(CURSOR0_0_DMDATA_SW_CNTL, DMDATA_SW_SIZE, mask_sh), \ |
103 | HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_MODE, mask_sh), \ |
104 | HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_QOS_LEVEL, mask_sh), \ |
105 | HUBP_SF(CURSOR0_0_DMDATA_QOS_CNTL, DMDATA_DL_DELTA, mask_sh), \ |
106 | HUBP_SF(CURSOR0_0_DMDATA_STATUS, DMDATA_DONE, mask_sh),\ |
107 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_VM_FLIP, mask_sh),\ |
108 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_0, DST_Y_PER_ROW_FLIP, mask_sh),\ |
109 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_1, REFCYC_PER_PTE_GROUP_FLIP_L, mask_sh),\ |
110 | HUBP_SF(HUBPREQ0_FLIP_PARAMETERS_2, REFCYC_PER_META_CHUNK_FLIP_L, mask_sh),\ |
111 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, mask_sh),\ |
112 | HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_DISABLE_STOP_DATA_DURING_VM, mask_sh),\ |
113 | HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL, HUBPREQ_MASTER_UPDATE_LOCK_STATUS, mask_sh),\ |
114 | HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, mask_sh),\ |
115 | HUBP_SF(HUBPREQ0_DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, mask_sh),\ |
116 | HUBP_SF(HUBPREQ0_VMID_SETTINGS_0, VMID, mask_sh) |
117 | |
118 | /*DCN2.x and DCN1.x*/ |
119 | #define HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh)\ |
120 | HUBP_MASK_SH_LIST_DCN2_SHARE_COMMON(mask_sh),\ |
121 | HUBP_SF(HUBP0_DCSURF_TILING_CONFIG, RB_ALIGNED, mask_sh),\ |
122 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG, MPTE_GROUP_SIZE, mask_sh),\ |
123 | HUBP_SF(HUBP0_DCHUBP_REQ_SIZE_CONFIG_C, MPTE_GROUP_SIZE_C, mask_sh) |
124 | |
125 | /*DCN2.0 specific*/ |
126 | #define HUBP_MASK_SH_LIST_DCN20(mask_sh)\ |
127 | HUBP_MASK_SH_LIST_DCN2_COMMON(mask_sh),\ |
128 | HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, mask_sh),\ |
129 | HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mask_sh),\ |
130 | HUBP_SF(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mask_sh) |
131 | |
132 | /*DCN2.x */ |
133 | #define DCN2_HUBP_REG_COMMON_VARIABLE_LIST \ |
134 | HUBP_COMMON_REG_VARIABLE_LIST; \ |
135 | uint32_t DMDATA_ADDRESS_HIGH; \ |
136 | uint32_t DMDATA_ADDRESS_LOW; \ |
137 | uint32_t DMDATA_CNTL; \ |
138 | uint32_t DMDATA_SW_CNTL; \ |
139 | uint32_t DMDATA_QOS_CNTL; \ |
140 | uint32_t DMDATA_SW_DATA; \ |
141 | uint32_t DMDATA_STATUS;\ |
142 | uint32_t DCSURF_FLIP_CONTROL2;\ |
143 | uint32_t FLIP_PARAMETERS_0;\ |
144 | uint32_t FLIP_PARAMETERS_1;\ |
145 | uint32_t FLIP_PARAMETERS_2;\ |
146 | uint32_t DCN_CUR1_TTU_CNTL0;\ |
147 | uint32_t DCN_CUR1_TTU_CNTL1;\ |
148 | uint32_t VMID_SETTINGS_0 |
149 | |
150 | |
151 | #define DCN21_HUBP_REG_COMMON_VARIABLE_LIST \ |
152 | DCN2_HUBP_REG_COMMON_VARIABLE_LIST; \ |
153 | uint32_t FLIP_PARAMETERS_3;\ |
154 | uint32_t FLIP_PARAMETERS_4;\ |
155 | uint32_t FLIP_PARAMETERS_5;\ |
156 | uint32_t FLIP_PARAMETERS_6;\ |
157 | uint32_t VBLANK_PARAMETERS_5;\ |
158 | uint32_t VBLANK_PARAMETERS_6 |
159 | |
160 | #define DCN30_HUBP_REG_COMMON_VARIABLE_LIST \ |
161 | DCN21_HUBP_REG_COMMON_VARIABLE_LIST;\ |
162 | uint32_t DCN_DMDATA_VM_CNTL |
163 | |
164 | #define DCN32_HUBP_REG_COMMON_VARIABLE_LIST \ |
165 | DCN30_HUBP_REG_COMMON_VARIABLE_LIST;\ |
166 | uint32_t DCHUBP_MALL_CONFIG;\ |
167 | uint32_t DCHUBP_VMPG_CONFIG;\ |
168 | uint32_t UCLK_PSTATE_FORCE |
169 | |
170 | #define DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type) \ |
171 | DCN_HUBP_REG_FIELD_BASE_LIST(type); \ |
172 | type DMDATA_ADDRESS_HIGH;\ |
173 | type DMDATA_MODE;\ |
174 | type DMDATA_UPDATED;\ |
175 | type DMDATA_REPEAT;\ |
176 | type DMDATA_SIZE;\ |
177 | type DMDATA_SW_UPDATED;\ |
178 | type DMDATA_SW_REPEAT;\ |
179 | type DMDATA_SW_SIZE;\ |
180 | type DMDATA_QOS_MODE;\ |
181 | type DMDATA_QOS_LEVEL;\ |
182 | type DMDATA_DL_DELTA;\ |
183 | type DMDATA_DONE;\ |
184 | type DST_Y_PER_VM_FLIP;\ |
185 | type DST_Y_PER_ROW_FLIP;\ |
186 | type REFCYC_PER_PTE_GROUP_FLIP_L;\ |
187 | type REFCYC_PER_META_CHUNK_FLIP_L;\ |
188 | type HUBP_VREADY_AT_OR_AFTER_VSYNC;\ |
189 | type HUBP_DISABLE_STOP_DATA_DURING_VM;\ |
190 | type HUBPREQ_MASTER_UPDATE_LOCK_STATUS;\ |
191 | type SURFACE_GSL_ENABLE;\ |
192 | type SURFACE_TRIPLE_BUFFER_ENABLE;\ |
193 | type VMID |
194 | |
195 | #define DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type) \ |
196 | DCN2_HUBP_REG_FIELD_VARIABLE_LIST(type);\ |
197 | type REFCYC_PER_VM_GROUP_FLIP;\ |
198 | type REFCYC_PER_VM_REQ_FLIP;\ |
199 | type REFCYC_PER_VM_GROUP_VBLANK;\ |
200 | type REFCYC_PER_VM_REQ_VBLANK;\ |
201 | type REFCYC_PER_PTE_GROUP_FLIP_C; \ |
202 | type REFCYC_PER_META_CHUNK_FLIP_C; \ |
203 | type VM_GROUP_SIZE |
204 | |
205 | #define DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type) \ |
206 | DCN21_HUBP_REG_FIELD_VARIABLE_LIST(type);\ |
207 | type PRIMARY_SURFACE_DCC_IND_BLK;\ |
208 | type SECONDARY_SURFACE_DCC_IND_BLK;\ |
209 | type PRIMARY_SURFACE_DCC_IND_BLK_C;\ |
210 | type SECONDARY_SURFACE_DCC_IND_BLK_C;\ |
211 | type ALPHA_PLANE_EN;\ |
212 | type REFCYC_PER_VM_DMDATA;\ |
213 | type DMDATA_VM_FAULT_STATUS;\ |
214 | type DMDATA_VM_FAULT_STATUS_CLEAR; \ |
215 | type DMDATA_VM_UNDERFLOW_STATUS;\ |
216 | type DMDATA_VM_LATE_STATUS;\ |
217 | type DMDATA_VM_UNDERFLOW_STATUS_CLEAR; \ |
218 | type DMDATA_VM_DONE; \ |
219 | type CROSSBAR_SRC_Y_G; \ |
220 | type CROSSBAR_SRC_ALPHA; \ |
221 | type PACK_3TO2_ELEMENT_DISABLE; \ |
222 | type ROW_TTU_MODE; \ |
223 | type NUM_PKRS |
224 | |
225 | #define DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type) \ |
226 | DCN30_HUBP_REG_FIELD_VARIABLE_LIST(type);\ |
227 | type HUBP_UNBOUNDED_REQ_MODE;\ |
228 | type CURSOR_REQ_MODE;\ |
229 | type HUBP_SOFT_RESET |
230 | |
231 | #define DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type) \ |
232 | DCN31_HUBP_REG_FIELD_VARIABLE_LIST(type);\ |
233 | type USE_MALL_SEL; \ |
234 | type USE_MALL_FOR_CURSOR;\ |
235 | type VMPG_SIZE; \ |
236 | type PTE_BUFFER_MODE; \ |
237 | type BIGK_FRAGMENT_SIZE; \ |
238 | type FORCE_ONE_ROW_FOR_FRAME; \ |
239 | type DATA_UCLK_PSTATE_FORCE_EN; \ |
240 | type DATA_UCLK_PSTATE_FORCE_VALUE; \ |
241 | type CURSOR_UCLK_PSTATE_FORCE_EN; \ |
242 | type CURSOR_UCLK_PSTATE_FORCE_VALUE |
243 | |
244 | struct dcn_hubp2_registers { |
245 | DCN32_HUBP_REG_COMMON_VARIABLE_LIST; |
246 | }; |
247 | |
248 | struct dcn_hubp2_shift { |
249 | DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t); |
250 | }; |
251 | |
252 | struct dcn_hubp2_mask { |
253 | DCN32_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t); |
254 | }; |
255 | |
256 | struct dcn20_hubp { |
257 | struct hubp base; |
258 | struct dcn_hubp_state state; |
259 | const struct dcn_hubp2_registers *hubp_regs; |
260 | const struct dcn_hubp2_shift *hubp_shift; |
261 | const struct dcn_hubp2_mask *hubp_mask; |
262 | }; |
263 | |
264 | bool hubp2_construct( |
265 | struct dcn20_hubp *hubp2, |
266 | struct dc_context *ctx, |
267 | uint32_t inst, |
268 | const struct dcn_hubp2_registers *hubp_regs, |
269 | const struct dcn_hubp2_shift *hubp_shift, |
270 | const struct dcn_hubp2_mask *hubp_mask); |
271 | |
272 | void hubp2_setup_interdependent( |
273 | struct hubp *hubp, |
274 | struct _vcs_dpi_display_dlg_regs_st *dlg_attr, |
275 | struct _vcs_dpi_display_ttu_regs_st *ttu_attr); |
276 | |
277 | void hubp2_vready_at_or_After_vsync(struct hubp *hubp, |
278 | struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); |
279 | |
280 | void hubp2_cursor_set_attributes( |
281 | struct hubp *hubp, |
282 | const struct dc_cursor_attributes *attr); |
283 | |
284 | void hubp2_set_vm_system_aperture_settings(struct hubp *hubp, |
285 | struct vm_system_aperture_param *apt); |
286 | |
287 | enum cursor_lines_per_chunk hubp2_get_lines_per_chunk( |
288 | unsigned int cursor_width, |
289 | enum dc_cursor_color_format cursor_mode); |
290 | |
291 | void hubp2_dmdata_set_attributes( |
292 | struct hubp *hubp, |
293 | const struct dc_dmdata_attributes *attr); |
294 | |
295 | void hubp2_dmdata_load( |
296 | struct hubp *hubp, |
297 | uint32_t dmdata_sw_size, |
298 | const uint32_t *dmdata_sw_data); |
299 | |
300 | bool hubp2_dmdata_status_done(struct hubp *hubp); |
301 | |
302 | void hubp2_enable_triplebuffer( |
303 | struct hubp *hubp, |
304 | bool enable); |
305 | |
306 | bool hubp2_is_triplebuffer_enabled( |
307 | struct hubp *hubp); |
308 | |
309 | void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable); |
310 | |
311 | void hubp2_program_deadline( |
312 | struct hubp *hubp, |
313 | struct _vcs_dpi_display_dlg_regs_st *dlg_attr, |
314 | struct _vcs_dpi_display_ttu_regs_st *ttu_attr); |
315 | |
316 | bool hubp2_program_surface_flip_and_addr( |
317 | struct hubp *hubp, |
318 | const struct dc_plane_address *address, |
319 | bool flip_immediate); |
320 | |
321 | void hubp2_dcc_control(struct hubp *hubp, bool enable, |
322 | enum hubp_ind_block_size independent_64b_blks); |
323 | |
324 | void hubp2_program_size( |
325 | struct hubp *hubp, |
326 | enum surface_pixel_format format, |
327 | const struct plane_size *plane_size, |
328 | struct dc_plane_dcc_param *dcc); |
329 | |
330 | void hubp2_program_rotation( |
331 | struct hubp *hubp, |
332 | enum dc_rotation_angle rotation, |
333 | bool horizontal_mirror); |
334 | |
335 | void hubp2_program_pixel_format( |
336 | struct hubp *hubp, |
337 | enum surface_pixel_format format); |
338 | |
339 | void hubp2_program_surface_config( |
340 | struct hubp *hubp, |
341 | enum surface_pixel_format format, |
342 | union dc_tiling_info *tiling_info, |
343 | struct plane_size *plane_size, |
344 | enum dc_rotation_angle rotation, |
345 | struct dc_plane_dcc_param *dcc, |
346 | bool horizontal_mirror, |
347 | unsigned int compat_level); |
348 | |
349 | bool hubp2_is_flip_pending(struct hubp *hubp); |
350 | |
351 | void hubp2_set_blank(struct hubp *hubp, bool blank); |
352 | void hubp2_set_blank_regs(struct hubp *hubp, bool blank); |
353 | |
354 | void hubp2_cursor_set_position( |
355 | struct hubp *hubp, |
356 | const struct dc_cursor_position *pos, |
357 | const struct dc_cursor_mi_param *param); |
358 | |
359 | void hubp2_clk_cntl(struct hubp *hubp, bool enable); |
360 | |
361 | void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst); |
362 | |
363 | void hubp2_clear_underflow(struct hubp *hubp); |
364 | |
365 | void hubp2_read_state_common(struct hubp *hubp); |
366 | |
367 | void hubp2_read_state(struct hubp *hubp); |
368 | |
369 | #endif /* __DC_MEM_INPUT_DCN20_H__ */ |
370 | |
371 | |
372 | |