1 | /* |
2 | * Copyright 2020 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef __DCN30_DCCG_H__ |
27 | #define __DCN30_DCCG_H__ |
28 | |
29 | #include "dcn20/dcn20_dccg.h" |
30 | |
31 | |
32 | #define DCCG_REG_LIST_DCN3AG() \ |
33 | DCCG_COMMON_REG_LIST_DCN_BASE(),\ |
34 | SR(PHYASYMCLK_CLOCK_CNTL),\ |
35 | SR(PHYBSYMCLK_CLOCK_CNTL),\ |
36 | SR(PHYCSYMCLK_CLOCK_CNTL) |
37 | |
38 | |
39 | #define DCCG_REG_LIST_DCN30() \ |
40 | DCCG_REG_LIST_DCN2(),\ |
41 | DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ |
42 | DCCG_SRII(PIXEL_RATE_CNTL, OTG, 3),\ |
43 | DCCG_SRII(PIXEL_RATE_CNTL, OTG, 4),\ |
44 | DCCG_SRII(PIXEL_RATE_CNTL, OTG, 5),\ |
45 | SR(PHYASYMCLK_CLOCK_CNTL),\ |
46 | SR(PHYBSYMCLK_CLOCK_CNTL),\ |
47 | SR(PHYCSYMCLK_CLOCK_CNTL) |
48 | |
49 | #define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \ |
50 | DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\ |
51 | DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\ |
52 | DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\ |
53 | DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\ |
54 | DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\ |
55 | DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ |
56 | DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\ |
57 | DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\ |
58 | DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh) |
59 | |
60 | #define DCCG_MASK_SH_LIST_DCN3(mask_sh) \ |
61 | DCCG_MASK_SH_LIST_DCN2(mask_sh),\ |
62 | DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\ |
63 | DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\ |
64 | DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ |
65 | DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\ |
66 | DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\ |
67 | DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh),\ |
68 | |
69 | struct dccg *dccg3_create( |
70 | struct dc_context *ctx, |
71 | const struct dccg_registers *regs, |
72 | const struct dccg_shift *dccg_shift, |
73 | const struct dccg_mask *dccg_mask); |
74 | |
75 | struct dccg *dccg30_create( |
76 | struct dc_context *ctx, |
77 | const struct dccg_registers *regs, |
78 | const struct dccg_shift *dccg_shift, |
79 | const struct dccg_mask *dccg_mask); |
80 | |
81 | #endif //__DCN30_DCCG_H__ |
82 | |