1 | /* Copyright 2020 Advanced Micro Devices, Inc. |
2 | * |
3 | * Permission is hereby granted, free of charge, to any person obtaining a |
4 | * copy of this software and associated documentation files (the "Software"), |
5 | * to deal in the Software without restriction, including without limitation |
6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
7 | * and/or sell copies of the Software, and to permit persons to whom the |
8 | * Software is furnished to do so, subject to the following conditions: |
9 | * |
10 | * The above copyright notice and this permission notice shall be included in |
11 | * all copies or substantial portions of the Software. |
12 | * |
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
16 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
19 | * OTHER DEALINGS IN THE SOFTWARE. |
20 | * |
21 | * Authors: AMD |
22 | * |
23 | */ |
24 | #ifndef __DC_DWBC_DCN30_H__ |
25 | #define __DC_DWBC_DCN30_H__ |
26 | |
27 | #define TO_DCN30_DWBC(dwbc_base) \ |
28 | container_of(dwbc_base, struct dcn30_dwbc, base) |
29 | |
30 | #define DWBC_COMMON_REG_LIST_DCN30(inst) \ |
31 | SR(DWB_ENABLE_CLK_CTRL),\ |
32 | SR(DWB_MEM_PWR_CTRL),\ |
33 | SR(FC_MODE_CTRL),\ |
34 | SR(FC_FLOW_CTRL),\ |
35 | SR(FC_WINDOW_START),\ |
36 | SR(FC_WINDOW_SIZE),\ |
37 | SR(FC_SOURCE_SIZE),\ |
38 | SR(DWB_UPDATE_CTRL),\ |
39 | SR(DWB_CRC_CTRL),\ |
40 | SR(DWB_CRC_MASK_R_G),\ |
41 | SR(DWB_CRC_MASK_B_A),\ |
42 | SR(DWB_CRC_VAL_R_G),\ |
43 | SR(DWB_CRC_VAL_B_A),\ |
44 | SR(DWB_OUT_CTRL),\ |
45 | SR(DWB_MMHUBBUB_BACKPRESSURE_CNT_EN),\ |
46 | SR(DWB_MMHUBBUB_BACKPRESSURE_CNT),\ |
47 | SR(DWB_HOST_READ_CONTROL),\ |
48 | SR(DWB_SOFT_RESET),\ |
49 | SR(DWB_HDR_MULT_COEF),\ |
50 | SR(DWB_GAMUT_REMAP_MODE),\ |
51 | SR(DWB_GAMUT_REMAP_COEF_FORMAT),\ |
52 | SR(DWB_GAMUT_REMAPA_C11_C12),\ |
53 | SR(DWB_GAMUT_REMAPA_C13_C14),\ |
54 | SR(DWB_GAMUT_REMAPA_C21_C22),\ |
55 | SR(DWB_GAMUT_REMAPA_C23_C24),\ |
56 | SR(DWB_GAMUT_REMAPA_C31_C32),\ |
57 | SR(DWB_GAMUT_REMAPA_C33_C34),\ |
58 | SR(DWB_GAMUT_REMAPB_C11_C12),\ |
59 | SR(DWB_GAMUT_REMAPB_C13_C14),\ |
60 | SR(DWB_GAMUT_REMAPB_C21_C22),\ |
61 | SR(DWB_GAMUT_REMAPB_C23_C24),\ |
62 | SR(DWB_GAMUT_REMAPB_C31_C32),\ |
63 | SR(DWB_GAMUT_REMAPB_C33_C34),\ |
64 | SR(DWB_OGAM_CONTROL),\ |
65 | SR(DWB_OGAM_LUT_INDEX),\ |
66 | SR(DWB_OGAM_LUT_DATA),\ |
67 | SR(DWB_OGAM_LUT_CONTROL),\ |
68 | SR(DWB_OGAM_RAMA_START_CNTL_B),\ |
69 | SR(DWB_OGAM_RAMA_START_CNTL_G),\ |
70 | SR(DWB_OGAM_RAMA_START_CNTL_R),\ |
71 | SR(DWB_OGAM_RAMA_START_BASE_CNTL_B),\ |
72 | SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_B),\ |
73 | SR(DWB_OGAM_RAMA_START_BASE_CNTL_G),\ |
74 | SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_G),\ |
75 | SR(DWB_OGAM_RAMA_START_BASE_CNTL_R),\ |
76 | SR(DWB_OGAM_RAMA_START_SLOPE_CNTL_R),\ |
77 | SR(DWB_OGAM_RAMA_END_CNTL1_B),\ |
78 | SR(DWB_OGAM_RAMA_END_CNTL2_B),\ |
79 | SR(DWB_OGAM_RAMA_END_CNTL1_G),\ |
80 | SR(DWB_OGAM_RAMA_END_CNTL2_G),\ |
81 | SR(DWB_OGAM_RAMA_END_CNTL1_R),\ |
82 | SR(DWB_OGAM_RAMA_END_CNTL2_R),\ |
83 | SR(DWB_OGAM_RAMA_OFFSET_B),\ |
84 | SR(DWB_OGAM_RAMA_OFFSET_G),\ |
85 | SR(DWB_OGAM_RAMA_OFFSET_R),\ |
86 | SR(DWB_OGAM_RAMA_REGION_0_1),\ |
87 | SR(DWB_OGAM_RAMA_REGION_2_3),\ |
88 | SR(DWB_OGAM_RAMA_REGION_4_5),\ |
89 | SR(DWB_OGAM_RAMA_REGION_6_7),\ |
90 | SR(DWB_OGAM_RAMA_REGION_8_9),\ |
91 | SR(DWB_OGAM_RAMA_REGION_10_11),\ |
92 | SR(DWB_OGAM_RAMA_REGION_12_13),\ |
93 | SR(DWB_OGAM_RAMA_REGION_14_15),\ |
94 | SR(DWB_OGAM_RAMA_REGION_16_17),\ |
95 | SR(DWB_OGAM_RAMA_REGION_18_19),\ |
96 | SR(DWB_OGAM_RAMA_REGION_20_21),\ |
97 | SR(DWB_OGAM_RAMA_REGION_22_23),\ |
98 | SR(DWB_OGAM_RAMA_REGION_24_25),\ |
99 | SR(DWB_OGAM_RAMA_REGION_26_27),\ |
100 | SR(DWB_OGAM_RAMA_REGION_28_29),\ |
101 | SR(DWB_OGAM_RAMA_REGION_30_31),\ |
102 | SR(DWB_OGAM_RAMA_REGION_32_33),\ |
103 | SR(DWB_OGAM_RAMB_START_CNTL_B),\ |
104 | SR(DWB_OGAM_RAMB_START_CNTL_G),\ |
105 | SR(DWB_OGAM_RAMB_START_CNTL_R),\ |
106 | SR(DWB_OGAM_RAMB_START_BASE_CNTL_B),\ |
107 | SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_B),\ |
108 | SR(DWB_OGAM_RAMB_START_BASE_CNTL_G),\ |
109 | SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_G),\ |
110 | SR(DWB_OGAM_RAMB_START_BASE_CNTL_R),\ |
111 | SR(DWB_OGAM_RAMB_START_SLOPE_CNTL_R),\ |
112 | SR(DWB_OGAM_RAMB_END_CNTL1_B),\ |
113 | SR(DWB_OGAM_RAMB_END_CNTL2_B),\ |
114 | SR(DWB_OGAM_RAMB_END_CNTL1_G),\ |
115 | SR(DWB_OGAM_RAMB_END_CNTL2_G),\ |
116 | SR(DWB_OGAM_RAMB_END_CNTL1_R),\ |
117 | SR(DWB_OGAM_RAMB_END_CNTL2_R),\ |
118 | SR(DWB_OGAM_RAMB_OFFSET_B),\ |
119 | SR(DWB_OGAM_RAMB_OFFSET_G),\ |
120 | SR(DWB_OGAM_RAMB_OFFSET_R),\ |
121 | SR(DWB_OGAM_RAMB_REGION_0_1),\ |
122 | SR(DWB_OGAM_RAMB_REGION_2_3),\ |
123 | SR(DWB_OGAM_RAMB_REGION_4_5),\ |
124 | SR(DWB_OGAM_RAMB_REGION_6_7),\ |
125 | SR(DWB_OGAM_RAMB_REGION_8_9),\ |
126 | SR(DWB_OGAM_RAMB_REGION_10_11),\ |
127 | SR(DWB_OGAM_RAMB_REGION_12_13),\ |
128 | SR(DWB_OGAM_RAMB_REGION_14_15),\ |
129 | SR(DWB_OGAM_RAMB_REGION_16_17),\ |
130 | SR(DWB_OGAM_RAMB_REGION_18_19),\ |
131 | SR(DWB_OGAM_RAMB_REGION_20_21),\ |
132 | SR(DWB_OGAM_RAMB_REGION_22_23),\ |
133 | SR(DWB_OGAM_RAMB_REGION_24_25),\ |
134 | SR(DWB_OGAM_RAMB_REGION_26_27),\ |
135 | SR(DWB_OGAM_RAMB_REGION_28_29),\ |
136 | SR(DWB_OGAM_RAMB_REGION_30_31),\ |
137 | SR(DWB_OGAM_RAMB_REGION_32_33) |
138 | |
139 | |
140 | #define DWBC_COMMON_MASK_SH_LIST_DCN30(mask_sh) \ |
141 | SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_ENABLE, mask_sh),\ |
142 | SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DISPCLK_R_DWB_GATE_DIS, mask_sh),\ |
143 | SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DISPCLK_G_DWB_GATE_DIS, mask_sh),\ |
144 | SF_DWB2(DWB_ENABLE_CLK_CTRL, DWB_TOP, 0, DWB_TEST_CLK_SEL, mask_sh),\ |
145 | SF_DWB2(DWB_MEM_PWR_CTRL, DWB_TOP, 0, DWB_OGAM_LUT_MEM_PWR_FORCE, mask_sh),\ |
146 | SF_DWB2(DWB_MEM_PWR_CTRL, DWB_TOP, 0, DWB_OGAM_LUT_MEM_PWR_DIS, mask_sh),\ |
147 | SF_DWB2(DWB_MEM_PWR_CTRL, DWB_TOP, 0, DWB_OGAM_LUT_MEM_PWR_STATE, mask_sh),\ |
148 | SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_FRAME_CAPTURE_EN, mask_sh),\ |
149 | SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_FRAME_CAPTURE_RATE, mask_sh),\ |
150 | SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_WINDOW_CROP_EN, mask_sh),\ |
151 | SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_EYE_SELECTION, mask_sh),\ |
152 | SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_STEREO_EYE_POLARITY, mask_sh),\ |
153 | SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_NEW_CONTENT, mask_sh),\ |
154 | SF_DWB2(FC_MODE_CTRL, DWB_TOP, 0, FC_FRAME_CAPTURE_EN_CURRENT, mask_sh),\ |
155 | SF_DWB2(FC_FLOW_CTRL, DWB_TOP, 0, FC_FIRST_PIXEL_DELAY_COUNT, mask_sh),\ |
156 | SF_DWB2(FC_WINDOW_START, DWB_TOP, 0, FC_WINDOW_START_X, mask_sh),\ |
157 | SF_DWB2(FC_WINDOW_START, DWB_TOP, 0, FC_WINDOW_START_Y, mask_sh),\ |
158 | SF_DWB2(FC_WINDOW_SIZE, DWB_TOP, 0, FC_WINDOW_WIDTH, mask_sh),\ |
159 | SF_DWB2(FC_WINDOW_SIZE, DWB_TOP, 0, FC_WINDOW_HEIGHT, mask_sh),\ |
160 | SF_DWB2(FC_SOURCE_SIZE, DWB_TOP, 0, FC_SOURCE_WIDTH, mask_sh),\ |
161 | SF_DWB2(FC_SOURCE_SIZE, DWB_TOP, 0, FC_SOURCE_HEIGHT, mask_sh),\ |
162 | SF_DWB2(DWB_UPDATE_CTRL, DWB_TOP, 0, DWB_UPDATE_LOCK, mask_sh),\ |
163 | SF_DWB2(DWB_UPDATE_CTRL, DWB_TOP, 0, DWB_UPDATE_PENDING, mask_sh),\ |
164 | SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_EN, mask_sh),\ |
165 | SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_CONT_EN, mask_sh),\ |
166 | SF_DWB2(DWB_CRC_CTRL, DWB_TOP, 0, DWB_CRC_SRC_SEL, mask_sh),\ |
167 | SF_DWB2(DWB_CRC_MASK_R_G, DWB_TOP, 0, DWB_CRC_RED_MASK, mask_sh),\ |
168 | SF_DWB2(DWB_CRC_MASK_R_G, DWB_TOP, 0, DWB_CRC_GREEN_MASK, mask_sh),\ |
169 | SF_DWB2(DWB_CRC_MASK_B_A, DWB_TOP, 0, DWB_CRC_BLUE_MASK, mask_sh),\ |
170 | SF_DWB2(DWB_CRC_MASK_B_A, DWB_TOP, 0, DWB_CRC_A_MASK, mask_sh),\ |
171 | SF_DWB2(DWB_CRC_VAL_R_G, DWB_TOP, 0, DWB_CRC_SIG_RED, mask_sh),\ |
172 | SF_DWB2(DWB_CRC_VAL_R_G, DWB_TOP, 0, DWB_CRC_SIG_GREEN, mask_sh),\ |
173 | SF_DWB2(DWB_CRC_VAL_B_A, DWB_TOP, 0, DWB_CRC_SIG_BLUE, mask_sh),\ |
174 | SF_DWB2(DWB_CRC_VAL_B_A, DWB_TOP, 0, DWB_CRC_SIG_A, mask_sh),\ |
175 | SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_FORMAT, mask_sh),\ |
176 | SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_DENORM, mask_sh),\ |
177 | SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_MAX, mask_sh),\ |
178 | SF_DWB2(DWB_OUT_CTRL, DWB_TOP, 0, OUT_MIN, mask_sh),\ |
179 | SF_DWB2(DWB_MMHUBBUB_BACKPRESSURE_CNT_EN, DWB_TOP, 0, DWB_MMHUBBUB_BACKPRESSURE_CNT_EN, mask_sh),\ |
180 | SF_DWB2(DWB_MMHUBBUB_BACKPRESSURE_CNT, DWB_TOP, 0, DWB_MMHUBBUB_MAX_BACKPRESSURE, mask_sh),\ |
181 | SF_DWB2(DWB_HOST_READ_CONTROL, DWB_TOP, 0, DWB_HOST_READ_RATE_CONTROL, mask_sh),\ |
182 | SF_DWB2(DWB_SOFT_RESET, DWB_TOP, 0, DWB_SOFT_RESET, mask_sh),\ |
183 | SF_DWB2(DWB_HDR_MULT_COEF, DWBCP, 0, DWB_HDR_MULT_COEF, mask_sh),\ |
184 | SF_DWB2(DWB_GAMUT_REMAP_MODE, DWBCP, 0, DWB_GAMUT_REMAP_MODE, mask_sh),\ |
185 | SF_DWB2(DWB_GAMUT_REMAP_MODE, DWBCP, 0, DWB_GAMUT_REMAP_MODE_CURRENT, mask_sh),\ |
186 | SF_DWB2(DWB_GAMUT_REMAP_COEF_FORMAT, DWBCP, 0, DWB_GAMUT_REMAP_COEF_FORMAT, mask_sh),\ |
187 | SF_DWB2(DWB_GAMUT_REMAPA_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPA_C11, mask_sh),\ |
188 | SF_DWB2(DWB_GAMUT_REMAPA_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPA_C12, mask_sh),\ |
189 | SF_DWB2(DWB_GAMUT_REMAPA_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPA_C13, mask_sh),\ |
190 | SF_DWB2(DWB_GAMUT_REMAPA_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPA_C14, mask_sh),\ |
191 | SF_DWB2(DWB_GAMUT_REMAPA_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPA_C21, mask_sh),\ |
192 | SF_DWB2(DWB_GAMUT_REMAPA_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPA_C22, mask_sh),\ |
193 | SF_DWB2(DWB_GAMUT_REMAPA_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPA_C23, mask_sh),\ |
194 | SF_DWB2(DWB_GAMUT_REMAPA_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPA_C24, mask_sh),\ |
195 | SF_DWB2(DWB_GAMUT_REMAPA_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPA_C31, mask_sh),\ |
196 | SF_DWB2(DWB_GAMUT_REMAPA_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPA_C32, mask_sh),\ |
197 | SF_DWB2(DWB_GAMUT_REMAPA_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPA_C33, mask_sh),\ |
198 | SF_DWB2(DWB_GAMUT_REMAPA_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPA_C34, mask_sh),\ |
199 | SF_DWB2(DWB_GAMUT_REMAPB_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPB_C11, mask_sh),\ |
200 | SF_DWB2(DWB_GAMUT_REMAPB_C11_C12, DWBCP, 0, DWB_GAMUT_REMAPB_C12, mask_sh),\ |
201 | SF_DWB2(DWB_GAMUT_REMAPB_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPB_C13, mask_sh),\ |
202 | SF_DWB2(DWB_GAMUT_REMAPB_C13_C14, DWBCP, 0, DWB_GAMUT_REMAPB_C14, mask_sh),\ |
203 | SF_DWB2(DWB_GAMUT_REMAPB_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPB_C21, mask_sh),\ |
204 | SF_DWB2(DWB_GAMUT_REMAPB_C21_C22, DWBCP, 0, DWB_GAMUT_REMAPB_C22, mask_sh),\ |
205 | SF_DWB2(DWB_GAMUT_REMAPB_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPB_C23, mask_sh),\ |
206 | SF_DWB2(DWB_GAMUT_REMAPB_C23_C24, DWBCP, 0, DWB_GAMUT_REMAPB_C24, mask_sh),\ |
207 | SF_DWB2(DWB_GAMUT_REMAPB_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPB_C31, mask_sh),\ |
208 | SF_DWB2(DWB_GAMUT_REMAPB_C31_C32, DWBCP, 0, DWB_GAMUT_REMAPB_C32, mask_sh),\ |
209 | SF_DWB2(DWB_GAMUT_REMAPB_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPB_C33, mask_sh),\ |
210 | SF_DWB2(DWB_GAMUT_REMAPB_C33_C34, DWBCP, 0, DWB_GAMUT_REMAPB_C34, mask_sh),\ |
211 | SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_MODE, mask_sh),\ |
212 | SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_SELECT, mask_sh),\ |
213 | SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_PWL_DISABLE, mask_sh),\ |
214 | SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_MODE_CURRENT, mask_sh),\ |
215 | SF_DWB2(DWB_OGAM_CONTROL, DWBCP, 0, DWB_OGAM_SELECT_CURRENT, mask_sh),\ |
216 | SF_DWB2(DWB_OGAM_LUT_INDEX, DWBCP, 0, DWB_OGAM_LUT_INDEX, mask_sh),\ |
217 | SF_DWB2(DWB_OGAM_LUT_DATA, DWBCP, 0, DWB_OGAM_LUT_DATA, mask_sh),\ |
218 | SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_WRITE_COLOR_MASK, mask_sh),\ |
219 | SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_READ_COLOR_SEL, mask_sh),\ |
220 | SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_HOST_SEL, mask_sh),\ |
221 | SF_DWB2(DWB_OGAM_LUT_CONTROL, DWBCP, 0, DWB_OGAM_LUT_CONFIG_MODE, mask_sh),\ |
222 | SF_DWB2(DWB_OGAM_RAMA_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_B, mask_sh),\ |
223 | SF_DWB2(DWB_OGAM_RAMA_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, mask_sh),\ |
224 | SF_DWB2(DWB_OGAM_RAMA_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_G, mask_sh),\ |
225 | SF_DWB2(DWB_OGAM_RAMA_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G, mask_sh),\ |
226 | SF_DWB2(DWB_OGAM_RAMA_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_R, mask_sh),\ |
227 | SF_DWB2(DWB_OGAM_RAMA_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R, mask_sh),\ |
228 | SF_DWB2(DWB_OGAM_RAMA_START_BASE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_BASE_B, mask_sh),\ |
229 | SF_DWB2(DWB_OGAM_RAMA_START_SLOPE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B, mask_sh),\ |
230 | SF_DWB2(DWB_OGAM_RAMA_START_BASE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_BASE_G, mask_sh),\ |
231 | SF_DWB2(DWB_OGAM_RAMA_START_SLOPE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G, mask_sh),\ |
232 | SF_DWB2(DWB_OGAM_RAMA_START_BASE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_BASE_R, mask_sh),\ |
233 | SF_DWB2(DWB_OGAM_RAMA_START_SLOPE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R, mask_sh),\ |
234 | SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_B, mask_sh),\ |
235 | SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_B, mask_sh),\ |
236 | SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B, mask_sh),\ |
237 | SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_G, mask_sh),\ |
238 | SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_G, mask_sh),\ |
239 | SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G, mask_sh),\ |
240 | SF_DWB2(DWB_OGAM_RAMA_END_CNTL1_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_BASE_R, mask_sh),\ |
241 | SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_R, mask_sh),\ |
242 | SF_DWB2(DWB_OGAM_RAMA_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R, mask_sh),\ |
243 | SF_DWB2(DWB_OGAM_RAMA_OFFSET_B, DWBCP, 0, DWB_OGAM_RAMA_OFFSET_B, mask_sh),\ |
244 | SF_DWB2(DWB_OGAM_RAMA_OFFSET_G, DWBCP, 0, DWB_OGAM_RAMA_OFFSET_G, mask_sh),\ |
245 | SF_DWB2(DWB_OGAM_RAMA_OFFSET_R, DWBCP, 0, DWB_OGAM_RAMA_OFFSET_R, mask_sh),\ |
246 | SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, mask_sh),\ |
247 | SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ |
248 | SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, mask_sh),\ |
249 | SF_DWB2(DWB_OGAM_RAMA_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ |
250 | SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET, mask_sh),\ |
251 | SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, mask_sh),\ |
252 | SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET, mask_sh),\ |
253 | SF_DWB2(DWB_OGAM_RAMA_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, mask_sh),\ |
254 | SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET, mask_sh),\ |
255 | SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, mask_sh),\ |
256 | SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET, mask_sh),\ |
257 | SF_DWB2(DWB_OGAM_RAMA_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, mask_sh),\ |
258 | SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET, mask_sh),\ |
259 | SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, mask_sh),\ |
260 | SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET, mask_sh),\ |
261 | SF_DWB2(DWB_OGAM_RAMA_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, mask_sh),\ |
262 | SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET, mask_sh),\ |
263 | SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, mask_sh),\ |
264 | SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET, mask_sh),\ |
265 | SF_DWB2(DWB_OGAM_RAMA_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, mask_sh),\ |
266 | SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET, mask_sh),\ |
267 | SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, mask_sh),\ |
268 | SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET, mask_sh),\ |
269 | SF_DWB2(DWB_OGAM_RAMA_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, mask_sh),\ |
270 | SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET, mask_sh),\ |
271 | SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, mask_sh),\ |
272 | SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET, mask_sh),\ |
273 | SF_DWB2(DWB_OGAM_RAMA_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, mask_sh),\ |
274 | SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET, mask_sh),\ |
275 | SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, mask_sh),\ |
276 | SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET, mask_sh),\ |
277 | SF_DWB2(DWB_OGAM_RAMA_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, mask_sh),\ |
278 | SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET, mask_sh),\ |
279 | SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, mask_sh),\ |
280 | SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET, mask_sh),\ |
281 | SF_DWB2(DWB_OGAM_RAMA_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, mask_sh),\ |
282 | SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET, mask_sh),\ |
283 | SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, mask_sh),\ |
284 | SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET, mask_sh),\ |
285 | SF_DWB2(DWB_OGAM_RAMA_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, mask_sh),\ |
286 | SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET, mask_sh),\ |
287 | SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, mask_sh),\ |
288 | SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET, mask_sh),\ |
289 | SF_DWB2(DWB_OGAM_RAMA_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, mask_sh),\ |
290 | SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET, mask_sh),\ |
291 | SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, mask_sh),\ |
292 | SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET, mask_sh),\ |
293 | SF_DWB2(DWB_OGAM_RAMA_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, mask_sh),\ |
294 | SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET, mask_sh),\ |
295 | SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, mask_sh),\ |
296 | SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET, mask_sh),\ |
297 | SF_DWB2(DWB_OGAM_RAMA_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, mask_sh),\ |
298 | SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET, mask_sh),\ |
299 | SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, mask_sh),\ |
300 | SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET, mask_sh),\ |
301 | SF_DWB2(DWB_OGAM_RAMA_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, mask_sh),\ |
302 | SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET, mask_sh),\ |
303 | SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, mask_sh),\ |
304 | SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET, mask_sh),\ |
305 | SF_DWB2(DWB_OGAM_RAMA_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, mask_sh),\ |
306 | SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET, mask_sh),\ |
307 | SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, mask_sh),\ |
308 | SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET, mask_sh),\ |
309 | SF_DWB2(DWB_OGAM_RAMA_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, mask_sh),\ |
310 | SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET, mask_sh),\ |
311 | SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, mask_sh),\ |
312 | SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET, mask_sh),\ |
313 | SF_DWB2(DWB_OGAM_RAMA_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, mask_sh),\ |
314 | SF_DWB2(DWB_OGAM_RAMB_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_B, mask_sh),\ |
315 | SF_DWB2(DWB_OGAM_RAMB_START_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B, mask_sh),\ |
316 | SF_DWB2(DWB_OGAM_RAMB_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_G, mask_sh),\ |
317 | SF_DWB2(DWB_OGAM_RAMB_START_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G, mask_sh),\ |
318 | SF_DWB2(DWB_OGAM_RAMB_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_R, mask_sh),\ |
319 | SF_DWB2(DWB_OGAM_RAMB_START_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R, mask_sh),\ |
320 | SF_DWB2(DWB_OGAM_RAMB_START_BASE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_BASE_B, mask_sh),\ |
321 | SF_DWB2(DWB_OGAM_RAMB_START_SLOPE_CNTL_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B, mask_sh),\ |
322 | SF_DWB2(DWB_OGAM_RAMB_START_BASE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_BASE_G, mask_sh),\ |
323 | SF_DWB2(DWB_OGAM_RAMB_START_SLOPE_CNTL_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G, mask_sh),\ |
324 | SF_DWB2(DWB_OGAM_RAMB_START_BASE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_BASE_R, mask_sh),\ |
325 | SF_DWB2(DWB_OGAM_RAMB_START_SLOPE_CNTL_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R, mask_sh),\ |
326 | SF_DWB2(DWB_OGAM_RAMB_END_CNTL1_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_BASE_B, mask_sh),\ |
327 | SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_B, mask_sh),\ |
328 | SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_B, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B, mask_sh),\ |
329 | SF_DWB2(DWB_OGAM_RAMB_END_CNTL1_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_BASE_G, mask_sh),\ |
330 | SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_G, mask_sh),\ |
331 | SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_G, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G, mask_sh),\ |
332 | SF_DWB2(DWB_OGAM_RAMB_END_CNTL1_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_BASE_R, mask_sh),\ |
333 | SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_R, mask_sh),\ |
334 | SF_DWB2(DWB_OGAM_RAMB_END_CNTL2_R, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R, mask_sh),\ |
335 | SF_DWB2(DWB_OGAM_RAMB_OFFSET_B, DWBCP, 0, DWB_OGAM_RAMB_OFFSET_B, mask_sh),\ |
336 | SF_DWB2(DWB_OGAM_RAMB_OFFSET_G, DWBCP, 0, DWB_OGAM_RAMB_OFFSET_G, mask_sh),\ |
337 | SF_DWB2(DWB_OGAM_RAMB_OFFSET_R, DWBCP, 0, DWB_OGAM_RAMB_OFFSET_R, mask_sh),\ |
338 | SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET, mask_sh),\ |
339 | SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ |
340 | SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET, mask_sh),\ |
341 | SF_DWB2(DWB_OGAM_RAMB_REGION_0_1, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ |
342 | SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET, mask_sh),\ |
343 | SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, mask_sh),\ |
344 | SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET, mask_sh),\ |
345 | SF_DWB2(DWB_OGAM_RAMB_REGION_2_3, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, mask_sh),\ |
346 | SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET, mask_sh),\ |
347 | SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, mask_sh),\ |
348 | SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET, mask_sh),\ |
349 | SF_DWB2(DWB_OGAM_RAMB_REGION_4_5, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, mask_sh),\ |
350 | SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET, mask_sh),\ |
351 | SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, mask_sh),\ |
352 | SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET, mask_sh),\ |
353 | SF_DWB2(DWB_OGAM_RAMB_REGION_6_7, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, mask_sh),\ |
354 | SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET, mask_sh),\ |
355 | SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, mask_sh),\ |
356 | SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET, mask_sh),\ |
357 | SF_DWB2(DWB_OGAM_RAMB_REGION_8_9, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, mask_sh),\ |
358 | SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET, mask_sh),\ |
359 | SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, mask_sh),\ |
360 | SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET, mask_sh),\ |
361 | SF_DWB2(DWB_OGAM_RAMB_REGION_10_11, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, mask_sh),\ |
362 | SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET, mask_sh),\ |
363 | SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, mask_sh),\ |
364 | SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET, mask_sh),\ |
365 | SF_DWB2(DWB_OGAM_RAMB_REGION_12_13, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, mask_sh),\ |
366 | SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET, mask_sh),\ |
367 | SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, mask_sh),\ |
368 | SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET, mask_sh),\ |
369 | SF_DWB2(DWB_OGAM_RAMB_REGION_14_15, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, mask_sh),\ |
370 | SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET, mask_sh),\ |
371 | SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, mask_sh),\ |
372 | SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET, mask_sh),\ |
373 | SF_DWB2(DWB_OGAM_RAMB_REGION_16_17, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, mask_sh),\ |
374 | SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET, mask_sh),\ |
375 | SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, mask_sh),\ |
376 | SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET, mask_sh),\ |
377 | SF_DWB2(DWB_OGAM_RAMB_REGION_18_19, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, mask_sh),\ |
378 | SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET, mask_sh),\ |
379 | SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, mask_sh),\ |
380 | SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET, mask_sh),\ |
381 | SF_DWB2(DWB_OGAM_RAMB_REGION_20_21, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, mask_sh),\ |
382 | SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET, mask_sh),\ |
383 | SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, mask_sh),\ |
384 | SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET, mask_sh),\ |
385 | SF_DWB2(DWB_OGAM_RAMB_REGION_22_23, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, mask_sh),\ |
386 | SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET, mask_sh),\ |
387 | SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, mask_sh),\ |
388 | SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET, mask_sh),\ |
389 | SF_DWB2(DWB_OGAM_RAMB_REGION_24_25, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, mask_sh),\ |
390 | SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET, mask_sh),\ |
391 | SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, mask_sh),\ |
392 | SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET, mask_sh),\ |
393 | SF_DWB2(DWB_OGAM_RAMB_REGION_26_27, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, mask_sh),\ |
394 | SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET, mask_sh),\ |
395 | SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, mask_sh),\ |
396 | SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET, mask_sh),\ |
397 | SF_DWB2(DWB_OGAM_RAMB_REGION_28_29, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, mask_sh),\ |
398 | SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET, mask_sh),\ |
399 | SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, mask_sh),\ |
400 | SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET, mask_sh),\ |
401 | SF_DWB2(DWB_OGAM_RAMB_REGION_30_31, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, mask_sh),\ |
402 | SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET, mask_sh),\ |
403 | SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, mask_sh),\ |
404 | SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET, mask_sh),\ |
405 | SF_DWB2(DWB_OGAM_RAMB_REGION_32_33, DWBCP, 0, DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, mask_sh) |
406 | |
407 | |
408 | #define DWBC_REG_FIELD_LIST_DCN3_0(type) \ |
409 | type DWB_ENABLE;\ |
410 | type DISPCLK_R_DWB_GATE_DIS;\ |
411 | type DISPCLK_G_DWB_GATE_DIS;\ |
412 | type DWB_TEST_CLK_SEL;\ |
413 | type DWBSCL_LUT_MEM_PWR_FORCE;\ |
414 | type DWBSCL_LUT_MEM_PWR_DIS;\ |
415 | type DWBSCL_LUT_MEM_PWR_STATE;\ |
416 | type DWBSCL_LB_MEM_PWR_FORCE;\ |
417 | type DWBSCL_LB_MEM_PWR_DIS;\ |
418 | type DWBSCL_LB_MEM_PWR_STATE;\ |
419 | type DWB_OGAM_LUT_MEM_PWR_FORCE;\ |
420 | type DWB_OGAM_LUT_MEM_PWR_DIS;\ |
421 | type DWB_OGAM_LUT_MEM_PWR_STATE;\ |
422 | type FC_FRAME_CAPTURE_EN;\ |
423 | type FC_FRAME_CAPTURE_RATE;\ |
424 | type FC_WINDOW_CROP_EN;\ |
425 | type FC_EYE_SELECTION;\ |
426 | type FC_STEREO_EYE_POLARITY;\ |
427 | type FC_NEW_CONTENT;\ |
428 | type FC_FI_EN;\ |
429 | type FC_FI_PHASE;\ |
430 | type FC_FRAME_CAPTURE_EN_CURRENT;\ |
431 | type FC_FIRST_PIXEL_DELAY_COUNT;\ |
432 | type FC_WINDOW_START_X;\ |
433 | type FC_WINDOW_START_Y;\ |
434 | type FC_WINDOW_WIDTH;\ |
435 | type FC_WINDOW_HEIGHT;\ |
436 | type FC_SOURCE_WIDTH;\ |
437 | type FC_SOURCE_HEIGHT;\ |
438 | type DWB_UPDATE_LOCK;\ |
439 | type DWB_UPDATE_PENDING;\ |
440 | type DWB_CRC_EN;\ |
441 | type DWB_CRC_CONT_EN;\ |
442 | type DWB_CRC_SRC_SEL;\ |
443 | type DWB_CRC_RED_MASK;\ |
444 | type DWB_CRC_GREEN_MASK;\ |
445 | type DWB_CRC_BLUE_MASK;\ |
446 | type DWB_CRC_A_MASK;\ |
447 | type DWB_CRC_SIG_RED;\ |
448 | type DWB_CRC_SIG_GREEN;\ |
449 | type DWB_CRC_SIG_BLUE;\ |
450 | type DWB_CRC_SIG_A;\ |
451 | type OUT_FORMAT;\ |
452 | type OUT_DENORM;\ |
453 | type OUT_MAX;\ |
454 | type OUT_MIN;\ |
455 | type DWB_MMHUBBUB_BACKPRESSURE_CNT_EN;\ |
456 | type DWB_MMHUBBUB_MAX_BACKPRESSURE;\ |
457 | type DWB_HOST_READ_RATE_CONTROL;\ |
458 | type DWBSCL_DATA_OVERFLOW_FLAG;\ |
459 | type DWBSCL_DATA_OVERFLOW_ACK;\ |
460 | type DWBSCL_DATA_OVERFLOW_MASK;\ |
461 | type DWBSCL_DATA_OVERFLOW_INT_STATUS;\ |
462 | type DWBSCL_DATA_OVERFLOW_INT_TYPE;\ |
463 | type DWBSCL_DATA_OVERFLOW_TYPE;\ |
464 | type DWBSCL_DATA_OVERFLOW_OUT_X_CNT;\ |
465 | type DWBSCL_DATA_OVERFLOW_OUT_Y_CNT;\ |
466 | type DWB_SOFT_RESET;\ |
467 | type DWBSCL_COEF_RAM_TAP_PAIR_IDX;\ |
468 | type DWBSCL_COEF_RAM_PHASE;\ |
469 | type DWBSCL_COEF_RAM_FILTER_TYPE;\ |
470 | type DWBSCL_COEF_RAM_SELECT_RD;\ |
471 | type DWBSCL_COEF_RAM_EVEN_TAP_COEF;\ |
472 | type DWBSCL_COEF_RAM_EVEN_TAP_COEF_EN;\ |
473 | type DWBSCL_COEF_RAM_ODD_TAP_COEF;\ |
474 | type DWBSCL_COEF_RAM_ODD_TAP_COEF_EN;\ |
475 | type DWBSCL_MODE;\ |
476 | type DWBSCL_COEF_RAM_SELECT;\ |
477 | type DWBSCL_COEF_RAM_SELECT_CURRENT;\ |
478 | type DWBSCL_H_NUM_OF_TAPS;\ |
479 | type DWBSCL_V_NUM_OF_TAPS;\ |
480 | type DWBSCL_H_SCALE_RATIO;\ |
481 | type DWBSCL_H_INIT_FRAC;\ |
482 | type DWBSCL_H_INIT_INT;\ |
483 | type DWBSCL_V_SCALE_RATIO;\ |
484 | type DWBSCL_V_INIT_FRAC;\ |
485 | type DWBSCL_V_INIT_INT;\ |
486 | type DWBSCL_BOUNDARY_MODE;\ |
487 | type DWBSCL_BLACK_COLOR_RGB;\ |
488 | type DWBSCL_DEST_WIDTH;\ |
489 | type DWBSCL_DEST_HEIGHT;\ |
490 | type DWB_HDR_MULT_COEF;\ |
491 | type DWB_GAMUT_REMAP_MODE;\ |
492 | type DWB_GAMUT_REMAP_MODE_CURRENT;\ |
493 | type DWB_GAMUT_REMAP_COEF_FORMAT;\ |
494 | type DWB_GAMUT_REMAPA_C11;\ |
495 | type DWB_GAMUT_REMAPA_C12;\ |
496 | type DWB_GAMUT_REMAPA_C13;\ |
497 | type DWB_GAMUT_REMAPA_C14;\ |
498 | type DWB_GAMUT_REMAPA_C21;\ |
499 | type DWB_GAMUT_REMAPA_C22;\ |
500 | type DWB_GAMUT_REMAPA_C23;\ |
501 | type DWB_GAMUT_REMAPA_C24;\ |
502 | type DWB_GAMUT_REMAPA_C31;\ |
503 | type DWB_GAMUT_REMAPA_C32;\ |
504 | type DWB_GAMUT_REMAPA_C33;\ |
505 | type DWB_GAMUT_REMAPA_C34;\ |
506 | type DWB_GAMUT_REMAPB_C11;\ |
507 | type DWB_GAMUT_REMAPB_C12;\ |
508 | type DWB_GAMUT_REMAPB_C13;\ |
509 | type DWB_GAMUT_REMAPB_C14;\ |
510 | type DWB_GAMUT_REMAPB_C21;\ |
511 | type DWB_GAMUT_REMAPB_C22;\ |
512 | type DWB_GAMUT_REMAPB_C23;\ |
513 | type DWB_GAMUT_REMAPB_C24;\ |
514 | type DWB_GAMUT_REMAPB_C31;\ |
515 | type DWB_GAMUT_REMAPB_C32;\ |
516 | type DWB_GAMUT_REMAPB_C33;\ |
517 | type DWB_GAMUT_REMAPB_C34;\ |
518 | type DWB_OGAM_MODE;\ |
519 | type DWB_OGAM_SELECT;\ |
520 | type DWB_OGAM_PWL_DISABLE;\ |
521 | type DWB_OGAM_MODE_CURRENT;\ |
522 | type DWB_OGAM_SELECT_CURRENT;\ |
523 | type DWB_OGAM_LUT_INDEX;\ |
524 | type DWB_OGAM_LUT_DATA;\ |
525 | type DWB_OGAM_LUT_WRITE_COLOR_MASK;\ |
526 | type DWB_OGAM_LUT_READ_COLOR_SEL;\ |
527 | type DWB_OGAM_LUT_HOST_SEL;\ |
528 | type DWB_OGAM_LUT_CONFIG_MODE;\ |
529 | type DWB_OGAM_LUT_STATUS;\ |
530 | type DWB_OGAM_RAMA_EXP_REGION_START_B;\ |
531 | type DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;\ |
532 | type DWB_OGAM_RAMA_EXP_REGION_START_G;\ |
533 | type DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_G;\ |
534 | type DWB_OGAM_RAMA_EXP_REGION_START_R;\ |
535 | type DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_R;\ |
536 | type DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;\ |
537 | type DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;\ |
538 | type DWB_OGAM_RAMA_EXP_REGION_START_BASE_G;\ |
539 | type DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_G;\ |
540 | type DWB_OGAM_RAMA_EXP_REGION_START_BASE_R;\ |
541 | type DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_R;\ |
542 | type DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;\ |
543 | type DWB_OGAM_RAMA_EXP_REGION_END_B;\ |
544 | type DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B;\ |
545 | type DWB_OGAM_RAMA_EXP_REGION_END_BASE_G;\ |
546 | type DWB_OGAM_RAMA_EXP_REGION_END_G;\ |
547 | type DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_G;\ |
548 | type DWB_OGAM_RAMA_EXP_REGION_END_BASE_R;\ |
549 | type DWB_OGAM_RAMA_EXP_REGION_END_R;\ |
550 | type DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_R;\ |
551 | type DWB_OGAM_RAMA_OFFSET_B;\ |
552 | type DWB_OGAM_RAMA_OFFSET_G;\ |
553 | type DWB_OGAM_RAMA_OFFSET_R;\ |
554 | type DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;\ |
555 | type DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;\ |
556 | type DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET;\ |
557 | type DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;\ |
558 | type DWB_OGAM_RAMA_EXP_REGION2_LUT_OFFSET;\ |
559 | type DWB_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS;\ |
560 | type DWB_OGAM_RAMA_EXP_REGION3_LUT_OFFSET;\ |
561 | type DWB_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS;\ |
562 | type DWB_OGAM_RAMA_EXP_REGION4_LUT_OFFSET;\ |
563 | type DWB_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS;\ |
564 | type DWB_OGAM_RAMA_EXP_REGION5_LUT_OFFSET;\ |
565 | type DWB_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS;\ |
566 | type DWB_OGAM_RAMA_EXP_REGION6_LUT_OFFSET;\ |
567 | type DWB_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS;\ |
568 | type DWB_OGAM_RAMA_EXP_REGION7_LUT_OFFSET;\ |
569 | type DWB_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS;\ |
570 | type DWB_OGAM_RAMA_EXP_REGION8_LUT_OFFSET;\ |
571 | type DWB_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS;\ |
572 | type DWB_OGAM_RAMA_EXP_REGION9_LUT_OFFSET;\ |
573 | type DWB_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS;\ |
574 | type DWB_OGAM_RAMA_EXP_REGION10_LUT_OFFSET;\ |
575 | type DWB_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS;\ |
576 | type DWB_OGAM_RAMA_EXP_REGION11_LUT_OFFSET;\ |
577 | type DWB_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS;\ |
578 | type DWB_OGAM_RAMA_EXP_REGION12_LUT_OFFSET;\ |
579 | type DWB_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS;\ |
580 | type DWB_OGAM_RAMA_EXP_REGION13_LUT_OFFSET;\ |
581 | type DWB_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS;\ |
582 | type DWB_OGAM_RAMA_EXP_REGION14_LUT_OFFSET;\ |
583 | type DWB_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS;\ |
584 | type DWB_OGAM_RAMA_EXP_REGION15_LUT_OFFSET;\ |
585 | type DWB_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS;\ |
586 | type DWB_OGAM_RAMA_EXP_REGION16_LUT_OFFSET;\ |
587 | type DWB_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS;\ |
588 | type DWB_OGAM_RAMA_EXP_REGION17_LUT_OFFSET;\ |
589 | type DWB_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS;\ |
590 | type DWB_OGAM_RAMA_EXP_REGION18_LUT_OFFSET;\ |
591 | type DWB_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS;\ |
592 | type DWB_OGAM_RAMA_EXP_REGION19_LUT_OFFSET;\ |
593 | type DWB_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS;\ |
594 | type DWB_OGAM_RAMA_EXP_REGION20_LUT_OFFSET;\ |
595 | type DWB_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS;\ |
596 | type DWB_OGAM_RAMA_EXP_REGION21_LUT_OFFSET;\ |
597 | type DWB_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS;\ |
598 | type DWB_OGAM_RAMA_EXP_REGION22_LUT_OFFSET;\ |
599 | type DWB_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS;\ |
600 | type DWB_OGAM_RAMA_EXP_REGION23_LUT_OFFSET;\ |
601 | type DWB_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS;\ |
602 | type DWB_OGAM_RAMA_EXP_REGION24_LUT_OFFSET;\ |
603 | type DWB_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS;\ |
604 | type DWB_OGAM_RAMA_EXP_REGION25_LUT_OFFSET;\ |
605 | type DWB_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS;\ |
606 | type DWB_OGAM_RAMA_EXP_REGION26_LUT_OFFSET;\ |
607 | type DWB_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS;\ |
608 | type DWB_OGAM_RAMA_EXP_REGION27_LUT_OFFSET;\ |
609 | type DWB_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS;\ |
610 | type DWB_OGAM_RAMA_EXP_REGION28_LUT_OFFSET;\ |
611 | type DWB_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS;\ |
612 | type DWB_OGAM_RAMA_EXP_REGION29_LUT_OFFSET;\ |
613 | type DWB_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS;\ |
614 | type DWB_OGAM_RAMA_EXP_REGION30_LUT_OFFSET;\ |
615 | type DWB_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS;\ |
616 | type DWB_OGAM_RAMA_EXP_REGION31_LUT_OFFSET;\ |
617 | type DWB_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS;\ |
618 | type DWB_OGAM_RAMA_EXP_REGION32_LUT_OFFSET;\ |
619 | type DWB_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS;\ |
620 | type DWB_OGAM_RAMA_EXP_REGION33_LUT_OFFSET;\ |
621 | type DWB_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS;\ |
622 | type DWB_OGAM_RAMB_EXP_REGION_START_B;\ |
623 | type DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_B;\ |
624 | type DWB_OGAM_RAMB_EXP_REGION_START_G;\ |
625 | type DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_G;\ |
626 | type DWB_OGAM_RAMB_EXP_REGION_START_R;\ |
627 | type DWB_OGAM_RAMB_EXP_REGION_START_SEGMENT_R;\ |
628 | type DWB_OGAM_RAMB_EXP_REGION_START_BASE_B;\ |
629 | type DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_B;\ |
630 | type DWB_OGAM_RAMB_EXP_REGION_START_BASE_G;\ |
631 | type DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_G;\ |
632 | type DWB_OGAM_RAMB_EXP_REGION_START_BASE_R;\ |
633 | type DWB_OGAM_RAMB_EXP_REGION_START_SLOPE_R;\ |
634 | type DWB_OGAM_RAMB_EXP_REGION_END_BASE_B;\ |
635 | type DWB_OGAM_RAMB_EXP_REGION_END_B;\ |
636 | type DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_B;\ |
637 | type DWB_OGAM_RAMB_EXP_REGION_END_BASE_G;\ |
638 | type DWB_OGAM_RAMB_EXP_REGION_END_G;\ |
639 | type DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_G;\ |
640 | type DWB_OGAM_RAMB_EXP_REGION_END_BASE_R;\ |
641 | type DWB_OGAM_RAMB_EXP_REGION_END_R;\ |
642 | type DWB_OGAM_RAMB_EXP_REGION_END_SLOPE_R;\ |
643 | type DWB_OGAM_RAMB_OFFSET_B;\ |
644 | type DWB_OGAM_RAMB_OFFSET_G;\ |
645 | type DWB_OGAM_RAMB_OFFSET_R;\ |
646 | type DWB_OGAM_RAMB_EXP_REGION0_LUT_OFFSET;\ |
647 | type DWB_OGAM_RAMB_EXP_REGION0_NUM_SEGMENTS;\ |
648 | type DWB_OGAM_RAMB_EXP_REGION1_LUT_OFFSET;\ |
649 | type DWB_OGAM_RAMB_EXP_REGION1_NUM_SEGMENTS;\ |
650 | type DWB_OGAM_RAMB_EXP_REGION2_LUT_OFFSET;\ |
651 | type DWB_OGAM_RAMB_EXP_REGION2_NUM_SEGMENTS;\ |
652 | type DWB_OGAM_RAMB_EXP_REGION3_LUT_OFFSET;\ |
653 | type DWB_OGAM_RAMB_EXP_REGION3_NUM_SEGMENTS;\ |
654 | type DWB_OGAM_RAMB_EXP_REGION4_LUT_OFFSET;\ |
655 | type DWB_OGAM_RAMB_EXP_REGION4_NUM_SEGMENTS;\ |
656 | type DWB_OGAM_RAMB_EXP_REGION5_LUT_OFFSET;\ |
657 | type DWB_OGAM_RAMB_EXP_REGION5_NUM_SEGMENTS;\ |
658 | type DWB_OGAM_RAMB_EXP_REGION6_LUT_OFFSET;\ |
659 | type DWB_OGAM_RAMB_EXP_REGION6_NUM_SEGMENTS;\ |
660 | type DWB_OGAM_RAMB_EXP_REGION7_LUT_OFFSET;\ |
661 | type DWB_OGAM_RAMB_EXP_REGION7_NUM_SEGMENTS;\ |
662 | type DWB_OGAM_RAMB_EXP_REGION8_LUT_OFFSET;\ |
663 | type DWB_OGAM_RAMB_EXP_REGION8_NUM_SEGMENTS;\ |
664 | type DWB_OGAM_RAMB_EXP_REGION9_LUT_OFFSET;\ |
665 | type DWB_OGAM_RAMB_EXP_REGION9_NUM_SEGMENTS;\ |
666 | type DWB_OGAM_RAMB_EXP_REGION10_LUT_OFFSET;\ |
667 | type DWB_OGAM_RAMB_EXP_REGION10_NUM_SEGMENTS;\ |
668 | type DWB_OGAM_RAMB_EXP_REGION11_LUT_OFFSET;\ |
669 | type DWB_OGAM_RAMB_EXP_REGION11_NUM_SEGMENTS;\ |
670 | type DWB_OGAM_RAMB_EXP_REGION12_LUT_OFFSET;\ |
671 | type DWB_OGAM_RAMB_EXP_REGION12_NUM_SEGMENTS;\ |
672 | type DWB_OGAM_RAMB_EXP_REGION13_LUT_OFFSET;\ |
673 | type DWB_OGAM_RAMB_EXP_REGION13_NUM_SEGMENTS;\ |
674 | type DWB_OGAM_RAMB_EXP_REGION14_LUT_OFFSET;\ |
675 | type DWB_OGAM_RAMB_EXP_REGION14_NUM_SEGMENTS;\ |
676 | type DWB_OGAM_RAMB_EXP_REGION15_LUT_OFFSET;\ |
677 | type DWB_OGAM_RAMB_EXP_REGION15_NUM_SEGMENTS;\ |
678 | type DWB_OGAM_RAMB_EXP_REGION16_LUT_OFFSET;\ |
679 | type DWB_OGAM_RAMB_EXP_REGION16_NUM_SEGMENTS;\ |
680 | type DWB_OGAM_RAMB_EXP_REGION17_LUT_OFFSET;\ |
681 | type DWB_OGAM_RAMB_EXP_REGION17_NUM_SEGMENTS;\ |
682 | type DWB_OGAM_RAMB_EXP_REGION18_LUT_OFFSET;\ |
683 | type DWB_OGAM_RAMB_EXP_REGION18_NUM_SEGMENTS;\ |
684 | type DWB_OGAM_RAMB_EXP_REGION19_LUT_OFFSET;\ |
685 | type DWB_OGAM_RAMB_EXP_REGION19_NUM_SEGMENTS;\ |
686 | type DWB_OGAM_RAMB_EXP_REGION20_LUT_OFFSET;\ |
687 | type DWB_OGAM_RAMB_EXP_REGION20_NUM_SEGMENTS;\ |
688 | type DWB_OGAM_RAMB_EXP_REGION21_LUT_OFFSET;\ |
689 | type DWB_OGAM_RAMB_EXP_REGION21_NUM_SEGMENTS;\ |
690 | type DWB_OGAM_RAMB_EXP_REGION22_LUT_OFFSET;\ |
691 | type DWB_OGAM_RAMB_EXP_REGION22_NUM_SEGMENTS;\ |
692 | type DWB_OGAM_RAMB_EXP_REGION23_LUT_OFFSET;\ |
693 | type DWB_OGAM_RAMB_EXP_REGION23_NUM_SEGMENTS;\ |
694 | type DWB_OGAM_RAMB_EXP_REGION24_LUT_OFFSET;\ |
695 | type DWB_OGAM_RAMB_EXP_REGION24_NUM_SEGMENTS;\ |
696 | type DWB_OGAM_RAMB_EXP_REGION25_LUT_OFFSET;\ |
697 | type DWB_OGAM_RAMB_EXP_REGION25_NUM_SEGMENTS;\ |
698 | type DWB_OGAM_RAMB_EXP_REGION26_LUT_OFFSET;\ |
699 | type DWB_OGAM_RAMB_EXP_REGION26_NUM_SEGMENTS;\ |
700 | type DWB_OGAM_RAMB_EXP_REGION27_LUT_OFFSET;\ |
701 | type DWB_OGAM_RAMB_EXP_REGION27_NUM_SEGMENTS;\ |
702 | type DWB_OGAM_RAMB_EXP_REGION28_LUT_OFFSET;\ |
703 | type DWB_OGAM_RAMB_EXP_REGION28_NUM_SEGMENTS;\ |
704 | type DWB_OGAM_RAMB_EXP_REGION29_LUT_OFFSET;\ |
705 | type DWB_OGAM_RAMB_EXP_REGION29_NUM_SEGMENTS;\ |
706 | type DWB_OGAM_RAMB_EXP_REGION30_LUT_OFFSET;\ |
707 | type DWB_OGAM_RAMB_EXP_REGION30_NUM_SEGMENTS;\ |
708 | type DWB_OGAM_RAMB_EXP_REGION31_LUT_OFFSET;\ |
709 | type DWB_OGAM_RAMB_EXP_REGION31_NUM_SEGMENTS;\ |
710 | type DWB_OGAM_RAMB_EXP_REGION32_LUT_OFFSET;\ |
711 | type DWB_OGAM_RAMB_EXP_REGION32_NUM_SEGMENTS;\ |
712 | type DWB_OGAM_RAMB_EXP_REGION33_LUT_OFFSET;\ |
713 | type DWB_OGAM_RAMB_EXP_REGION33_NUM_SEGMENTS; |
714 | |
715 | struct dcn30_dwbc_registers { |
716 | /* DCN3AG */ |
717 | /* DWB_TOP */ |
718 | uint32_t DWB_ENABLE_CLK_CTRL; |
719 | uint32_t DWB_MEM_PWR_CTRL; |
720 | uint32_t FC_MODE_CTRL; |
721 | uint32_t FC_FLOW_CTRL; |
722 | uint32_t FC_WINDOW_START; |
723 | uint32_t FC_WINDOW_SIZE; |
724 | uint32_t FC_SOURCE_SIZE; |
725 | uint32_t DWB_UPDATE_CTRL; |
726 | uint32_t DWB_CRC_CTRL; |
727 | uint32_t DWB_CRC_MASK_R_G; |
728 | uint32_t DWB_CRC_MASK_B_A; |
729 | uint32_t DWB_CRC_VAL_R_G; |
730 | uint32_t DWB_CRC_VAL_B_A; |
731 | uint32_t DWB_OUT_CTRL; |
732 | uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT_EN; |
733 | uint32_t DWB_MMHUBBUB_BACKPRESSURE_CNT; |
734 | uint32_t DWB_HOST_READ_CONTROL; |
735 | uint32_t DWB_SOFT_RESET; |
736 | |
737 | /* DWBSCL */ |
738 | uint32_t DWBSCL_COEF_RAM_TAP_SELECT; |
739 | uint32_t DWBSCL_COEF_RAM_TAP_DATA; |
740 | uint32_t DWBSCL_MODE; |
741 | uint32_t DWBSCL_TAP_CONTROL; |
742 | uint32_t DWBSCL_HORZ_FILTER_SCALE_RATIO; |
743 | uint32_t DWBSCL_HORZ_FILTER_INIT; |
744 | uint32_t DWBSCL_VERT_FILTER_SCALE_RATIO; |
745 | uint32_t DWBSCL_VERT_FILTER_INIT; |
746 | uint32_t DWBSCL_BOUNDARY_CTRL; |
747 | uint32_t DWBSCL_DEST_SIZE; |
748 | uint32_t DWBSCL_OVERFLOW_STATUS; |
749 | uint32_t DWBSCL_OVERFLOW_COUNTER; |
750 | |
751 | /* DWBCP */ |
752 | uint32_t DWB_HDR_MULT_COEF; |
753 | uint32_t DWB_GAMUT_REMAP_MODE; |
754 | uint32_t DWB_GAMUT_REMAP_COEF_FORMAT; |
755 | uint32_t DWB_GAMUT_REMAPA_C11_C12; |
756 | uint32_t DWB_GAMUT_REMAPA_C13_C14; |
757 | uint32_t DWB_GAMUT_REMAPA_C21_C22; |
758 | uint32_t DWB_GAMUT_REMAPA_C23_C24; |
759 | uint32_t DWB_GAMUT_REMAPA_C31_C32; |
760 | uint32_t DWB_GAMUT_REMAPA_C33_C34; |
761 | uint32_t DWB_GAMUT_REMAPB_C11_C12; |
762 | uint32_t DWB_GAMUT_REMAPB_C13_C14; |
763 | uint32_t DWB_GAMUT_REMAPB_C21_C22; |
764 | uint32_t DWB_GAMUT_REMAPB_C23_C24; |
765 | uint32_t DWB_GAMUT_REMAPB_C31_C32; |
766 | uint32_t DWB_GAMUT_REMAPB_C33_C34; |
767 | uint32_t DWB_OGAM_CONTROL; |
768 | uint32_t DWB_OGAM_LUT_INDEX; |
769 | uint32_t DWB_OGAM_LUT_DATA; |
770 | uint32_t DWB_OGAM_LUT_CONTROL; |
771 | uint32_t DWB_OGAM_RAMA_START_CNTL_B; |
772 | uint32_t DWB_OGAM_RAMA_START_CNTL_G; |
773 | uint32_t DWB_OGAM_RAMA_START_CNTL_R; |
774 | uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_B; |
775 | uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_B; |
776 | uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_G; |
777 | uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_G; |
778 | uint32_t DWB_OGAM_RAMA_START_BASE_CNTL_R; |
779 | uint32_t DWB_OGAM_RAMA_START_SLOPE_CNTL_R; |
780 | uint32_t DWB_OGAM_RAMA_END_CNTL1_B; |
781 | uint32_t DWB_OGAM_RAMA_END_CNTL2_B; |
782 | uint32_t DWB_OGAM_RAMA_END_CNTL1_G; |
783 | uint32_t DWB_OGAM_RAMA_END_CNTL2_G; |
784 | uint32_t DWB_OGAM_RAMA_END_CNTL1_R; |
785 | uint32_t DWB_OGAM_RAMA_END_CNTL2_R; |
786 | uint32_t DWB_OGAM_RAMA_OFFSET_B; |
787 | uint32_t DWB_OGAM_RAMA_OFFSET_G; |
788 | uint32_t DWB_OGAM_RAMA_OFFSET_R; |
789 | uint32_t DWB_OGAM_RAMA_REGION_0_1; |
790 | uint32_t DWB_OGAM_RAMA_REGION_2_3; |
791 | uint32_t DWB_OGAM_RAMA_REGION_4_5; |
792 | uint32_t DWB_OGAM_RAMA_REGION_6_7; |
793 | uint32_t DWB_OGAM_RAMA_REGION_8_9; |
794 | uint32_t DWB_OGAM_RAMA_REGION_10_11; |
795 | uint32_t DWB_OGAM_RAMA_REGION_12_13; |
796 | uint32_t DWB_OGAM_RAMA_REGION_14_15; |
797 | uint32_t DWB_OGAM_RAMA_REGION_16_17; |
798 | uint32_t DWB_OGAM_RAMA_REGION_18_19; |
799 | uint32_t DWB_OGAM_RAMA_REGION_20_21; |
800 | uint32_t DWB_OGAM_RAMA_REGION_22_23; |
801 | uint32_t DWB_OGAM_RAMA_REGION_24_25; |
802 | uint32_t DWB_OGAM_RAMA_REGION_26_27; |
803 | uint32_t DWB_OGAM_RAMA_REGION_28_29; |
804 | uint32_t DWB_OGAM_RAMA_REGION_30_31; |
805 | uint32_t DWB_OGAM_RAMA_REGION_32_33; |
806 | uint32_t DWB_OGAM_RAMB_START_CNTL_B; |
807 | uint32_t DWB_OGAM_RAMB_START_CNTL_G; |
808 | uint32_t DWB_OGAM_RAMB_START_CNTL_R; |
809 | uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_B; |
810 | uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_B; |
811 | uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_G; |
812 | uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_G; |
813 | uint32_t DWB_OGAM_RAMB_START_BASE_CNTL_R; |
814 | uint32_t DWB_OGAM_RAMB_START_SLOPE_CNTL_R; |
815 | uint32_t DWB_OGAM_RAMB_END_CNTL1_B; |
816 | uint32_t DWB_OGAM_RAMB_END_CNTL2_B; |
817 | uint32_t DWB_OGAM_RAMB_END_CNTL1_G; |
818 | uint32_t DWB_OGAM_RAMB_END_CNTL2_G; |
819 | uint32_t DWB_OGAM_RAMB_END_CNTL1_R; |
820 | uint32_t DWB_OGAM_RAMB_END_CNTL2_R; |
821 | uint32_t DWB_OGAM_RAMB_OFFSET_B; |
822 | uint32_t DWB_OGAM_RAMB_OFFSET_G; |
823 | uint32_t DWB_OGAM_RAMB_OFFSET_R; |
824 | uint32_t DWB_OGAM_RAMB_REGION_0_1; |
825 | uint32_t DWB_OGAM_RAMB_REGION_2_3; |
826 | uint32_t DWB_OGAM_RAMB_REGION_4_5; |
827 | uint32_t DWB_OGAM_RAMB_REGION_6_7; |
828 | uint32_t DWB_OGAM_RAMB_REGION_8_9; |
829 | uint32_t DWB_OGAM_RAMB_REGION_10_11; |
830 | uint32_t DWB_OGAM_RAMB_REGION_12_13; |
831 | uint32_t DWB_OGAM_RAMB_REGION_14_15; |
832 | uint32_t DWB_OGAM_RAMB_REGION_16_17; |
833 | uint32_t DWB_OGAM_RAMB_REGION_18_19; |
834 | uint32_t DWB_OGAM_RAMB_REGION_20_21; |
835 | uint32_t DWB_OGAM_RAMB_REGION_22_23; |
836 | uint32_t DWB_OGAM_RAMB_REGION_24_25; |
837 | uint32_t DWB_OGAM_RAMB_REGION_26_27; |
838 | uint32_t DWB_OGAM_RAMB_REGION_28_29; |
839 | uint32_t DWB_OGAM_RAMB_REGION_30_31; |
840 | uint32_t DWB_OGAM_RAMB_REGION_32_33; |
841 | }; |
842 | |
843 | /* Internal enums / structs */ |
844 | enum dwbscl_coef_filter_type_sel { |
845 | DWBSCL_COEF_RAM_FILTER_TYPE_VERT_RGB = 0, |
846 | DWBSCL_COEF_RAM_FILTER_TYPE_HORZ_RGB = 1 |
847 | }; |
848 | |
849 | |
850 | struct dcn30_dwbc_mask { |
851 | DWBC_REG_FIELD_LIST_DCN3_0(uint32_t); |
852 | }; |
853 | |
854 | struct dcn30_dwbc_shift { |
855 | DWBC_REG_FIELD_LIST_DCN3_0(uint8_t); |
856 | }; |
857 | |
858 | struct dcn30_dwbc { |
859 | struct dwbc base; |
860 | const struct dcn30_dwbc_registers *dwbc_regs; |
861 | const struct dcn30_dwbc_shift *dwbc_shift; |
862 | const struct dcn30_dwbc_mask *dwbc_mask; |
863 | }; |
864 | |
865 | void dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30, |
866 | struct dc_context *ctx, |
867 | const struct dcn30_dwbc_registers *dwbc_regs, |
868 | const struct dcn30_dwbc_shift *dwbc_shift, |
869 | const struct dcn30_dwbc_mask *dwbc_mask, |
870 | int inst); |
871 | |
872 | bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params); |
873 | |
874 | bool dwb3_disable(struct dwbc *dwbc); |
875 | |
876 | bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params); |
877 | |
878 | bool dwb3_is_enabled(struct dwbc *dwbc); |
879 | |
880 | void dwb3_set_stereo(struct dwbc *dwbc, |
881 | struct dwb_stereo_params *stereo_params); |
882 | |
883 | void dwb3_set_new_content(struct dwbc *dwbc, |
884 | bool is_new_content); |
885 | |
886 | void dwb3_config_fc(struct dwbc *dwbc, |
887 | struct dc_dwb_params *params); |
888 | |
889 | void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params); |
890 | |
891 | void dwb3_program_hdr_mult( |
892 | struct dwbc *dwbc, |
893 | const struct dc_dwb_params *params); |
894 | |
895 | void dwb3_set_gamut_remap( |
896 | struct dwbc *dwbc, |
897 | const struct dc_dwb_params *params); |
898 | |
899 | bool dwb3_ogam_set_input_transfer_func( |
900 | struct dwbc *dwbc, |
901 | const struct dc_transfer_func *in_transfer_func_dwb_ogam); |
902 | |
903 | void dwb3_set_host_read_rate_control(struct dwbc *dwbc, bool host_read_delay); |
904 | #endif |
905 | |
906 | |
907 | |