| 1 | // SPDX-License-Identifier: MIT |
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| 2 | /* |
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| 3 | * Copyright (C) 2021 Advanced Micro Devices, Inc. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be included in |
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| 13 | * all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: AMD |
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| 24 | */ |
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| 25 | |
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| 26 | #ifndef __DCN303_DCCG_H__ |
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| 27 | #define __DCN303_DCCG_H__ |
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| 28 | |
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| 29 | #include "dcn30/dcn30_dccg.h" |
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| 30 | |
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| 31 | |
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| 32 | #define DCCG_REG_LIST_DCN3_03() \ |
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| 33 | SR(DPPCLK_DTO_CTRL),\ |
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| 34 | DCCG_SRII(DTO_PARAM, DPPCLK, 0),\ |
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| 35 | DCCG_SRII(DTO_PARAM, DPPCLK, 1),\ |
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| 36 | SR(REFCLK_CNTL),\ |
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| 37 | SR(DISPCLK_FREQ_CHANGE_CNTL),\ |
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| 38 | DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\ |
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| 39 | DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1) |
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| 40 | |
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| 41 | |
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| 42 | #define DCCG_MASK_SH_LIST_DCN3_03(mask_sh) \ |
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| 43 | DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\ |
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| 44 | DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\ |
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| 45 | DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\ |
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| 46 | DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\ |
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| 47 | DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\ |
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| 48 | DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\ |
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| 49 | DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\ |
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| 50 | DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh),\ |
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| 51 | DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_DELAY, mask_sh),\ |
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| 52 | DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_STEP_SIZE, mask_sh),\ |
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| 53 | DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_FREQ_RAMP_DONE, mask_sh),\ |
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| 54 | DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_MAX_ERRDET_CYCLES, mask_sh),\ |
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| 55 | DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_RESET, mask_sh),\ |
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| 56 | DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_STATE, mask_sh),\ |
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| 57 | DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DCCG_FIFO_ERRDET_OVR_EN, mask_sh),\ |
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| 58 | DCCG_SF(DISPCLK_FREQ_CHANGE_CNTL, DISPCLK_CHG_FWD_CORR_DISABLE, mask_sh),\ |
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| 59 | DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\ |
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| 60 | DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\ |
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| 61 | DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\ |
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| 62 | DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh) |
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| 63 | |
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| 64 | #endif //__DCN303_DCCG_H__ |
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| 65 | |
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