1// SPDX-License-Identifier: MIT
2/*
3 * Copyright (C) 2021 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 */
25
26#include "dcn303/dcn303_init.h"
27#include "dcn303_resource.h"
28#include "dcn303/dcn303_dccg.h"
29#include "irq/dcn303/irq_service_dcn303.h"
30
31#include "dcn30/dcn30_dio_link_encoder.h"
32#include "dcn30/dcn30_dio_stream_encoder.h"
33#include "dcn30/dcn30_dpp.h"
34#include "dcn30/dcn30_dwb.h"
35#include "dcn30/dcn30_hubbub.h"
36#include "dcn30/dcn30_hubp.h"
37#include "dcn30/dcn30_mmhubbub.h"
38#include "dcn30/dcn30_mpc.h"
39#include "dcn30/dcn30_opp.h"
40#include "dcn30/dcn30_optc.h"
41#include "dcn30/dcn30_resource.h"
42
43#include "dcn20/dcn20_dsc.h"
44#include "dcn20/dcn20_resource.h"
45
46#include "dml/dcn30/dcn30_fpu.h"
47
48#include "dcn10/dcn10_resource.h"
49
50#include "link.h"
51
52#include "dce/dce_abm.h"
53#include "dce/dce_audio.h"
54#include "dce/dce_aux.h"
55#include "dce/dce_clock_source.h"
56#include "dce/dce_hwseq.h"
57#include "dce/dce_i2c_hw.h"
58#include "dce/dce_panel_cntl.h"
59#include "dce/dmub_abm.h"
60#include "dce/dmub_psr.h"
61#include "clk_mgr.h"
62
63#include "hw_sequencer_private.h"
64#include "reg_helper.h"
65#include "resource.h"
66#include "vm_helper.h"
67
68#include "sienna_cichlid_ip_offset.h"
69#include "dcn/dcn_3_0_3_offset.h"
70#include "dcn/dcn_3_0_3_sh_mask.h"
71#include "dpcs/dpcs_3_0_3_offset.h"
72#include "dpcs/dpcs_3_0_3_sh_mask.h"
73#include "nbio/nbio_2_3_offset.h"
74
75#include "dml/dcn303/dcn303_fpu.h"
76
77#define DC_LOGGER \
78 dc->ctx->logger
79#define DC_LOGGER_INIT(logger)
80
81
82static const struct dc_debug_options debug_defaults_drv = {
83 .disable_dmcu = true,
84 .force_abm_enable = false,
85 .timing_trace = false,
86 .clock_trace = true,
87 .disable_pplib_clock_request = true,
88 .pipe_split_policy = MPC_SPLIT_AVOID,
89 .force_single_disp_pipe_split = false,
90 .disable_dcc = DCC_ENABLE,
91 .vsr_support = true,
92 .performance_trace = false,
93 .max_downscale_src_width = 7680,/*upto 8K*/
94 .disable_pplib_wm_range = false,
95 .scl_reset_length10 = true,
96 .sanity_checks = false,
97 .underflow_assert_delay_us = 0xFFFFFFFF,
98 .dwb_fi_phase = -1, // -1 = disable,
99 .dmub_command_table = true,
100 .exit_idle_opt_for_cursor_updates = true,
101 .disable_idle_power_optimizations = false,
102 .using_dml2 = false,
103};
104
105static const struct dc_panel_config panel_config_defaults = {
106 .psr = {
107 .disable_psr = false,
108 .disallow_psrsu = false,
109 .disallow_replay = false,
110 },
111};
112
113enum dcn303_clk_src_array_id {
114 DCN303_CLK_SRC_PLL0,
115 DCN303_CLK_SRC_PLL1,
116 DCN303_CLK_SRC_TOTAL
117};
118
119static const struct resource_caps res_cap_dcn303 = {
120 .num_timing_generator = 2,
121 .num_opp = 2,
122 .num_video_plane = 2,
123 .num_audio = 2,
124 .num_stream_encoder = 2,
125 .num_dwb = 1,
126 .num_ddc = 2,
127 .num_vmid = 16,
128 .num_mpc_3dlut = 1,
129 .num_dsc = 2,
130};
131
132static const struct dc_plane_cap plane_cap = {
133 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
134 .per_pixel_alpha = true,
135 .pixel_format_support = {
136 .argb8888 = true,
137 .nv12 = true,
138 .fp16 = true,
139 .p010 = true,
140 .ayuv = false,
141 },
142 .max_upscale_factor = {
143 .argb8888 = 16000,
144 .nv12 = 16000,
145 .fp16 = 16000
146 },
147 .max_downscale_factor = {
148 .argb8888 = 600,
149 .nv12 = 600,
150 .fp16 = 600
151 },
152 16,
153 16
154};
155
156/* NBIO */
157#define NBIO_BASE_INNER(seg) \
158 NBIO_BASE__INST0_SEG ## seg
159
160#define NBIO_BASE(seg) \
161 NBIO_BASE_INNER(seg)
162
163#define NBIO_SR(reg_name)\
164 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
165 mm ## reg_name
166
167/* DCN */
168#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
169
170#define BASE(seg) BASE_INNER(seg)
171
172#define SR(reg_name)\
173 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
174
175#define SF(reg_name, field_name, post_fix)\
176 .field_name = reg_name ## __ ## field_name ## post_fix
177
178#define SRI(reg_name, block, id)\
179 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
180
181#define SRI2(reg_name, block, id)\
182 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
183
184#define SRII(reg_name, block, id)\
185 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
186 mm ## block ## id ## _ ## reg_name
187
188#define DCCG_SRII(reg_name, block, id)\
189 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
190 mm ## block ## id ## _ ## reg_name
191
192#define VUPDATE_SRII(reg_name, block, id)\
193 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
194 mm ## reg_name ## _ ## block ## id
195
196#define SRII_DWB(reg_name, temp_name, block, id)\
197 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
198 mm ## block ## id ## _ ## temp_name
199
200#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
201 .field_name = reg_name ## __ ## field_name ## post_fix
202
203#define SRII_MPC_RMU(reg_name, block, id)\
204 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
205 mm ## block ## id ## _ ## reg_name
206
207static const struct dcn_hubbub_registers hubbub_reg = {
208 HUBBUB_REG_LIST_DCN30(0)
209};
210
211static const struct dcn_hubbub_shift hubbub_shift = {
212 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
213};
214
215static const struct dcn_hubbub_mask hubbub_mask = {
216 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
217};
218
219#define vmid_regs(id)\
220 [id] = { DCN20_VMID_REG_LIST(id) }
221
222static const struct dcn_vmid_registers vmid_regs[] = {
223 vmid_regs(0),
224 vmid_regs(1),
225 vmid_regs(2),
226 vmid_regs(3),
227 vmid_regs(4),
228 vmid_regs(5),
229 vmid_regs(6),
230 vmid_regs(7),
231 vmid_regs(8),
232 vmid_regs(9),
233 vmid_regs(10),
234 vmid_regs(11),
235 vmid_regs(12),
236 vmid_regs(13),
237 vmid_regs(14),
238 vmid_regs(15)
239};
240
241static const struct dcn20_vmid_shift vmid_shifts = {
242 DCN20_VMID_MASK_SH_LIST(__SHIFT)
243};
244
245static const struct dcn20_vmid_mask vmid_masks = {
246 DCN20_VMID_MASK_SH_LIST(_MASK)
247};
248
249static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx)
250{
251 int i;
252
253 struct dcn20_hubbub *hubbub3 = kzalloc(size: sizeof(struct dcn20_hubbub), GFP_KERNEL);
254
255 if (!hubbub3)
256 return NULL;
257
258 hubbub3_construct(hubbub3, ctx, hubbub_regs: &hubbub_reg, hubbub_shift: &hubbub_shift, hubbub_mask: &hubbub_mask);
259
260 for (i = 0; i < res_cap_dcn303.num_vmid; i++) {
261 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
262
263 vmid->ctx = ctx;
264
265 vmid->regs = &vmid_regs[i];
266 vmid->shifts = &vmid_shifts;
267 vmid->masks = &vmid_masks;
268 }
269
270 return &hubbub3->base;
271}
272
273#define vpg_regs(id)\
274 [id] = { VPG_DCN3_REG_LIST(id) }
275
276static const struct dcn30_vpg_registers vpg_regs[] = {
277 vpg_regs(0),
278 vpg_regs(1),
279 vpg_regs(2)
280};
281
282static const struct dcn30_vpg_shift vpg_shift = {
283 DCN3_VPG_MASK_SH_LIST(__SHIFT)
284};
285
286static const struct dcn30_vpg_mask vpg_mask = {
287 DCN3_VPG_MASK_SH_LIST(_MASK)
288};
289
290static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)
291{
292 struct dcn30_vpg *vpg3 = kzalloc(size: sizeof(struct dcn30_vpg), GFP_KERNEL);
293
294 if (!vpg3)
295 return NULL;
296
297 vpg3_construct(vpg3, ctx, inst, vpg_regs: &vpg_regs[inst], vpg_shift: &vpg_shift, vpg_mask: &vpg_mask);
298
299 return &vpg3->base;
300}
301
302#define afmt_regs(id)\
303 [id] = { AFMT_DCN3_REG_LIST(id) }
304
305static const struct dcn30_afmt_registers afmt_regs[] = {
306 afmt_regs(0),
307 afmt_regs(1),
308 afmt_regs(2)
309};
310
311static const struct dcn30_afmt_shift afmt_shift = {
312 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
313};
314
315static const struct dcn30_afmt_mask afmt_mask = {
316 DCN3_AFMT_MASK_SH_LIST(_MASK)
317};
318
319static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)
320{
321 struct dcn30_afmt *afmt3 = kzalloc(size: sizeof(struct dcn30_afmt), GFP_KERNEL);
322
323 if (!afmt3)
324 return NULL;
325
326 afmt3_construct(afmt3, ctx, inst, afmt_regs: &afmt_regs[inst], afmt_shift: &afmt_shift, afmt_mask: &afmt_mask);
327
328 return &afmt3->base;
329}
330
331#define audio_regs(id)\
332 [id] = { AUD_COMMON_REG_LIST(id) }
333
334static const struct dce_audio_registers audio_regs[] = {
335 audio_regs(0),
336 audio_regs(1),
337 audio_regs(2),
338 audio_regs(3),
339 audio_regs(4),
340 audio_regs(5),
341 audio_regs(6)
342};
343
344#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
345 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
346 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
347 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
348
349static const struct dce_audio_shift audio_shift = {
350 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
351};
352
353static const struct dce_audio_mask audio_mask = {
354 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
355};
356
357static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst)
358{
359 return dce_audio_create(ctx, inst, reg: &audio_regs[inst], shifts: &audio_shift, masks: &audio_mask);
360}
361
362#define stream_enc_regs(id)\
363 [id] = { SE_DCN3_REG_LIST(id) }
364
365static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
366 stream_enc_regs(0),
367 stream_enc_regs(1)
368};
369
370static const struct dcn10_stream_encoder_shift se_shift = {
371 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
372};
373
374static const struct dcn10_stream_encoder_mask se_mask = {
375 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
376};
377
378static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
379{
380 struct dcn10_stream_encoder *enc1;
381 struct vpg *vpg;
382 struct afmt *afmt;
383 int vpg_inst;
384 int afmt_inst;
385
386 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
387 if (eng_id <= ENGINE_ID_DIGB) {
388 vpg_inst = eng_id;
389 afmt_inst = eng_id;
390 } else
391 return NULL;
392
393 enc1 = kzalloc(size: sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
394 vpg = dcn303_vpg_create(ctx, inst: vpg_inst);
395 afmt = dcn303_afmt_create(ctx, inst: afmt_inst);
396
397 if (!enc1 || !vpg || !afmt) {
398 kfree(objp: enc1);
399 kfree(objp: vpg);
400 kfree(objp: afmt);
401 return NULL;
402 }
403
404 dcn30_dio_stream_encoder_construct(enc1, ctx, bp: ctx->dc_bios, eng_id, vpg, afmt, regs: &stream_enc_regs[eng_id],
405 se_shift: &se_shift, se_mask: &se_mask);
406
407 return &enc1->base;
408}
409
410#define clk_src_regs(index, pllid)\
411 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) }
412
413static const struct dce110_clk_src_regs clk_src_regs[] = {
414 clk_src_regs(0, A),
415 clk_src_regs(1, B)
416};
417
418static const struct dce110_clk_src_shift cs_shift = {
419 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
420};
421
422static const struct dce110_clk_src_mask cs_mask = {
423 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
424};
425
426static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
427 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
428{
429 struct dce110_clk_src *clk_src = kzalloc(size: sizeof(struct dce110_clk_src), GFP_KERNEL);
430
431 if (!clk_src)
432 return NULL;
433
434 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift: &cs_shift, cs_mask: &cs_mask)) {
435 clk_src->base.dp_clk_src = dp_clk_src;
436 return &clk_src->base;
437 }
438
439 kfree(objp: clk_src);
440 BREAK_TO_DEBUGGER();
441 return NULL;
442}
443
444static const struct dce_hwseq_registers hwseq_reg = {
445 HWSEQ_DCN303_REG_LIST()
446};
447
448static const struct dce_hwseq_shift hwseq_shift = {
449 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT)
450};
451
452static const struct dce_hwseq_mask hwseq_mask = {
453 HWSEQ_DCN303_MASK_SH_LIST(_MASK)
454};
455
456static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx)
457{
458 struct dce_hwseq *hws = kzalloc(size: sizeof(struct dce_hwseq), GFP_KERNEL);
459
460 if (hws) {
461 hws->ctx = ctx;
462 hws->regs = &hwseq_reg;
463 hws->shifts = &hwseq_shift;
464 hws->masks = &hwseq_mask;
465 }
466 return hws;
467}
468
469#define hubp_regs(id)\
470 [id] = { HUBP_REG_LIST_DCN30(id) }
471
472static const struct dcn_hubp2_registers hubp_regs[] = {
473 hubp_regs(0),
474 hubp_regs(1)
475};
476
477static const struct dcn_hubp2_shift hubp_shift = {
478 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
479};
480
481static const struct dcn_hubp2_mask hubp_mask = {
482 HUBP_MASK_SH_LIST_DCN30(_MASK)
483};
484
485static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)
486{
487 struct dcn20_hubp *hubp2 = kzalloc(size: sizeof(struct dcn20_hubp), GFP_KERNEL);
488
489 if (!hubp2)
490 return NULL;
491
492 if (hubp3_construct(hubp2, ctx, inst, hubp_regs: &hubp_regs[inst], hubp_shift: &hubp_shift, hubp_mask: &hubp_mask))
493 return &hubp2->base;
494
495 BREAK_TO_DEBUGGER();
496 kfree(objp: hubp2);
497 return NULL;
498}
499
500#define dpp_regs(id)\
501 [id] = { DPP_REG_LIST_DCN30(id) }
502
503static const struct dcn3_dpp_registers dpp_regs[] = {
504 dpp_regs(0),
505 dpp_regs(1)
506};
507
508static const struct dcn3_dpp_shift tf_shift = {
509 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
510};
511
512static const struct dcn3_dpp_mask tf_mask = {
513 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
514};
515
516static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)
517{
518 struct dcn3_dpp *dpp = kzalloc(size: sizeof(struct dcn3_dpp), GFP_KERNEL);
519
520 if (!dpp)
521 return NULL;
522
523 if (dpp3_construct(dpp3: dpp, ctx, inst, tf_regs: &dpp_regs[inst], tf_shift: &tf_shift, tf_mask: &tf_mask))
524 return &dpp->base;
525
526 BREAK_TO_DEBUGGER();
527 kfree(objp: dpp);
528 return NULL;
529}
530
531#define opp_regs(id)\
532 [id] = { OPP_REG_LIST_DCN30(id) }
533
534static const struct dcn20_opp_registers opp_regs[] = {
535 opp_regs(0),
536 opp_regs(1)
537};
538
539static const struct dcn20_opp_shift opp_shift = {
540 OPP_MASK_SH_LIST_DCN20(__SHIFT)
541};
542
543static const struct dcn20_opp_mask opp_mask = {
544 OPP_MASK_SH_LIST_DCN20(_MASK)
545};
546
547static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)
548{
549 struct dcn20_opp *opp = kzalloc(size: sizeof(struct dcn20_opp), GFP_KERNEL);
550
551 if (!opp) {
552 BREAK_TO_DEBUGGER();
553 return NULL;
554 }
555
556 dcn20_opp_construct(oppn20: opp, ctx, inst, regs: &opp_regs[inst], opp_shift: &opp_shift, opp_mask: &opp_mask);
557 return &opp->base;
558}
559
560#define optc_regs(id)\
561 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
562
563static const struct dcn_optc_registers optc_regs[] = {
564 optc_regs(0),
565 optc_regs(1)
566};
567
568static const struct dcn_optc_shift optc_shift = {
569 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
570};
571
572static const struct dcn_optc_mask optc_mask = {
573 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
574};
575
576static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance)
577{
578 struct optc *tgn10 = kzalloc(size: sizeof(struct optc), GFP_KERNEL);
579
580 if (!tgn10)
581 return NULL;
582
583 tgn10->base.inst = instance;
584 tgn10->base.ctx = ctx;
585
586 tgn10->tg_regs = &optc_regs[instance];
587 tgn10->tg_shift = &optc_shift;
588 tgn10->tg_mask = &optc_mask;
589
590 dcn30_timing_generator_init(optc1: tgn10);
591
592 return &tgn10->base;
593}
594
595static const struct dcn30_mpc_registers mpc_regs = {
596 MPC_REG_LIST_DCN3_0(0),
597 MPC_REG_LIST_DCN3_0(1),
598 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
599 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
600 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
601 MPC_RMU_REG_LIST_DCN3AG(0),
602 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
603};
604
605static const struct dcn30_mpc_shift mpc_shift = {
606 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT)
607};
608
609static const struct dcn30_mpc_mask mpc_mask = {
610 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK)
611};
612
613static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
614{
615 struct dcn30_mpc *mpc30 = kzalloc(size: sizeof(struct dcn30_mpc), GFP_KERNEL);
616
617 if (!mpc30)
618 return NULL;
619
620 dcn30_mpc_construct(mpc30, ctx, mpc_regs: &mpc_regs, mpc_shift: &mpc_shift, mpc_mask: &mpc_mask, num_mpcc, num_rmu);
621
622 return &mpc30->base;
623}
624
625#define dsc_regsDCN20(id)\
626[id] = { DSC_REG_LIST_DCN20(id) }
627
628static const struct dcn20_dsc_registers dsc_regs[] = {
629 dsc_regsDCN20(0),
630 dsc_regsDCN20(1)
631};
632
633static const struct dcn20_dsc_shift dsc_shift = {
634 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
635};
636
637static const struct dcn20_dsc_mask dsc_mask = {
638 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
639};
640
641static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)
642{
643 struct dcn20_dsc *dsc = kzalloc(size: sizeof(struct dcn20_dsc), GFP_KERNEL);
644
645 if (!dsc) {
646 BREAK_TO_DEBUGGER();
647 return NULL;
648 }
649
650 dsc2_construct(dsc, ctx, inst, dsc_regs: &dsc_regs[inst], dsc_shift: &dsc_shift, dsc_mask: &dsc_mask);
651 return &dsc->base;
652}
653
654#define dwbc_regs_dcn3(id)\
655[id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
656
657static const struct dcn30_dwbc_registers dwbc30_regs[] = {
658 dwbc_regs_dcn3(0)
659};
660
661static const struct dcn30_dwbc_shift dwbc30_shift = {
662 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
663};
664
665static const struct dcn30_dwbc_mask dwbc30_mask = {
666 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
667};
668
669static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
670{
671 int i;
672 uint32_t pipe_count = pool->res_cap->num_dwb;
673
674 for (i = 0; i < pipe_count; i++) {
675 struct dcn30_dwbc *dwbc30 = kzalloc(size: sizeof(struct dcn30_dwbc), GFP_KERNEL);
676
677 if (!dwbc30) {
678 dm_error("DC: failed to create dwbc30!\n");
679 return false;
680 }
681
682 dcn30_dwbc_construct(dwbc30, ctx, dwbc_regs: &dwbc30_regs[i], dwbc_shift: &dwbc30_shift, dwbc_mask: &dwbc30_mask, inst: i);
683
684 pool->dwbc[i] = &dwbc30->base;
685 }
686 return true;
687}
688
689#define mcif_wb_regs_dcn3(id)\
690[id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
691
692static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
693 mcif_wb_regs_dcn3(0)
694};
695
696static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
697 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
698};
699
700static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
701 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
702};
703
704static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
705{
706 int i;
707 uint32_t pipe_count = pool->res_cap->num_dwb;
708
709 for (i = 0; i < pipe_count; i++) {
710 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(size: sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
711
712 if (!mcif_wb30) {
713 dm_error("DC: failed to create mcif_wb30!\n");
714 return false;
715 }
716
717 dcn30_mmhubbub_construct(mcif_wb30, ctx, mcif_wb_regs: &mcif_wb30_regs[i], mcif_wb_shift: &mcif_wb30_shift, mcif_wb_mask: &mcif_wb30_mask, inst: i);
718
719 pool->mcif_wb[i] = &mcif_wb30->base;
720 }
721 return true;
722}
723
724#define aux_engine_regs(id)\
725[id] = {\
726 AUX_COMMON_REG_LIST0(id), \
727 .AUXN_IMPCAL = 0, \
728 .AUXP_IMPCAL = 0, \
729 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
730}
731
732static const struct dce110_aux_registers aux_engine_regs[] = {
733 aux_engine_regs(0),
734 aux_engine_regs(1)
735};
736
737static const struct dce110_aux_registers_shift aux_shift = {
738 DCN_AUX_MASK_SH_LIST(__SHIFT)
739};
740
741static const struct dce110_aux_registers_mask aux_mask = {
742 DCN_AUX_MASK_SH_LIST(_MASK)
743};
744
745static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)
746{
747 struct aux_engine_dce110 *aux_engine = kzalloc(size: sizeof(struct aux_engine_dce110), GFP_KERNEL);
748
749 if (!aux_engine)
750 return NULL;
751
752 dce110_aux_engine_construct(aux_engine110: aux_engine, ctx, inst, timeout_period: SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
753 regs: &aux_engine_regs[inst], mask: &aux_mask, shift: &aux_shift, is_ext_aux_timeout_configurable: ctx->dc->caps.extended_aux_timeout_support);
754
755 return &aux_engine->base;
756}
757
758#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
759
760static const struct dce_i2c_registers i2c_hw_regs[] = {
761 i2c_inst_regs(1),
762 i2c_inst_regs(2)
763};
764
765static const struct dce_i2c_shift i2c_shifts = {
766 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
767};
768
769static const struct dce_i2c_mask i2c_masks = {
770 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
771};
772
773static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
774{
775 struct dce_i2c_hw *dce_i2c_hw = kzalloc(size: sizeof(struct dce_i2c_hw), GFP_KERNEL);
776
777 if (!dce_i2c_hw)
778 return NULL;
779
780 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, engine_id: inst, regs: &i2c_hw_regs[inst], shifts: &i2c_shifts, masks: &i2c_masks);
781
782 return dce_i2c_hw;
783}
784
785static const struct encoder_feature_support link_enc_feature = {
786 .max_hdmi_deep_color = COLOR_DEPTH_121212,
787 .max_hdmi_pixel_clock = 600000,
788 .hdmi_ycbcr420_supported = true,
789 .dp_ycbcr420_supported = true,
790 .fec_supported = true,
791 .flags.bits.IS_HBR2_CAPABLE = true,
792 .flags.bits.IS_HBR3_CAPABLE = true,
793 .flags.bits.IS_TPS3_CAPABLE = true,
794 .flags.bits.IS_TPS4_CAPABLE = true
795};
796
797#define link_regs(id, phyid)\
798 [id] = {\
799 LE_DCN3_REG_LIST(id), \
800 UNIPHY_DCN2_REG_LIST(phyid), \
801 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
802 }
803
804static const struct dcn10_link_enc_registers link_enc_regs[] = {
805 link_regs(0, A),
806 link_regs(1, B)
807};
808
809static const struct dcn10_link_enc_shift le_shift = {
810 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
811 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
812};
813
814static const struct dcn10_link_enc_mask le_mask = {
815 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
816 DPCS_DCN2_MASK_SH_LIST(_MASK)
817};
818
819#define aux_regs(id)\
820 [id] = { DCN2_AUX_REG_LIST(id) }
821
822static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
823 aux_regs(0),
824 aux_regs(1)
825};
826
827#define hpd_regs(id)\
828 [id] = { HPD_REG_LIST(id) }
829
830static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
831 hpd_regs(0),
832 hpd_regs(1)
833};
834
835static struct link_encoder *dcn303_link_encoder_create(
836 struct dc_context *ctx,
837 const struct encoder_init_data *enc_init_data)
838{
839 struct dcn20_link_encoder *enc20 = kzalloc(size: sizeof(struct dcn20_link_encoder), GFP_KERNEL);
840
841 if (!enc20)
842 return NULL;
843
844 dcn30_link_encoder_construct(enc20, init_data: enc_init_data, enc_features: &link_enc_feature,
845 link_regs: &link_enc_regs[enc_init_data->transmitter], aux_regs: &link_enc_aux_regs[enc_init_data->channel - 1],
846 hpd_regs: &link_enc_hpd_regs[enc_init_data->hpd_source], link_shift: &le_shift, link_mask: &le_mask);
847
848 return &enc20->enc10.base;
849}
850
851static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
852 { DCN_PANEL_CNTL_REG_LIST() }
853};
854
855static const struct dce_panel_cntl_shift panel_cntl_shift = {
856 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
857};
858
859static const struct dce_panel_cntl_mask panel_cntl_mask = {
860 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
861};
862
863static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data)
864{
865 struct dce_panel_cntl *panel_cntl = kzalloc(size: sizeof(struct dce_panel_cntl), GFP_KERNEL);
866
867 if (!panel_cntl)
868 return NULL;
869
870 dce_panel_cntl_construct(panel_cntl, init_data, regs: &panel_cntl_regs[init_data->inst],
871 shift: &panel_cntl_shift, mask: &panel_cntl_mask);
872
873 return &panel_cntl->base;
874}
875
876static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
877{
878 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
879 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), field_value: &straps->dc_pinstraps_audio);
880}
881
882static const struct resource_create_funcs res_create_funcs = {
883 .read_dce_straps = read_dce_straps,
884 .create_audio = dcn303_create_audio,
885 .create_stream_encoder = dcn303_stream_encoder_create,
886 .create_hwseq = dcn303_hwseq_create,
887};
888
889static bool is_soc_bounding_box_valid(struct dc *dc)
890{
891 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
892
893 if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev))
894 return true;
895
896 return false;
897}
898
899static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
900{
901 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc;
902 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip;
903
904 DC_LOGGER_INIT(dc->ctx->logger);
905
906 if (!is_soc_bounding_box_valid(dc)) {
907 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
908 return false;
909 }
910
911 loaded_ip->max_num_otg = pool->pipe_count;
912 loaded_ip->max_num_dpp = pool->pipe_count;
913 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
914 DC_FP_START();
915 dcn20_patch_bounding_box(dc, bb: loaded_bb);
916 DC_FP_END();
917
918 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
919 struct bp_soc_bb_info bb_info = { 0 };
920
921 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
922 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
923 DC_FP_START();
924 dcn303_fpu_init_soc_bounding_box(bb_info);
925 DC_FP_END();
926 }
927 }
928
929 return true;
930}
931
932static void dcn303_resource_destruct(struct resource_pool *pool)
933{
934 unsigned int i;
935
936 for (i = 0; i < pool->stream_enc_count; i++) {
937 if (pool->stream_enc[i] != NULL) {
938 if (pool->stream_enc[i]->vpg != NULL) {
939 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
940 pool->stream_enc[i]->vpg = NULL;
941 }
942 if (pool->stream_enc[i]->afmt != NULL) {
943 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
944 pool->stream_enc[i]->afmt = NULL;
945 }
946 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
947 pool->stream_enc[i] = NULL;
948 }
949 }
950
951 for (i = 0; i < pool->res_cap->num_dsc; i++) {
952 if (pool->dscs[i] != NULL)
953 dcn20_dsc_destroy(dsc: &pool->dscs[i]);
954 }
955
956 if (pool->mpc != NULL) {
957 kfree(TO_DCN20_MPC(pool->mpc));
958 pool->mpc = NULL;
959 }
960
961 if (pool->hubbub != NULL) {
962 kfree(objp: pool->hubbub);
963 pool->hubbub = NULL;
964 }
965
966 for (i = 0; i < pool->pipe_count; i++) {
967 if (pool->dpps[i] != NULL) {
968 kfree(TO_DCN20_DPP(pool->dpps[i]));
969 pool->dpps[i] = NULL;
970 }
971
972 if (pool->hubps[i] != NULL) {
973 kfree(TO_DCN20_HUBP(pool->hubps[i]));
974 pool->hubps[i] = NULL;
975 }
976
977 if (pool->irqs != NULL)
978 dal_irq_service_destroy(irq_service: &pool->irqs);
979 }
980
981 for (i = 0; i < pool->res_cap->num_ddc; i++) {
982 if (pool->engines[i] != NULL)
983 dce110_engine_destroy(engine: &pool->engines[i]);
984 if (pool->hw_i2cs[i] != NULL) {
985 kfree(objp: pool->hw_i2cs[i]);
986 pool->hw_i2cs[i] = NULL;
987 }
988 if (pool->sw_i2cs[i] != NULL) {
989 kfree(objp: pool->sw_i2cs[i]);
990 pool->sw_i2cs[i] = NULL;
991 }
992 }
993
994 for (i = 0; i < pool->res_cap->num_opp; i++) {
995 if (pool->opps[i] != NULL)
996 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
997 }
998
999 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1000 if (pool->timing_generators[i] != NULL) {
1001 kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1002 pool->timing_generators[i] = NULL;
1003 }
1004 }
1005
1006 for (i = 0; i < pool->res_cap->num_dwb; i++) {
1007 if (pool->dwbc[i] != NULL) {
1008 kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1009 pool->dwbc[i] = NULL;
1010 }
1011 if (pool->mcif_wb[i] != NULL) {
1012 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1013 pool->mcif_wb[i] = NULL;
1014 }
1015 }
1016
1017 for (i = 0; i < pool->audio_count; i++) {
1018 if (pool->audios[i])
1019 dce_aud_destroy(audio: &pool->audios[i]);
1020 }
1021
1022 for (i = 0; i < pool->clk_src_count; i++) {
1023 if (pool->clock_sources[i] != NULL)
1024 dcn20_clock_source_destroy(clk_src: &pool->clock_sources[i]);
1025 }
1026
1027 if (pool->dp_clock_source != NULL)
1028 dcn20_clock_source_destroy(clk_src: &pool->dp_clock_source);
1029
1030 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1031 if (pool->mpc_lut[i] != NULL) {
1032 dc_3dlut_func_release(lut: pool->mpc_lut[i]);
1033 pool->mpc_lut[i] = NULL;
1034 }
1035 if (pool->mpc_shaper[i] != NULL) {
1036 dc_transfer_func_release(dc_tf: pool->mpc_shaper[i]);
1037 pool->mpc_shaper[i] = NULL;
1038 }
1039 }
1040
1041 for (i = 0; i < pool->pipe_count; i++) {
1042 if (pool->multiple_abms[i] != NULL)
1043 dce_abm_destroy(abm: &pool->multiple_abms[i]);
1044 }
1045
1046 if (pool->psr != NULL)
1047 dmub_psr_destroy(dmub: &pool->psr);
1048
1049 if (pool->dccg != NULL)
1050 dcn_dccg_destroy(dccg: &pool->dccg);
1051
1052 if (pool->oem_device != NULL) {
1053 struct dc *dc = pool->oem_device->ctx->dc;
1054
1055 dc->link_srv->destroy_ddc_service(&pool->oem_device);
1056 }
1057}
1058
1059static void dcn303_destroy_resource_pool(struct resource_pool **pool)
1060{
1061 dcn303_resource_destruct(pool: *pool);
1062 kfree(objp: *pool);
1063 *pool = NULL;
1064}
1065
1066static void dcn303_get_panel_config_defaults(struct dc_panel_config *panel_config)
1067{
1068 *panel_config = panel_config_defaults;
1069}
1070
1071void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1072{
1073 DC_FP_START();
1074 dcn303_fpu_update_bw_bounding_box(dc, bw_params);
1075 DC_FP_END();
1076}
1077
1078static struct resource_funcs dcn303_res_pool_funcs = {
1079 .destroy = dcn303_destroy_resource_pool,
1080 .link_enc_create = dcn303_link_encoder_create,
1081 .panel_cntl_create = dcn303_panel_cntl_create,
1082 .validate_bandwidth = dcn30_validate_bandwidth,
1083 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1084 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1085 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1086 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1087 .release_pipe = dcn20_release_pipe,
1088 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1089 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1090 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1091 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1092 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1093 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1094 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1095 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1096 .update_bw_bounding_box = dcn303_update_bw_bounding_box,
1097 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1098 .get_panel_config_defaults = dcn303_get_panel_config_defaults,
1099};
1100
1101static struct dc_cap_funcs cap_funcs = {
1102 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1103};
1104
1105static const struct bios_registers bios_regs = {
1106 NBIO_SR(BIOS_SCRATCH_3),
1107 NBIO_SR(BIOS_SCRATCH_6)
1108};
1109
1110static const struct dccg_registers dccg_regs = {
1111 DCCG_REG_LIST_DCN3_03()
1112};
1113
1114static const struct dccg_shift dccg_shift = {
1115 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT)
1116};
1117
1118static const struct dccg_mask dccg_mask = {
1119 DCCG_MASK_SH_LIST_DCN3_03(_MASK)
1120};
1121
1122#define abm_regs(id)\
1123 [id] = { ABM_DCN302_REG_LIST(id) }
1124
1125static const struct dce_abm_registers abm_regs[] = {
1126 abm_regs(0),
1127 abm_regs(1)
1128};
1129
1130static const struct dce_abm_shift abm_shift = {
1131 ABM_MASK_SH_LIST_DCN30(__SHIFT)
1132};
1133
1134static const struct dce_abm_mask abm_mask = {
1135 ABM_MASK_SH_LIST_DCN30(_MASK)
1136};
1137
1138static bool dcn303_resource_construct(
1139 uint8_t num_virtual_links,
1140 struct dc *dc,
1141 struct resource_pool *pool)
1142{
1143 int i;
1144 struct dc_context *ctx = dc->ctx;
1145 struct irq_service_init_data init_data;
1146 struct ddc_service_init_data ddc_init_data;
1147
1148 ctx->dc_bios->regs = &bios_regs;
1149
1150 pool->res_cap = &res_cap_dcn303;
1151
1152 pool->funcs = &dcn303_res_pool_funcs;
1153
1154 /*************************************************
1155 * Resource + asic cap harcoding *
1156 *************************************************/
1157 pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1158 pool->pipe_count = pool->res_cap->num_timing_generator;
1159 pool->mpcc_count = pool->res_cap->num_timing_generator;
1160 dc->caps.max_downscale_ratio = 600;
1161 dc->caps.i2c_speed_in_khz = 100;
1162 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by derfault*/
1163 dc->caps.max_cursor_size = 256;
1164 dc->caps.min_horizontal_blanking_period = 80;
1165 dc->caps.dmdata_alloc_size = 2048;
1166 dc->caps.mall_size_per_mem_channel = 4;
1167 /* total size = mall per channel * num channels * 1024 * 1024 */
1168 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *
1169 dc->ctx->dc_bios->vram_info.num_chans *
1170 1024 * 1024;
1171 dc->caps.cursor_cache_size =
1172 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1173 dc->caps.max_slave_planes = 1;
1174 dc->caps.post_blend_color_processing = true;
1175 dc->caps.force_dp_tps4_for_cp2520 = true;
1176 dc->caps.extended_aux_timeout_support = true;
1177 dc->caps.dmcub_support = true;
1178 dc->caps.max_v_total = (1 << 15) - 1;
1179
1180 /* Color pipeline capabilities */
1181 dc->caps.color.dpp.dcn_arch = 1;
1182 dc->caps.color.dpp.input_lut_shared = 0;
1183 dc->caps.color.dpp.icsc = 1;
1184 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1185 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1186 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1187 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1188 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1189 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1190 dc->caps.color.dpp.post_csc = 1;
1191 dc->caps.color.dpp.gamma_corr = 1;
1192 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1193
1194 dc->caps.color.dpp.hw_3d_lut = 1;
1195 dc->caps.color.dpp.ogam_ram = 1;
1196 // no OGAM ROM on DCN3
1197 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1198 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1199 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1200 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1201 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1202 dc->caps.color.dpp.ocsc = 0;
1203
1204 dc->caps.color.mpc.gamut_remap = 1;
1205 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
1206 dc->caps.color.mpc.ogam_ram = 1;
1207 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1208 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1209 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1210 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1211 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1212 dc->caps.color.mpc.ocsc = 1;
1213
1214 dc->caps.dp_hdmi21_pcon_support = true;
1215
1216 dc->config.dc_mode_clk_limit_support = true;
1217 /* read VBIOS LTTPR caps */
1218 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1219 enum bp_result bp_query_result;
1220 uint8_t is_vbios_lttpr_enable = 0;
1221
1222 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1223 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1224 }
1225
1226 if (ctx->dc_bios->funcs->get_lttpr_interop) {
1227 enum bp_result bp_query_result;
1228 uint8_t is_vbios_interop_enabled = 0;
1229
1230 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios, &is_vbios_interop_enabled);
1231 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
1232 }
1233
1234 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1235 dc->debug = debug_defaults_drv;
1236
1237 // Init the vm_helper
1238 if (dc->vm_helper)
1239 vm_helper_init(vm_helper: dc->vm_helper, num_vmid: 16);
1240
1241 /*************************************************
1242 * Create resources *
1243 *************************************************/
1244
1245 /* Clock Sources for Pixel Clock*/
1246 pool->clock_sources[DCN303_CLK_SRC_PLL0] =
1247 dcn303_clock_source_create(ctx, bios: ctx->dc_bios,
1248 id: CLOCK_SOURCE_COMBO_PHY_PLL0,
1249 regs: &clk_src_regs[0], dp_clk_src: false);
1250 pool->clock_sources[DCN303_CLK_SRC_PLL1] =
1251 dcn303_clock_source_create(ctx, bios: ctx->dc_bios,
1252 id: CLOCK_SOURCE_COMBO_PHY_PLL1,
1253 regs: &clk_src_regs[1], dp_clk_src: false);
1254
1255 pool->clk_src_count = DCN303_CLK_SRC_TOTAL;
1256
1257 /* todo: not reuse phy_pll registers */
1258 pool->dp_clock_source =
1259 dcn303_clock_source_create(ctx, bios: ctx->dc_bios,
1260 id: CLOCK_SOURCE_ID_DP_DTO,
1261 regs: &clk_src_regs[0], dp_clk_src: true);
1262
1263 for (i = 0; i < pool->clk_src_count; i++) {
1264 if (pool->clock_sources[i] == NULL) {
1265 dm_error("DC: failed to create clock sources!\n");
1266 BREAK_TO_DEBUGGER();
1267 goto create_fail;
1268 }
1269 }
1270
1271 /* DCCG */
1272 pool->dccg = dccg30_create(ctx, regs: &dccg_regs, dccg_shift: &dccg_shift, dccg_mask: &dccg_mask);
1273 if (pool->dccg == NULL) {
1274 dm_error("DC: failed to create dccg!\n");
1275 BREAK_TO_DEBUGGER();
1276 goto create_fail;
1277 }
1278
1279 /* PP Lib and SMU interfaces */
1280 init_soc_bounding_box(dc, pool);
1281
1282 /* DML */
1283 dml_init_instance(lib: &dc->dml, soc_bb: &dcn3_03_soc, ip_params: &dcn3_03_ip, project: DML_PROJECT_DCN30);
1284
1285 /* IRQ */
1286 init_data.ctx = dc->ctx;
1287 pool->irqs = dal_irq_service_dcn303_create(init_data: &init_data);
1288 if (!pool->irqs)
1289 goto create_fail;
1290
1291 /* HUBBUB */
1292 pool->hubbub = dcn303_hubbub_create(ctx);
1293 if (pool->hubbub == NULL) {
1294 BREAK_TO_DEBUGGER();
1295 dm_error("DC: failed to create hubbub!\n");
1296 goto create_fail;
1297 }
1298
1299 /* HUBPs, DPPs, OPPs and TGs */
1300 for (i = 0; i < pool->pipe_count; i++) {
1301 pool->hubps[i] = dcn303_hubp_create(ctx, inst: i);
1302 if (pool->hubps[i] == NULL) {
1303 BREAK_TO_DEBUGGER();
1304 dm_error("DC: failed to create hubps!\n");
1305 goto create_fail;
1306 }
1307
1308 pool->dpps[i] = dcn303_dpp_create(ctx, inst: i);
1309 if (pool->dpps[i] == NULL) {
1310 BREAK_TO_DEBUGGER();
1311 dm_error("DC: failed to create dpps!\n");
1312 goto create_fail;
1313 }
1314 }
1315
1316 for (i = 0; i < pool->res_cap->num_opp; i++) {
1317 pool->opps[i] = dcn303_opp_create(ctx, inst: i);
1318 if (pool->opps[i] == NULL) {
1319 BREAK_TO_DEBUGGER();
1320 dm_error("DC: failed to create output pixel processor!\n");
1321 goto create_fail;
1322 }
1323 }
1324
1325 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1326 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, instance: i);
1327 if (pool->timing_generators[i] == NULL) {
1328 BREAK_TO_DEBUGGER();
1329 dm_error("DC: failed to create tg!\n");
1330 goto create_fail;
1331 }
1332 }
1333 pool->timing_generator_count = i;
1334
1335 /* PSR */
1336 pool->psr = dmub_psr_create(ctx);
1337 if (pool->psr == NULL) {
1338 dm_error("DC: failed to create psr!\n");
1339 BREAK_TO_DEBUGGER();
1340 goto create_fail;
1341 }
1342
1343 /* ABM */
1344 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1345 pool->multiple_abms[i] = dmub_abm_create(ctx, regs: &abm_regs[i], abm_shift: &abm_shift, abm_mask: &abm_mask);
1346 if (pool->multiple_abms[i] == NULL) {
1347 dm_error("DC: failed to create abm for pipe %d!\n", i);
1348 BREAK_TO_DEBUGGER();
1349 goto create_fail;
1350 }
1351 }
1352
1353 /* MPC and DSC */
1354 pool->mpc = dcn303_mpc_create(ctx, num_mpcc: pool->mpcc_count, num_rmu: pool->res_cap->num_mpc_3dlut);
1355 if (pool->mpc == NULL) {
1356 BREAK_TO_DEBUGGER();
1357 dm_error("DC: failed to create mpc!\n");
1358 goto create_fail;
1359 }
1360
1361 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1362 pool->dscs[i] = dcn303_dsc_create(ctx, inst: i);
1363 if (pool->dscs[i] == NULL) {
1364 BREAK_TO_DEBUGGER();
1365 dm_error("DC: failed to create display stream compressor %d!\n", i);
1366 goto create_fail;
1367 }
1368 }
1369
1370 /* DWB and MMHUBBUB */
1371 if (!dcn303_dwbc_create(ctx, pool)) {
1372 BREAK_TO_DEBUGGER();
1373 dm_error("DC: failed to create dwbc!\n");
1374 goto create_fail;
1375 }
1376
1377 if (!dcn303_mmhubbub_create(ctx, pool)) {
1378 BREAK_TO_DEBUGGER();
1379 dm_error("DC: failed to create mcif_wb!\n");
1380 goto create_fail;
1381 }
1382
1383 /* AUX and I2C */
1384 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1385 pool->engines[i] = dcn303_aux_engine_create(ctx, inst: i);
1386 if (pool->engines[i] == NULL) {
1387 BREAK_TO_DEBUGGER();
1388 dm_error("DC:failed to create aux engine!!\n");
1389 goto create_fail;
1390 }
1391 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, inst: i);
1392 if (pool->hw_i2cs[i] == NULL) {
1393 BREAK_TO_DEBUGGER();
1394 dm_error("DC:failed to create hw i2c!!\n");
1395 goto create_fail;
1396 }
1397 pool->sw_i2cs[i] = NULL;
1398 }
1399
1400 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
1401 if (!resource_construct(num_virtual_links, dc, pool,
1402 create_funcs: &res_create_funcs))
1403 goto create_fail;
1404
1405 /* HW Sequencer and Plane caps */
1406 dcn303_hw_sequencer_construct(dc);
1407
1408 dc->caps.max_planes = pool->pipe_count;
1409
1410 for (i = 0; i < dc->caps.max_planes; ++i)
1411 dc->caps.planes[i] = plane_cap;
1412
1413 dc->cap_funcs = cap_funcs;
1414
1415 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1416 ddc_init_data.ctx = dc->ctx;
1417 ddc_init_data.link = NULL;
1418 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1419 ddc_init_data.id.enum_id = 0;
1420 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1421 pool->oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
1422 } else {
1423 pool->oem_device = NULL;
1424 }
1425
1426 return true;
1427
1428create_fail:
1429
1430 dcn303_resource_destruct(pool);
1431
1432 return false;
1433}
1434
1435struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1436{
1437 struct resource_pool *pool = kzalloc(size: sizeof(struct resource_pool), GFP_KERNEL);
1438
1439 if (!pool)
1440 return NULL;
1441
1442 if (dcn303_resource_construct(num_virtual_links: init_data->num_virtual_links, dc, pool))
1443 return pool;
1444
1445 BREAK_TO_DEBUGGER();
1446 kfree(objp: pool);
1447 return NULL;
1448}
1449

source code of linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c