1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DC_STREAM_ENCODER_DCN10_H__
27#define __DC_STREAM_ENCODER_DCN10_H__
28
29#include "stream_encoder.h"
30
31#define DCN10STRENC_FROM_STRENC(stream_encoder)\
32 container_of(stream_encoder, struct dcn10_stream_encoder, base)
33
34#define SE_COMMON_DCN_REG_LIST(id) \
35 SRI(AFMT_CNTL, DIG, id), \
36 SRI(AFMT_GENERIC_0, DIG, id), \
37 SRI(AFMT_GENERIC_1, DIG, id), \
38 SRI(AFMT_GENERIC_2, DIG, id), \
39 SRI(AFMT_GENERIC_3, DIG, id), \
40 SRI(AFMT_GENERIC_4, DIG, id), \
41 SRI(AFMT_GENERIC_5, DIG, id), \
42 SRI(AFMT_GENERIC_6, DIG, id), \
43 SRI(AFMT_GENERIC_7, DIG, id), \
44 SRI(AFMT_GENERIC_HDR, DIG, id), \
45 SRI(AFMT_INFOFRAME_CONTROL0, DIG, id), \
46 SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
47 SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id), \
48 SRI(AFMT_AUDIO_PACKET_CONTROL, DIG, id), \
49 SRI(AFMT_AUDIO_PACKET_CONTROL2, DIG, id), \
50 SRI(AFMT_AUDIO_SRC_CONTROL, DIG, id), \
51 SRI(AFMT_60958_0, DIG, id), \
52 SRI(AFMT_60958_1, DIG, id), \
53 SRI(AFMT_60958_2, DIG, id), \
54 SRI(DIG_FE_CNTL, DIG, id), \
55 SRI(DIG_FIFO_STATUS, DIG, id), \
56 SRI(HDMI_CONTROL, DIG, id), \
57 SRI(HDMI_DB_CONTROL, DIG, id), \
58 SRI(HDMI_GC, DIG, id), \
59 SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
60 SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
61 SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
62 SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
63 SRI(HDMI_INFOFRAME_CONTROL0, DIG, id), \
64 SRI(HDMI_INFOFRAME_CONTROL1, DIG, id), \
65 SRI(HDMI_VBI_PACKET_CONTROL, DIG, id), \
66 SRI(HDMI_AUDIO_PACKET_CONTROL, DIG, id),\
67 SRI(HDMI_ACR_PACKET_CONTROL, DIG, id),\
68 SRI(HDMI_ACR_32_0, DIG, id),\
69 SRI(HDMI_ACR_32_1, DIG, id),\
70 SRI(HDMI_ACR_44_0, DIG, id),\
71 SRI(HDMI_ACR_44_1, DIG, id),\
72 SRI(HDMI_ACR_48_0, DIG, id),\
73 SRI(HDMI_ACR_48_1, DIG, id),\
74 SRI(DP_DB_CNTL, DP, id), \
75 SRI(DP_MSA_MISC, DP, id), \
76 SRI(DP_MSA_VBID_MISC, DP, id), \
77 SRI(DP_MSA_COLORIMETRY, DP, id), \
78 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
79 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
80 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
82 SRI(DP_MSE_RATE_CNTL, DP, id), \
83 SRI(DP_MSE_RATE_UPDATE, DP, id), \
84 SRI(DP_PIXEL_FORMAT, DP, id), \
85 SRI(DP_SEC_CNTL, DP, id), \
86 SRI(DP_SEC_CNTL1, DP, id), \
87 SRI(DP_SEC_CNTL2, DP, id), \
88 SRI(DP_SEC_CNTL5, DP, id), \
89 SRI(DP_SEC_CNTL6, DP, id), \
90 SRI(DP_STEER_FIFO, DP, id), \
91 SRI(DP_VID_M, DP, id), \
92 SRI(DP_VID_N, DP, id), \
93 SRI(DP_VID_STREAM_CNTL, DP, id), \
94 SRI(DP_VID_TIMING, DP, id), \
95 SRI(DP_SEC_AUD_N, DP, id), \
96 SRI(DP_SEC_AUD_N_READBACK, DP, id), \
97 SRI(DP_SEC_AUD_M_READBACK, DP, id), \
98 SRI(DP_SEC_TIMESTAMP, DP, id), \
99 SRI(DIG_CLOCK_PATTERN, DIG, id)
100
101#define SE_DCN_REG_LIST(id)\
102 SE_COMMON_DCN_REG_LIST(id)
103
104
105struct dcn10_stream_enc_registers {
106 uint32_t AFMT_CNTL;
107 uint32_t AFMT_AVI_INFO0;
108 uint32_t AFMT_AVI_INFO1;
109 uint32_t AFMT_AVI_INFO2;
110 uint32_t AFMT_AVI_INFO3;
111 uint32_t AFMT_GENERIC_0;
112 uint32_t AFMT_GENERIC_1;
113 uint32_t AFMT_GENERIC_2;
114 uint32_t AFMT_GENERIC_3;
115 uint32_t AFMT_GENERIC_4;
116 uint32_t AFMT_GENERIC_5;
117 uint32_t AFMT_GENERIC_6;
118 uint32_t AFMT_GENERIC_7;
119 uint32_t AFMT_GENERIC_HDR;
120 uint32_t AFMT_INFOFRAME_CONTROL0;
121 uint32_t AFMT_VBI_PACKET_CONTROL;
122 uint32_t AFMT_VBI_PACKET_CONTROL1;
123 uint32_t AFMT_AUDIO_PACKET_CONTROL;
124 uint32_t AFMT_AUDIO_PACKET_CONTROL2;
125 uint32_t AFMT_AUDIO_SRC_CONTROL;
126 uint32_t AFMT_60958_0;
127 uint32_t AFMT_60958_1;
128 uint32_t AFMT_60958_2;
129 uint32_t DIG_FE_CNTL;
130 uint32_t DIG_FE_CNTL2;
131 uint32_t DIG_FIFO_STATUS;
132 uint32_t DP_MSE_RATE_CNTL;
133 uint32_t DP_MSE_RATE_UPDATE;
134 uint32_t DP_PIXEL_FORMAT;
135 uint32_t DP_SEC_CNTL;
136 uint32_t DP_SEC_CNTL1;
137 uint32_t DP_SEC_CNTL2;
138 uint32_t DP_SEC_CNTL5;
139 uint32_t DP_SEC_CNTL6;
140 uint32_t DP_STEER_FIFO;
141 uint32_t DP_VID_M;
142 uint32_t DP_VID_N;
143 uint32_t DP_VID_STREAM_CNTL;
144 uint32_t DP_VID_TIMING;
145 uint32_t DP_SEC_AUD_N;
146 uint32_t DP_SEC_AUD_N_READBACK;
147 uint32_t DP_SEC_AUD_M_READBACK;
148 uint32_t DP_SEC_TIMESTAMP;
149 uint32_t HDMI_CONTROL;
150 uint32_t HDMI_GC;
151 uint32_t HDMI_GENERIC_PACKET_CONTROL0;
152 uint32_t HDMI_GENERIC_PACKET_CONTROL1;
153 uint32_t HDMI_GENERIC_PACKET_CONTROL2;
154 uint32_t HDMI_GENERIC_PACKET_CONTROL3;
155 uint32_t HDMI_GENERIC_PACKET_CONTROL4;
156 uint32_t HDMI_GENERIC_PACKET_CONTROL5;
157 uint32_t HDMI_INFOFRAME_CONTROL0;
158 uint32_t HDMI_INFOFRAME_CONTROL1;
159 uint32_t HDMI_VBI_PACKET_CONTROL;
160 uint32_t HDMI_AUDIO_PACKET_CONTROL;
161 uint32_t HDMI_ACR_PACKET_CONTROL;
162 uint32_t HDMI_ACR_32_0;
163 uint32_t HDMI_ACR_32_1;
164 uint32_t HDMI_ACR_44_0;
165 uint32_t HDMI_ACR_44_1;
166 uint32_t HDMI_ACR_48_0;
167 uint32_t HDMI_ACR_48_1;
168 uint32_t DP_DB_CNTL;
169 uint32_t DP_MSA_MISC;
170 uint32_t DP_MSA_VBID_MISC;
171 uint32_t DP_MSA_COLORIMETRY;
172 uint32_t DP_MSA_TIMING_PARAM1;
173 uint32_t DP_MSA_TIMING_PARAM2;
174 uint32_t DP_MSA_TIMING_PARAM3;
175 uint32_t DP_MSA_TIMING_PARAM4;
176 uint32_t HDMI_DB_CONTROL;
177 uint32_t DP_DSC_CNTL;
178 uint32_t DP_DSC_BYTES_PER_PIXEL;
179 uint32_t DME_CONTROL;
180 uint32_t DP_SEC_METADATA_TRANSMISSION;
181 uint32_t HDMI_METADATA_PACKET_CONTROL;
182 uint32_t DP_SEC_FRAMING4;
183 uint32_t DP_GSP11_CNTL;
184 uint32_t HDMI_GENERIC_PACKET_CONTROL6;
185 uint32_t HDMI_GENERIC_PACKET_CONTROL7;
186 uint32_t HDMI_GENERIC_PACKET_CONTROL8;
187 uint32_t HDMI_GENERIC_PACKET_CONTROL9;
188 uint32_t HDMI_GENERIC_PACKET_CONTROL10;
189 uint32_t DIG_CLOCK_PATTERN;
190 uint32_t DIG_FIFO_CTRL0;
191 uint32_t DIG_FE_CLK_CNTL;
192 uint32_t DIG_FE_EN_CNTL;
193 uint32_t STREAM_MAPPER_CONTROL;
194};
195
196
197#define SE_SF(reg_name, field_name, post_fix)\
198 .field_name = reg_name ## __ ## field_name ## post_fix
199
200#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\
201 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
202 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\
203 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\
204 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\
205 SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\
206 SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\
207 SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\
208 SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\
209 SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\
210 SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\
211 SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\
212 SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\
213 SE_SF(DIG0_HDMI_CONTROL, HDMI_NO_EXTRA_NULL_PACKET_FILLED, mask_sh),\
214 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\
215 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\
216 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\
217 SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, mask_sh),\
218 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\
219 SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\
220 SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\
221 SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\
222 SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\
223 SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\
224 SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\
225 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\
226 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\
227 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\
228 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\
229 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\
230 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\
231 SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND, mask_sh),\
232 SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_PENDING, mask_sh),\
233 SE_SF(DP0_DP_SEC_CNTL4, DP_SEC_GSP4_LINE_NUM, mask_sh),\
234 SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP4_SEND_ANY_LINE, mask_sh),\
235 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\
236 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\
237 SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\
238 SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\
239 SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
240 SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\
241 SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\
242 SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\
243 SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\
244 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\
245 SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\
246 SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\
247 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\
248 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\
249 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\
250 SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\
251 SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\
252 SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\
253 SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\
254 SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\
255 SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\
256 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
257 SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\
258 SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\
259 SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
260 SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
261 SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\
262 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\
263 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\
264 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\
265 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\
266 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\
267 SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\
268 SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\
269 SE_SF(DP0_DP_SEC_AUD_N_READBACK, DP_SEC_AUD_N_READBACK, mask_sh),\
270 SE_SF(DP0_DP_SEC_AUD_M_READBACK, DP_SEC_AUD_M_READBACK, mask_sh),\
271 SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\
272 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\
273 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\
274 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\
275 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\
276 SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\
277 SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\
278 SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\
279 SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\
280 SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\
281 SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, mask_sh),\
282 SE_SF(DIG0_DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, mask_sh),\
283 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_LEVEL_ERROR, mask_sh),\
284 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_USE_OVERWRITE_LEVEL, mask_sh),\
285 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_OVERWRITE_LEVEL, mask_sh),\
286 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_ERROR_ACK, mask_sh),\
287 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CAL_AVERAGE_LEVEL, mask_sh),\
288 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MAXIMUM_LEVEL, mask_sh),\
289 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_MINIMUM_LEVEL, mask_sh),\
290 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_READ_CLOCK_SRC, mask_sh),\
291 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_CALIBRATED, mask_sh),\
292 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECAL_AVERAGE, mask_sh),\
293 SE_SF(DIG0_DIG_FIFO_STATUS, DIG_FIFO_FORCE_RECOMP_MINMAX, mask_sh),\
294 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\
295 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\
296 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\
297 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\
298 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\
299 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\
300 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\
301 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\
302 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING, mask_sh),\
303 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\
304 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\
305 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\
306 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\
307 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\
308 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
309 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
310 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
311 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\
312 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\
313 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\
314 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\
315 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\
316 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\
317 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\
318 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\
319 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
320 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
321 SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
322 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\
323 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\
324 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\
325 SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\
326 SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_PPS, mask_sh),\
327 SE_SF(DP0_DP_SEC_CNTL2, DP_SEC_GSP7_SEND, mask_sh),\
328 SE_SF(DP0_DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, mask_sh),\
329 SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\
330 SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\
331 SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\
332 SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\
333 SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\
334 SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\
335 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\
336 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\
337 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\
338 SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\
339 SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\
340 SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\
341 SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\
342 SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh),\
343 SE_SF(DIG0_DIG_FE_CNTL, DIG_SOURCE_SELECT, mask_sh),\
344 SE_SF(DIG0_DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, mask_sh)
345
346#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\
347 SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\
348 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\
349 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\
350 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\
351 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\
352 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\
353 SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh)
354
355
356#define SE_REG_FIELD_LIST_DCN1_0(type) \
357 type AFMT_GENERIC_INDEX;\
358 type AFMT_GENERIC_HB0;\
359 type AFMT_GENERIC_HB1;\
360 type AFMT_GENERIC_HB2;\
361 type AFMT_GENERIC_HB3;\
362 type AFMT_GENERIC_LOCK_STATUS;\
363 type AFMT_GENERIC_CONFLICT;\
364 type AFMT_GENERIC_CONFLICT_CLR;\
365 type AFMT_GENERIC0_FRAME_UPDATE_PENDING;\
366 type AFMT_GENERIC1_FRAME_UPDATE_PENDING;\
367 type AFMT_GENERIC2_FRAME_UPDATE_PENDING;\
368 type AFMT_GENERIC3_FRAME_UPDATE_PENDING;\
369 type AFMT_GENERIC4_FRAME_UPDATE_PENDING;\
370 type AFMT_GENERIC4_IMMEDIATE_UPDATE_PENDING;\
371 type AFMT_GENERIC5_FRAME_UPDATE_PENDING;\
372 type AFMT_GENERIC6_FRAME_UPDATE_PENDING;\
373 type AFMT_GENERIC7_FRAME_UPDATE_PENDING;\
374 type AFMT_GENERIC0_FRAME_UPDATE;\
375 type AFMT_GENERIC1_FRAME_UPDATE;\
376 type AFMT_GENERIC2_FRAME_UPDATE;\
377 type AFMT_GENERIC3_FRAME_UPDATE;\
378 type AFMT_GENERIC4_FRAME_UPDATE;\
379 type AFMT_GENERIC0_IMMEDIATE_UPDATE;\
380 type AFMT_GENERIC1_IMMEDIATE_UPDATE;\
381 type AFMT_GENERIC2_IMMEDIATE_UPDATE;\
382 type AFMT_GENERIC3_IMMEDIATE_UPDATE;\
383 type AFMT_GENERIC4_IMMEDIATE_UPDATE;\
384 type AFMT_GENERIC5_IMMEDIATE_UPDATE;\
385 type AFMT_GENERIC6_IMMEDIATE_UPDATE;\
386 type AFMT_GENERIC7_IMMEDIATE_UPDATE;\
387 type AFMT_GENERIC5_FRAME_UPDATE;\
388 type AFMT_GENERIC6_FRAME_UPDATE;\
389 type AFMT_GENERIC7_FRAME_UPDATE;\
390 type HDMI_GENERIC0_CONT;\
391 type HDMI_GENERIC0_SEND;\
392 type HDMI_GENERIC0_LINE;\
393 type HDMI_GENERIC1_CONT;\
394 type HDMI_GENERIC1_SEND;\
395 type HDMI_GENERIC1_LINE;\
396 type HDMI_GENERIC2_CONT;\
397 type HDMI_GENERIC2_SEND;\
398 type HDMI_GENERIC2_LINE;\
399 type HDMI_GENERIC3_CONT;\
400 type HDMI_GENERIC3_SEND;\
401 type HDMI_GENERIC3_LINE;\
402 type HDMI_GENERIC4_CONT;\
403 type HDMI_GENERIC4_SEND;\
404 type HDMI_GENERIC4_LINE;\
405 type HDMI_GENERIC5_CONT;\
406 type HDMI_GENERIC5_SEND;\
407 type HDMI_GENERIC5_LINE;\
408 type HDMI_GENERIC6_CONT;\
409 type HDMI_GENERIC6_SEND;\
410 type HDMI_GENERIC6_LINE;\
411 type HDMI_GENERIC7_CONT;\
412 type HDMI_GENERIC7_SEND;\
413 type HDMI_GENERIC7_LINE;\
414 type DP_PIXEL_ENCODING;\
415 type DP_COMPONENT_DEPTH;\
416 type HDMI_PACKET_GEN_VERSION;\
417 type HDMI_KEEPOUT_MODE;\
418 type HDMI_DEEP_COLOR_ENABLE;\
419 type HDMI_CLOCK_CHANNEL_RATE;\
420 type HDMI_DEEP_COLOR_DEPTH;\
421 type HDMI_GC_CONT;\
422 type HDMI_GC_SEND;\
423 type HDMI_NULL_SEND;\
424 type HDMI_DATA_SCRAMBLE_EN;\
425 type HDMI_NO_EXTRA_NULL_PACKET_FILLED;\
426 type HDMI_AUDIO_INFO_SEND;\
427 type AFMT_AUDIO_INFO_UPDATE;\
428 type HDMI_AUDIO_INFO_LINE;\
429 type HDMI_GC_AVMUTE;\
430 type DP_MSE_RATE_X;\
431 type DP_MSE_RATE_Y;\
432 type DP_MSE_RATE_UPDATE_PENDING;\
433 type DP_SEC_GSP0_ENABLE;\
434 type DP_SEC_STREAM_ENABLE;\
435 type DP_SEC_GSP1_ENABLE;\
436 type DP_SEC_GSP2_ENABLE;\
437 type DP_SEC_GSP3_ENABLE;\
438 type DP_SEC_GSP4_ENABLE;\
439 type DP_SEC_GSP5_ENABLE;\
440 type DP_SEC_GSP5_LINE_NUM;\
441 type DP_SEC_GSP5_LINE_REFERENCE;\
442 type DP_SEC_GSP6_ENABLE;\
443 type DP_SEC_GSP7_ENABLE;\
444 type DP_SEC_GSP7_PPS;\
445 type DP_SEC_GSP7_SEND;\
446 type DP_SEC_GSP4_SEND;\
447 type DP_SEC_GSP4_SEND_PENDING;\
448 type DP_SEC_GSP4_LINE_NUM;\
449 type DP_SEC_GSP4_SEND_ANY_LINE;\
450 type DP_SEC_MPG_ENABLE;\
451 type DP_VID_STREAM_DIS_DEFER;\
452 type DP_VID_STREAM_ENABLE;\
453 type DP_VID_STREAM_STATUS;\
454 type DP_STEER_FIFO_RESET;\
455 type DP_VID_M_N_GEN_EN;\
456 type DP_VID_N;\
457 type DP_VID_M;\
458 type DIG_START;\
459 type AFMT_AUDIO_SRC_SELECT;\
460 type AFMT_AUDIO_CHANNEL_ENABLE;\
461 type HDMI_AUDIO_PACKETS_PER_LINE;\
462 type HDMI_AUDIO_DELAY_EN;\
463 type AFMT_60958_CS_UPDATE;\
464 type AFMT_AUDIO_LAYOUT_OVRD;\
465 type AFMT_60958_OSF_OVRD;\
466 type HDMI_ACR_AUTO_SEND;\
467 type HDMI_ACR_SOURCE;\
468 type HDMI_ACR_AUDIO_PRIORITY;\
469 type HDMI_ACR_CTS_32;\
470 type HDMI_ACR_N_32;\
471 type HDMI_ACR_CTS_44;\
472 type HDMI_ACR_N_44;\
473 type HDMI_ACR_CTS_48;\
474 type HDMI_ACR_N_48;\
475 type AFMT_60958_CS_CHANNEL_NUMBER_L;\
476 type AFMT_60958_CS_CLOCK_ACCURACY;\
477 type AFMT_60958_CS_CHANNEL_NUMBER_R;\
478 type AFMT_60958_CS_CHANNEL_NUMBER_2;\
479 type AFMT_60958_CS_CHANNEL_NUMBER_3;\
480 type AFMT_60958_CS_CHANNEL_NUMBER_4;\
481 type AFMT_60958_CS_CHANNEL_NUMBER_5;\
482 type AFMT_60958_CS_CHANNEL_NUMBER_6;\
483 type AFMT_60958_CS_CHANNEL_NUMBER_7;\
484 type DP_SEC_AUD_N;\
485 type DP_SEC_AUD_N_READBACK;\
486 type DP_SEC_AUD_M_READBACK;\
487 type DP_SEC_TIMESTAMP_MODE;\
488 type DP_SEC_ASP_ENABLE;\
489 type DP_SEC_ATP_ENABLE;\
490 type DP_SEC_AIP_ENABLE;\
491 type DP_SEC_ACM_ENABLE;\
492 type DP_SEC_GSP7_LINE_NUM;\
493 type AFMT_AUDIO_SAMPLE_SEND;\
494 type AFMT_AUDIO_CLOCK_EN;\
495 type TMDS_PIXEL_ENCODING;\
496 type TMDS_COLOR_FORMAT;\
497 type DIG_STEREOSYNC_SELECT;\
498 type DIG_STEREOSYNC_GATE_EN;\
499 type DP_DB_DISABLE;\
500 type DP_MSA_MISC0;\
501 type DP_MSA_HTOTAL;\
502 type DP_MSA_VTOTAL;\
503 type DP_MSA_HSTART;\
504 type DP_MSA_VSTART;\
505 type DP_MSA_HSYNCWIDTH;\
506 type DP_MSA_HSYNCPOLARITY;\
507 type DP_MSA_VSYNCWIDTH;\
508 type DP_MSA_VSYNCPOLARITY;\
509 type DP_MSA_HWIDTH;\
510 type DP_MSA_VHEIGHT;\
511 type HDMI_DB_DISABLE;\
512 type DP_VID_N_MUL;\
513 type DP_VID_M_DOUBLE_VALUE_EN;\
514 type DIG_SOURCE_SELECT;\
515 type DIG_FIFO_LEVEL_ERROR;\
516 type DIG_FIFO_USE_OVERWRITE_LEVEL;\
517 type DIG_FIFO_OVERWRITE_LEVEL;\
518 type DIG_FIFO_ERROR_ACK;\
519 type DIG_FIFO_CAL_AVERAGE_LEVEL;\
520 type DIG_FIFO_MAXIMUM_LEVEL;\
521 type DIG_FIFO_MINIMUM_LEVEL;\
522 type DIG_FIFO_READ_CLOCK_SRC;\
523 type DIG_FIFO_CALIBRATED;\
524 type DIG_FIFO_FORCE_RECAL_AVERAGE;\
525 type DIG_FIFO_FORCE_RECOMP_MINMAX;\
526 type DIG_CLOCK_PATTERN
527
528#define SE_REG_FIELD_LIST_DCN2_0(type) \
529 type DP_DSC_MODE;\
530 type DP_DSC_SLICE_WIDTH;\
531 type DP_DSC_BYTES_PER_PIXEL;\
532 type DP_VBID6_LINE_REFERENCE;\
533 type DP_VBID6_LINE_NUM;\
534 type METADATA_ENGINE_EN;\
535 type METADATA_HUBP_REQUESTOR_ID;\
536 type METADATA_STREAM_TYPE;\
537 type DP_SEC_METADATA_PACKET_ENABLE;\
538 type DP_SEC_METADATA_PACKET_LINE_REFERENCE;\
539 type DP_SEC_METADATA_PACKET_LINE;\
540 type HDMI_METADATA_PACKET_ENABLE;\
541 type HDMI_METADATA_PACKET_LINE_REFERENCE;\
542 type HDMI_METADATA_PACKET_LINE;\
543 type DOLBY_VISION_EN;\
544 type DP_PIXEL_COMBINE;\
545 type DP_SST_SDP_SPLITTING
546
547#define SE_REG_FIELD_LIST_DCN3_0(type) \
548 type HDMI_GENERIC8_CONT;\
549 type HDMI_GENERIC8_SEND;\
550 type HDMI_GENERIC8_LINE;\
551 type HDMI_GENERIC9_CONT;\
552 type HDMI_GENERIC9_SEND;\
553 type HDMI_GENERIC9_LINE;\
554 type HDMI_GENERIC10_CONT;\
555 type HDMI_GENERIC10_SEND;\
556 type HDMI_GENERIC10_LINE;\
557 type HDMI_GENERIC11_CONT;\
558 type HDMI_GENERIC11_SEND;\
559 type HDMI_GENERIC11_LINE;\
560 type HDMI_GENERIC12_CONT;\
561 type HDMI_GENERIC12_SEND;\
562 type HDMI_GENERIC12_LINE;\
563 type HDMI_GENERIC13_CONT;\
564 type HDMI_GENERIC13_SEND;\
565 type HDMI_GENERIC13_LINE;\
566 type HDMI_GENERIC14_CONT;\
567 type HDMI_GENERIC14_SEND;\
568 type HDMI_GENERIC14_LINE;\
569 type DP_SEC_GSP11_PPS;\
570 type DP_SEC_GSP11_ENABLE;\
571 type DP_SEC_GSP11_LINE_NUM
572
573#define SE_REG_FIELD_LIST_DCN3_2(type) \
574 type DIG_FIFO_OUTPUT_PIXEL_MODE;\
575 type DP_PIXEL_PER_CYCLE_PROCESSING_MODE;\
576 type DIG_SYMCLK_FE_ON;\
577 type DIG_FIFO_READ_START_LEVEL;\
578 type DIG_FIFO_ENABLE;\
579 type DIG_FIFO_RESET;\
580 type DIG_FIFO_RESET_DONE;\
581 type PIXEL_ENCODING_TYPE;\
582 type UNCOMPRESSED_PIXEL_FORMAT;\
583 type UNCOMPRESSED_COMPONENT_DEPTH
584
585#define SE_REG_FIELD_LIST_DCN3_5_COMMON(type) \
586 type DIG_FE_CLK_EN;\
587 type DIG_FE_MODE;\
588 type DIG_FE_SOFT_RESET;\
589 type DIG_FE_ENABLE;\
590 type DIG_FE_SYMCLK_FE_G_CLOCK_ON;\
591 type DIG_FE_DISPCLK_G_CLOCK_ON;\
592 type DIG_FE_SYMCLK_FE_G_AFMT_CLOCK_ON;\
593 type DIG_FE_SYMCLK_FE_G_TMDS_CLOCK_ON;\
594 type DIG_FE_SOCCLK_G_AFMT_CLOCK_ON;\
595 type DIG_STREAM_LINK_TARGET
596
597struct dcn10_stream_encoder_shift {
598 SE_REG_FIELD_LIST_DCN1_0(uint8_t);
599 uint8_t HDMI_ACP_SEND;
600 SE_REG_FIELD_LIST_DCN2_0(uint8_t);
601 SE_REG_FIELD_LIST_DCN3_0(uint8_t);
602 SE_REG_FIELD_LIST_DCN3_2(uint8_t);
603 SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t);
604};
605
606struct dcn10_stream_encoder_mask {
607 SE_REG_FIELD_LIST_DCN1_0(uint32_t);
608 uint32_t HDMI_ACP_SEND;
609 SE_REG_FIELD_LIST_DCN2_0(uint32_t);
610 SE_REG_FIELD_LIST_DCN3_0(uint32_t);
611 SE_REG_FIELD_LIST_DCN3_2(uint32_t);
612 SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t);
613};
614
615struct dcn10_stream_encoder {
616 struct stream_encoder base;
617 const struct dcn10_stream_enc_registers *regs;
618 const struct dcn10_stream_encoder_shift *se_shift;
619 const struct dcn10_stream_encoder_mask *se_mask;
620};
621
622void dcn10_stream_encoder_construct(
623 struct dcn10_stream_encoder *enc1,
624 struct dc_context *ctx,
625 struct dc_bios *bp,
626 enum engine_id eng_id,
627 const struct dcn10_stream_enc_registers *regs,
628 const struct dcn10_stream_encoder_shift *se_shift,
629 const struct dcn10_stream_encoder_mask *se_mask);
630
631void enc1_update_generic_info_packet(
632 struct dcn10_stream_encoder *enc1,
633 uint32_t packet_index,
634 const struct dc_info_packet *info_packet);
635
636void enc1_stream_encoder_dp_set_stream_attribute(
637 struct stream_encoder *enc,
638 struct dc_crtc_timing *crtc_timing,
639 enum dc_color_space output_color_space,
640 bool use_vsc_sdp_for_colorimetry,
641 uint32_t enable_sdp_splitting);
642
643void enc1_stream_encoder_hdmi_set_stream_attribute(
644 struct stream_encoder *enc,
645 struct dc_crtc_timing *crtc_timing,
646 int actual_pix_clk_khz,
647 bool enable_audio);
648
649void enc1_stream_encoder_dvi_set_stream_attribute(
650 struct stream_encoder *enc,
651 struct dc_crtc_timing *crtc_timing,
652 bool is_dual_link);
653
654void enc1_stream_encoder_set_throttled_vcp_size(
655 struct stream_encoder *enc,
656 struct fixed31_32 avg_time_slots_per_mtp);
657
658void enc1_stream_encoder_update_dp_info_packets(
659 struct stream_encoder *enc,
660 const struct encoder_info_frame *info_frame);
661
662void enc1_stream_encoder_send_immediate_sdp_message(
663 struct stream_encoder *enc,
664 const uint8_t *custom_sdp_message,
665 unsigned int sdp_message_size);
666
667void enc1_stream_encoder_stop_dp_info_packets(
668 struct stream_encoder *enc);
669
670void enc1_stream_encoder_reset_fifo(
671 struct stream_encoder *enc);
672
673void enc1_stream_encoder_dp_blank(
674 struct dc_link *link,
675 struct stream_encoder *enc);
676
677void enc1_stream_encoder_dp_unblank(
678 struct dc_link *link,
679 struct stream_encoder *enc,
680 const struct encoder_unblank_param *param);
681
682void enc1_setup_stereo_sync(
683 struct stream_encoder *enc,
684 int tg_inst, bool enable);
685
686void enc1_stream_encoder_set_avmute(
687 struct stream_encoder *enc,
688 bool enable);
689
690void enc1_se_audio_mute_control(
691 struct stream_encoder *enc,
692 bool mute);
693
694void enc1_se_dp_audio_setup(
695 struct stream_encoder *enc,
696 unsigned int az_inst,
697 struct audio_info *info);
698
699void enc1_se_dp_audio_enable(
700 struct stream_encoder *enc);
701
702void enc1_se_dp_audio_disable(
703 struct stream_encoder *enc);
704
705void enc1_se_hdmi_audio_setup(
706 struct stream_encoder *enc,
707 unsigned int az_inst,
708 struct audio_info *info,
709 struct audio_crtc_info *audio_crtc_info);
710
711void enc1_se_hdmi_audio_disable(
712 struct stream_encoder *enc);
713
714void enc1_dig_connect_to_otg(
715 struct stream_encoder *enc,
716 int tg_inst);
717
718unsigned int enc1_dig_source_otg(
719 struct stream_encoder *enc);
720
721void enc1_stream_encoder_set_stream_attribute_helper(
722 struct dcn10_stream_encoder *enc1,
723 struct dc_crtc_timing *crtc_timing);
724
725void enc1_se_enable_audio_clock(
726 struct stream_encoder *enc,
727 bool enable);
728
729void enc1_se_enable_dp_audio(
730 struct stream_encoder *enc);
731
732void get_audio_clock_info(
733 enum dc_color_depth color_depth,
734 uint32_t crtc_pixel_clock_100Hz,
735 uint32_t actual_pixel_clock_100Hz,
736 struct audio_clock_info *audio_clock_info);
737
738void enc1_reset_hdmi_stream_attribute(
739 struct stream_encoder *enc);
740
741bool enc1_stream_encoder_dp_get_pixel_format(
742 struct stream_encoder *enc,
743 enum dc_pixel_encoding *encoding,
744 enum dc_color_depth *depth);
745
746#endif /* __DC_STREAM_ENCODER_DCN10_H__ */
747

source code of linux/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h