1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #include "dm_services.h" |
27 | #include "dc.h" |
28 | |
29 | #include "dcn10_init.h" |
30 | |
31 | #include "resource.h" |
32 | #include "include/irq_service_interface.h" |
33 | #include "dcn10_resource.h" |
34 | #include "dcn10_ipp.h" |
35 | #include "dcn10_mpc.h" |
36 | #include "irq/dcn10/irq_service_dcn10.h" |
37 | #include "dcn10_dpp.h" |
38 | #include "dcn10_optc.h" |
39 | #include "dcn10/dcn10_hwseq.h" |
40 | #include "dce110/dce110_hwseq.h" |
41 | #include "dcn10_opp.h" |
42 | #include "dcn10_link_encoder.h" |
43 | #include "dcn10_stream_encoder.h" |
44 | #include "dce/dce_clock_source.h" |
45 | #include "dce/dce_audio.h" |
46 | #include "dce/dce_hwseq.h" |
47 | #include "virtual/virtual_stream_encoder.h" |
48 | #include "dce110/dce110_resource.h" |
49 | #include "dce112/dce112_resource.h" |
50 | #include "dcn10_hubp.h" |
51 | #include "dcn10_hubbub.h" |
52 | #include "dce/dce_panel_cntl.h" |
53 | |
54 | #include "soc15_hw_ip.h" |
55 | #include "vega10_ip_offset.h" |
56 | |
57 | #include "dcn/dcn_1_0_offset.h" |
58 | #include "dcn/dcn_1_0_sh_mask.h" |
59 | |
60 | #include "nbio/nbio_7_0_offset.h" |
61 | |
62 | #include "mmhub/mmhub_9_1_offset.h" |
63 | #include "mmhub/mmhub_9_1_sh_mask.h" |
64 | |
65 | #include "reg_helper.h" |
66 | #include "dce/dce_abm.h" |
67 | #include "dce/dce_dmcu.h" |
68 | #include "dce/dce_aux.h" |
69 | #include "dce/dce_i2c.h" |
70 | |
71 | #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL |
72 | #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f |
73 | #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
74 | #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f |
75 | #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
76 | #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f |
77 | #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
78 | #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f |
79 | #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
80 | #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f |
81 | #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
82 | #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f |
83 | #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
84 | #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f |
85 | #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 |
86 | #endif |
87 | |
88 | |
89 | enum dcn10_clk_src_array_id { |
90 | DCN10_CLK_SRC_PLL0, |
91 | DCN10_CLK_SRC_PLL1, |
92 | DCN10_CLK_SRC_PLL2, |
93 | DCN10_CLK_SRC_PLL3, |
94 | DCN10_CLK_SRC_TOTAL, |
95 | DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3 |
96 | }; |
97 | |
98 | /* begin ********************* |
99 | * macros to expend register list macro defined in HW object header file */ |
100 | |
101 | /* DCN */ |
102 | #define BASE_INNER(seg) \ |
103 | DCE_BASE__INST0_SEG ## seg |
104 | |
105 | #define BASE(seg) \ |
106 | BASE_INNER(seg) |
107 | |
108 | #define SR(reg_name)\ |
109 | .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ |
110 | mm ## reg_name |
111 | |
112 | #define SRI(reg_name, block, id)\ |
113 | .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ |
114 | mm ## block ## id ## _ ## reg_name |
115 | |
116 | |
117 | #define SRII(reg_name, block, id)\ |
118 | .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ |
119 | mm ## block ## id ## _ ## reg_name |
120 | |
121 | #define VUPDATE_SRII(reg_name, block, id)\ |
122 | .reg_name[id] = BASE(mm ## reg_name ## 0 ## _ ## block ## id ## _BASE_IDX) + \ |
123 | mm ## reg_name ## 0 ## _ ## block ## id |
124 | |
125 | /* set field/register/bitfield name */ |
126 | #define SFRB(field_name, reg_name, bitfield, post_fix)\ |
127 | .field_name = reg_name ## __ ## bitfield ## post_fix |
128 | |
129 | /* NBIO */ |
130 | #define NBIO_BASE_INNER(seg) \ |
131 | NBIF_BASE__INST0_SEG ## seg |
132 | |
133 | #define NBIO_BASE(seg) \ |
134 | NBIO_BASE_INNER(seg) |
135 | |
136 | #define NBIO_SR(reg_name)\ |
137 | .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ |
138 | mm ## reg_name |
139 | |
140 | /* MMHUB */ |
141 | #define MMHUB_BASE_INNER(seg) \ |
142 | MMHUB_BASE__INST0_SEG ## seg |
143 | |
144 | #define MMHUB_BASE(seg) \ |
145 | MMHUB_BASE_INNER(seg) |
146 | |
147 | #define MMHUB_SR(reg_name)\ |
148 | .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ |
149 | mm ## reg_name |
150 | |
151 | /* macros to expend register list macro defined in HW object header file |
152 | * end *********************/ |
153 | |
154 | |
155 | static const struct dce_dmcu_registers dmcu_regs = { |
156 | DMCU_DCN10_REG_LIST() |
157 | }; |
158 | |
159 | static const struct dce_dmcu_shift dmcu_shift = { |
160 | DMCU_MASK_SH_LIST_DCN10(__SHIFT) |
161 | }; |
162 | |
163 | static const struct dce_dmcu_mask dmcu_mask = { |
164 | DMCU_MASK_SH_LIST_DCN10(_MASK) |
165 | }; |
166 | |
167 | static const struct dce_abm_registers abm_regs = { |
168 | ABM_DCN10_REG_LIST(0) |
169 | }; |
170 | |
171 | static const struct dce_abm_shift abm_shift = { |
172 | ABM_MASK_SH_LIST_DCN10(__SHIFT) |
173 | }; |
174 | |
175 | static const struct dce_abm_mask abm_mask = { |
176 | ABM_MASK_SH_LIST_DCN10(_MASK) |
177 | }; |
178 | |
179 | #define stream_enc_regs(id)\ |
180 | [id] = {\ |
181 | SE_DCN_REG_LIST(id)\ |
182 | } |
183 | |
184 | static const struct dcn10_stream_enc_registers stream_enc_regs[] = { |
185 | stream_enc_regs(0), |
186 | stream_enc_regs(1), |
187 | stream_enc_regs(2), |
188 | stream_enc_regs(3), |
189 | }; |
190 | |
191 | static const struct dcn10_stream_encoder_shift se_shift = { |
192 | SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) |
193 | }; |
194 | |
195 | static const struct dcn10_stream_encoder_mask se_mask = { |
196 | SE_COMMON_MASK_SH_LIST_DCN10(_MASK) |
197 | }; |
198 | |
199 | #define audio_regs(id)\ |
200 | [id] = {\ |
201 | AUD_COMMON_REG_LIST(id)\ |
202 | } |
203 | |
204 | static const struct dce_audio_registers audio_regs[] = { |
205 | audio_regs(0), |
206 | audio_regs(1), |
207 | audio_regs(2), |
208 | audio_regs(3), |
209 | }; |
210 | |
211 | #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ |
212 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ |
213 | SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ |
214 | AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) |
215 | |
216 | static const struct dce_audio_shift audio_shift = { |
217 | DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) |
218 | }; |
219 | |
220 | static const struct dce_audio_mask audio_mask = { |
221 | DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) |
222 | }; |
223 | |
224 | #define aux_regs(id)\ |
225 | [id] = {\ |
226 | AUX_REG_LIST(id)\ |
227 | } |
228 | |
229 | static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { |
230 | aux_regs(0), |
231 | aux_regs(1), |
232 | aux_regs(2), |
233 | aux_regs(3) |
234 | }; |
235 | |
236 | #define hpd_regs(id)\ |
237 | [id] = {\ |
238 | HPD_REG_LIST(id)\ |
239 | } |
240 | |
241 | static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { |
242 | hpd_regs(0), |
243 | hpd_regs(1), |
244 | hpd_regs(2), |
245 | hpd_regs(3) |
246 | }; |
247 | |
248 | #define link_regs(id)\ |
249 | [id] = {\ |
250 | LE_DCN10_REG_LIST(id), \ |
251 | SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ |
252 | } |
253 | |
254 | static const struct dcn10_link_enc_registers link_enc_regs[] = { |
255 | link_regs(0), |
256 | link_regs(1), |
257 | link_regs(2), |
258 | link_regs(3) |
259 | }; |
260 | |
261 | static const struct dcn10_link_enc_shift le_shift = { |
262 | LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) |
263 | }; |
264 | |
265 | static const struct dcn10_link_enc_mask le_mask = { |
266 | LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) |
267 | }; |
268 | |
269 | static const struct dce_panel_cntl_registers panel_cntl_regs[] = { |
270 | { DCN_PANEL_CNTL_REG_LIST() } |
271 | }; |
272 | |
273 | static const struct dce_panel_cntl_shift panel_cntl_shift = { |
274 | DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) |
275 | }; |
276 | |
277 | static const struct dce_panel_cntl_mask panel_cntl_mask = { |
278 | DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) |
279 | }; |
280 | |
281 | static const struct dce110_aux_registers_shift aux_shift = { |
282 | DCN10_AUX_MASK_SH_LIST(__SHIFT) |
283 | }; |
284 | |
285 | static const struct dce110_aux_registers_mask aux_mask = { |
286 | DCN10_AUX_MASK_SH_LIST(_MASK) |
287 | }; |
288 | |
289 | #define ipp_regs(id)\ |
290 | [id] = {\ |
291 | IPP_REG_LIST_DCN10(id),\ |
292 | } |
293 | |
294 | static const struct dcn10_ipp_registers ipp_regs[] = { |
295 | ipp_regs(0), |
296 | ipp_regs(1), |
297 | ipp_regs(2), |
298 | ipp_regs(3), |
299 | }; |
300 | |
301 | static const struct dcn10_ipp_shift ipp_shift = { |
302 | IPP_MASK_SH_LIST_DCN10(__SHIFT) |
303 | }; |
304 | |
305 | static const struct dcn10_ipp_mask ipp_mask = { |
306 | IPP_MASK_SH_LIST_DCN10(_MASK), |
307 | }; |
308 | |
309 | #define opp_regs(id)\ |
310 | [id] = {\ |
311 | OPP_REG_LIST_DCN10(id),\ |
312 | } |
313 | |
314 | static const struct dcn10_opp_registers opp_regs[] = { |
315 | opp_regs(0), |
316 | opp_regs(1), |
317 | opp_regs(2), |
318 | opp_regs(3), |
319 | }; |
320 | |
321 | static const struct dcn10_opp_shift opp_shift = { |
322 | OPP_MASK_SH_LIST_DCN10(__SHIFT) |
323 | }; |
324 | |
325 | static const struct dcn10_opp_mask opp_mask = { |
326 | OPP_MASK_SH_LIST_DCN10(_MASK), |
327 | }; |
328 | |
329 | #define aux_engine_regs(id)\ |
330 | [id] = {\ |
331 | AUX_COMMON_REG_LIST(id), \ |
332 | .AUX_RESET_MASK = 0 \ |
333 | } |
334 | |
335 | static const struct dce110_aux_registers aux_engine_regs[] = { |
336 | aux_engine_regs(0), |
337 | aux_engine_regs(1), |
338 | aux_engine_regs(2), |
339 | aux_engine_regs(3), |
340 | aux_engine_regs(4), |
341 | aux_engine_regs(5) |
342 | }; |
343 | |
344 | #define tf_regs(id)\ |
345 | [id] = {\ |
346 | TF_REG_LIST_DCN10(id),\ |
347 | } |
348 | |
349 | static const struct dcn_dpp_registers tf_regs[] = { |
350 | tf_regs(0), |
351 | tf_regs(1), |
352 | tf_regs(2), |
353 | tf_regs(3), |
354 | }; |
355 | |
356 | static const struct dcn_dpp_shift tf_shift = { |
357 | TF_REG_LIST_SH_MASK_DCN10(__SHIFT), |
358 | TF_DEBUG_REG_LIST_SH_DCN10 |
359 | |
360 | }; |
361 | |
362 | static const struct dcn_dpp_mask tf_mask = { |
363 | TF_REG_LIST_SH_MASK_DCN10(_MASK), |
364 | TF_DEBUG_REG_LIST_MASK_DCN10 |
365 | }; |
366 | |
367 | static const struct dcn_mpc_registers mpc_regs = { |
368 | MPC_COMMON_REG_LIST_DCN1_0(0), |
369 | MPC_COMMON_REG_LIST_DCN1_0(1), |
370 | MPC_COMMON_REG_LIST_DCN1_0(2), |
371 | MPC_COMMON_REG_LIST_DCN1_0(3), |
372 | MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(0), |
373 | MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(1), |
374 | MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(2), |
375 | MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(3) |
376 | }; |
377 | |
378 | static const struct dcn_mpc_shift mpc_shift = { |
379 | MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT),\ |
380 | SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, __SHIFT) |
381 | }; |
382 | |
383 | static const struct dcn_mpc_mask mpc_mask = { |
384 | MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK),\ |
385 | SFRB(CUR_VUPDATE_LOCK_SET, CUR0_VUPDATE_LOCK_SET0, CUR0_VUPDATE_LOCK_SET, _MASK) |
386 | }; |
387 | |
388 | #define tg_regs(id)\ |
389 | [id] = {TG_COMMON_REG_LIST_DCN1_0(id)} |
390 | |
391 | static const struct dcn_optc_registers tg_regs[] = { |
392 | tg_regs(0), |
393 | tg_regs(1), |
394 | tg_regs(2), |
395 | tg_regs(3), |
396 | }; |
397 | |
398 | static const struct dcn_optc_shift tg_shift = { |
399 | TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) |
400 | }; |
401 | |
402 | static const struct dcn_optc_mask tg_mask = { |
403 | TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) |
404 | }; |
405 | |
406 | static const struct bios_registers bios_regs = { |
407 | NBIO_SR(BIOS_SCRATCH_3), |
408 | NBIO_SR(BIOS_SCRATCH_6) |
409 | }; |
410 | |
411 | #define hubp_regs(id)\ |
412 | [id] = {\ |
413 | HUBP_REG_LIST_DCN10(id)\ |
414 | } |
415 | |
416 | static const struct dcn_mi_registers hubp_regs[] = { |
417 | hubp_regs(0), |
418 | hubp_regs(1), |
419 | hubp_regs(2), |
420 | hubp_regs(3), |
421 | }; |
422 | |
423 | static const struct dcn_mi_shift hubp_shift = { |
424 | HUBP_MASK_SH_LIST_DCN10(__SHIFT) |
425 | }; |
426 | |
427 | static const struct dcn_mi_mask hubp_mask = { |
428 | HUBP_MASK_SH_LIST_DCN10(_MASK) |
429 | }; |
430 | |
431 | static const struct dcn_hubbub_registers hubbub_reg = { |
432 | HUBBUB_REG_LIST_DCN10(0) |
433 | }; |
434 | |
435 | static const struct dcn_hubbub_shift hubbub_shift = { |
436 | HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) |
437 | }; |
438 | |
439 | static const struct dcn_hubbub_mask hubbub_mask = { |
440 | HUBBUB_MASK_SH_LIST_DCN10(_MASK) |
441 | }; |
442 | |
443 | static int map_transmitter_id_to_phy_instance( |
444 | enum transmitter transmitter) |
445 | { |
446 | switch (transmitter) { |
447 | case TRANSMITTER_UNIPHY_A: |
448 | return 0; |
449 | break; |
450 | case TRANSMITTER_UNIPHY_B: |
451 | return 1; |
452 | break; |
453 | case TRANSMITTER_UNIPHY_C: |
454 | return 2; |
455 | break; |
456 | case TRANSMITTER_UNIPHY_D: |
457 | return 3; |
458 | break; |
459 | default: |
460 | ASSERT(0); |
461 | return 0; |
462 | } |
463 | } |
464 | |
465 | #define clk_src_regs(index, pllid)\ |
466 | [index] = {\ |
467 | CS_COMMON_REG_LIST_DCN1_0(index, pllid),\ |
468 | } |
469 | |
470 | static const struct dce110_clk_src_regs clk_src_regs[] = { |
471 | clk_src_regs(0, A), |
472 | clk_src_regs(1, B), |
473 | clk_src_regs(2, C), |
474 | clk_src_regs(3, D) |
475 | }; |
476 | |
477 | static const struct dce110_clk_src_shift cs_shift = { |
478 | CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) |
479 | }; |
480 | |
481 | static const struct dce110_clk_src_mask cs_mask = { |
482 | CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) |
483 | }; |
484 | |
485 | static const struct resource_caps res_cap = { |
486 | .num_timing_generator = 4, |
487 | .num_opp = 4, |
488 | .num_video_plane = 4, |
489 | .num_audio = 4, |
490 | .num_stream_encoder = 4, |
491 | .num_pll = 4, |
492 | .num_ddc = 4, |
493 | }; |
494 | |
495 | static const struct resource_caps rv2_res_cap = { |
496 | .num_timing_generator = 3, |
497 | .num_opp = 3, |
498 | .num_video_plane = 3, |
499 | .num_audio = 3, |
500 | .num_stream_encoder = 3, |
501 | .num_pll = 3, |
502 | .num_ddc = 4, |
503 | }; |
504 | |
505 | static const struct dc_plane_cap plane_cap = { |
506 | .type = DC_PLANE_TYPE_DCN_UNIVERSAL, |
507 | .per_pixel_alpha = true, |
508 | |
509 | .pixel_format_support = { |
510 | .argb8888 = true, |
511 | .nv12 = true, |
512 | .fp16 = true, |
513 | .p010 = true |
514 | }, |
515 | |
516 | .max_upscale_factor = { |
517 | .argb8888 = 16000, |
518 | .nv12 = 16000, |
519 | .fp16 = 1 |
520 | }, |
521 | |
522 | .max_downscale_factor = { |
523 | .argb8888 = 250, |
524 | .nv12 = 250, |
525 | .fp16 = 1 |
526 | } |
527 | }; |
528 | |
529 | static const struct dc_debug_options debug_defaults_drv = { |
530 | .sanity_checks = true, |
531 | .disable_dmcu = false, |
532 | .force_abm_enable = false, |
533 | .timing_trace = false, |
534 | .clock_trace = true, |
535 | |
536 | /* raven smu dones't allow 0 disp clk, |
537 | * smu min disp clk limit is 50Mhz |
538 | * keep min disp clk 100Mhz avoid smu hang |
539 | */ |
540 | .min_disp_clk_khz = 100000, |
541 | |
542 | .disable_pplib_clock_request = false, |
543 | .disable_pplib_wm_range = false, |
544 | .pplib_wm_report_mode = WM_REPORT_DEFAULT, |
545 | .pipe_split_policy = MPC_SPLIT_DYNAMIC, |
546 | .force_single_disp_pipe_split = true, |
547 | .disable_dcc = DCC_ENABLE, |
548 | .voltage_align_fclk = true, |
549 | .disable_stereo_support = true, |
550 | .vsr_support = true, |
551 | .performance_trace = false, |
552 | .az_endpoint_mute_only = true, |
553 | .recovery_enabled = false, /*enable this by default after testing.*/ |
554 | .max_downscale_src_width = 3840, |
555 | .underflow_assert_delay_us = 0xFFFFFFFF, |
556 | .enable_legacy_fast_update = true, |
557 | .using_dml2 = false, |
558 | }; |
559 | |
560 | static const struct dc_debug_options debug_defaults_diags = { |
561 | .disable_dmcu = false, |
562 | .force_abm_enable = false, |
563 | .timing_trace = true, |
564 | .clock_trace = true, |
565 | .disable_stutter = true, |
566 | .disable_pplib_clock_request = true, |
567 | .disable_pplib_wm_range = true, |
568 | .underflow_assert_delay_us = 0xFFFFFFFF, |
569 | }; |
570 | |
571 | static void dcn10_dpp_destroy(struct dpp **dpp) |
572 | { |
573 | kfree(TO_DCN10_DPP(*dpp)); |
574 | *dpp = NULL; |
575 | } |
576 | |
577 | static struct dpp *dcn10_dpp_create( |
578 | struct dc_context *ctx, |
579 | uint32_t inst) |
580 | { |
581 | struct dcn10_dpp *dpp = |
582 | kzalloc(size: sizeof(struct dcn10_dpp), GFP_KERNEL); |
583 | |
584 | if (!dpp) |
585 | return NULL; |
586 | |
587 | dpp1_construct(dpp1: dpp, ctx, inst, |
588 | tf_regs: &tf_regs[inst], tf_shift: &tf_shift, tf_mask: &tf_mask); |
589 | return &dpp->base; |
590 | } |
591 | |
592 | static struct input_pixel_processor *dcn10_ipp_create( |
593 | struct dc_context *ctx, uint32_t inst) |
594 | { |
595 | struct dcn10_ipp *ipp = |
596 | kzalloc(size: sizeof(struct dcn10_ipp), GFP_KERNEL); |
597 | |
598 | if (!ipp) { |
599 | BREAK_TO_DEBUGGER(); |
600 | return NULL; |
601 | } |
602 | |
603 | dcn10_ipp_construct(ippn10: ipp, ctx, inst, |
604 | regs: &ipp_regs[inst], ipp_shift: &ipp_shift, ipp_mask: &ipp_mask); |
605 | return &ipp->base; |
606 | } |
607 | |
608 | |
609 | static struct output_pixel_processor *dcn10_opp_create( |
610 | struct dc_context *ctx, uint32_t inst) |
611 | { |
612 | struct dcn10_opp *opp = |
613 | kzalloc(size: sizeof(struct dcn10_opp), GFP_KERNEL); |
614 | |
615 | if (!opp) { |
616 | BREAK_TO_DEBUGGER(); |
617 | return NULL; |
618 | } |
619 | |
620 | dcn10_opp_construct(oppn10: opp, ctx, inst, |
621 | regs: &opp_regs[inst], opp_shift: &opp_shift, opp_mask: &opp_mask); |
622 | return &opp->base; |
623 | } |
624 | |
625 | static struct dce_aux *dcn10_aux_engine_create(struct dc_context *ctx, |
626 | uint32_t inst) |
627 | { |
628 | struct aux_engine_dce110 *aux_engine = |
629 | kzalloc(size: sizeof(struct aux_engine_dce110), GFP_KERNEL); |
630 | |
631 | if (!aux_engine) |
632 | return NULL; |
633 | |
634 | dce110_aux_engine_construct(aux_engine110: aux_engine, ctx, inst, |
635 | timeout_period: SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, |
636 | regs: &aux_engine_regs[inst], |
637 | mask: &aux_mask, |
638 | shift: &aux_shift, |
639 | is_ext_aux_timeout_configurable: ctx->dc->caps.extended_aux_timeout_support); |
640 | |
641 | return &aux_engine->base; |
642 | } |
643 | #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } |
644 | |
645 | static const struct dce_i2c_registers i2c_hw_regs[] = { |
646 | i2c_inst_regs(1), |
647 | i2c_inst_regs(2), |
648 | i2c_inst_regs(3), |
649 | i2c_inst_regs(4), |
650 | i2c_inst_regs(5), |
651 | i2c_inst_regs(6), |
652 | }; |
653 | |
654 | static const struct dce_i2c_shift i2c_shifts = { |
655 | I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) |
656 | }; |
657 | |
658 | static const struct dce_i2c_mask i2c_masks = { |
659 | I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) |
660 | }; |
661 | |
662 | static struct dce_i2c_hw *dcn10_i2c_hw_create(struct dc_context *ctx, |
663 | uint32_t inst) |
664 | { |
665 | struct dce_i2c_hw *dce_i2c_hw = |
666 | kzalloc(size: sizeof(struct dce_i2c_hw), GFP_KERNEL); |
667 | |
668 | if (!dce_i2c_hw) |
669 | return NULL; |
670 | |
671 | dcn1_i2c_hw_construct(dce_i2c_hw, ctx, engine_id: inst, |
672 | regs: &i2c_hw_regs[inst], shifts: &i2c_shifts, masks: &i2c_masks); |
673 | |
674 | return dce_i2c_hw; |
675 | } |
676 | static struct mpc *dcn10_mpc_create(struct dc_context *ctx) |
677 | { |
678 | struct dcn10_mpc *mpc10 = kzalloc(size: sizeof(struct dcn10_mpc), |
679 | GFP_KERNEL); |
680 | |
681 | if (!mpc10) |
682 | return NULL; |
683 | |
684 | dcn10_mpc_construct(mpcc10: mpc10, ctx, |
685 | mpc_regs: &mpc_regs, |
686 | mpc_shift: &mpc_shift, |
687 | mpc_mask: &mpc_mask, |
688 | num_mpcc: 4); |
689 | |
690 | return &mpc10->base; |
691 | } |
692 | |
693 | static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx) |
694 | { |
695 | struct dcn10_hubbub *dcn10_hubbub = kzalloc(size: sizeof(struct dcn10_hubbub), |
696 | GFP_KERNEL); |
697 | |
698 | if (!dcn10_hubbub) |
699 | return NULL; |
700 | |
701 | hubbub1_construct(hubbub: &dcn10_hubbub->base, ctx, |
702 | hubbub_regs: &hubbub_reg, |
703 | hubbub_shift: &hubbub_shift, |
704 | hubbub_mask: &hubbub_mask); |
705 | |
706 | return &dcn10_hubbub->base; |
707 | } |
708 | |
709 | static struct timing_generator *dcn10_timing_generator_create( |
710 | struct dc_context *ctx, |
711 | uint32_t instance) |
712 | { |
713 | struct optc *tgn10 = |
714 | kzalloc(size: sizeof(struct optc), GFP_KERNEL); |
715 | |
716 | if (!tgn10) |
717 | return NULL; |
718 | |
719 | tgn10->base.inst = instance; |
720 | tgn10->base.ctx = ctx; |
721 | |
722 | tgn10->tg_regs = &tg_regs[instance]; |
723 | tgn10->tg_shift = &tg_shift; |
724 | tgn10->tg_mask = &tg_mask; |
725 | |
726 | dcn10_timing_generator_init(optc: tgn10); |
727 | |
728 | return &tgn10->base; |
729 | } |
730 | |
731 | static const struct encoder_feature_support link_enc_feature = { |
732 | .max_hdmi_deep_color = COLOR_DEPTH_121212, |
733 | .max_hdmi_pixel_clock = 600000, |
734 | .hdmi_ycbcr420_supported = true, |
735 | .dp_ycbcr420_supported = true, |
736 | .flags.bits.IS_HBR2_CAPABLE = true, |
737 | .flags.bits.IS_HBR3_CAPABLE = true, |
738 | .flags.bits.IS_TPS3_CAPABLE = true, |
739 | .flags.bits.IS_TPS4_CAPABLE = true |
740 | }; |
741 | |
742 | static struct link_encoder *dcn10_link_encoder_create( |
743 | struct dc_context *ctx, |
744 | const struct encoder_init_data *enc_init_data) |
745 | { |
746 | struct dcn10_link_encoder *enc10 = |
747 | kzalloc(size: sizeof(struct dcn10_link_encoder), GFP_KERNEL); |
748 | int link_regs_id; |
749 | |
750 | if (!enc10) |
751 | return NULL; |
752 | |
753 | link_regs_id = |
754 | map_transmitter_id_to_phy_instance(transmitter: enc_init_data->transmitter); |
755 | |
756 | dcn10_link_encoder_construct(enc10, |
757 | init_data: enc_init_data, |
758 | enc_features: &link_enc_feature, |
759 | link_regs: &link_enc_regs[link_regs_id], |
760 | aux_regs: &link_enc_aux_regs[enc_init_data->channel - 1], |
761 | hpd_regs: &link_enc_hpd_regs[enc_init_data->hpd_source], |
762 | link_shift: &le_shift, |
763 | link_mask: &le_mask); |
764 | |
765 | return &enc10->base; |
766 | } |
767 | |
768 | static struct panel_cntl *dcn10_panel_cntl_create(const struct panel_cntl_init_data *init_data) |
769 | { |
770 | struct dce_panel_cntl *panel_cntl = |
771 | kzalloc(size: sizeof(struct dce_panel_cntl), GFP_KERNEL); |
772 | |
773 | if (!panel_cntl) |
774 | return NULL; |
775 | |
776 | dce_panel_cntl_construct(panel_cntl, |
777 | init_data, |
778 | regs: &panel_cntl_regs[init_data->inst], |
779 | shift: &panel_cntl_shift, |
780 | mask: &panel_cntl_mask); |
781 | |
782 | return &panel_cntl->base; |
783 | } |
784 | |
785 | static struct clock_source *dcn10_clock_source_create( |
786 | struct dc_context *ctx, |
787 | struct dc_bios *bios, |
788 | enum clock_source_id id, |
789 | const struct dce110_clk_src_regs *regs, |
790 | bool dp_clk_src) |
791 | { |
792 | struct dce110_clk_src *clk_src = |
793 | kzalloc(size: sizeof(struct dce110_clk_src), GFP_KERNEL); |
794 | |
795 | if (!clk_src) |
796 | return NULL; |
797 | |
798 | if (dce112_clk_src_construct(clk_src, ctx, bios, id, |
799 | regs, cs_shift: &cs_shift, cs_mask: &cs_mask)) { |
800 | clk_src->base.dp_clk_src = dp_clk_src; |
801 | return &clk_src->base; |
802 | } |
803 | |
804 | kfree(objp: clk_src); |
805 | BREAK_TO_DEBUGGER(); |
806 | return NULL; |
807 | } |
808 | |
809 | static void read_dce_straps( |
810 | struct dc_context *ctx, |
811 | struct resource_straps *straps) |
812 | { |
813 | generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), |
814 | FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), field_value: &straps->dc_pinstraps_audio); |
815 | } |
816 | |
817 | static struct audio *create_audio( |
818 | struct dc_context *ctx, unsigned int inst) |
819 | { |
820 | return dce_audio_create(ctx, inst, |
821 | reg: &audio_regs[inst], shifts: &audio_shift, masks: &audio_mask); |
822 | } |
823 | |
824 | static struct stream_encoder *dcn10_stream_encoder_create( |
825 | enum engine_id eng_id, |
826 | struct dc_context *ctx) |
827 | { |
828 | struct dcn10_stream_encoder *enc1 = |
829 | kzalloc(size: sizeof(struct dcn10_stream_encoder), GFP_KERNEL); |
830 | |
831 | if (!enc1) |
832 | return NULL; |
833 | |
834 | dcn10_stream_encoder_construct(enc1, ctx, bp: ctx->dc_bios, eng_id, |
835 | regs: &stream_enc_regs[eng_id], |
836 | se_shift: &se_shift, se_mask: &se_mask); |
837 | return &enc1->base; |
838 | } |
839 | |
840 | static const struct dce_hwseq_registers hwseq_reg = { |
841 | HWSEQ_DCN1_REG_LIST() |
842 | }; |
843 | |
844 | static const struct dce_hwseq_shift hwseq_shift = { |
845 | HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) |
846 | }; |
847 | |
848 | static const struct dce_hwseq_mask hwseq_mask = { |
849 | HWSEQ_DCN1_MASK_SH_LIST(_MASK) |
850 | }; |
851 | |
852 | static struct dce_hwseq *dcn10_hwseq_create( |
853 | struct dc_context *ctx) |
854 | { |
855 | struct dce_hwseq *hws = kzalloc(size: sizeof(struct dce_hwseq), GFP_KERNEL); |
856 | |
857 | if (hws) { |
858 | hws->ctx = ctx; |
859 | hws->regs = &hwseq_reg; |
860 | hws->shifts = &hwseq_shift; |
861 | hws->masks = &hwseq_mask; |
862 | hws->wa.DEGVIDCN10_253 = true; |
863 | hws->wa.false_optc_underflow = true; |
864 | hws->wa.DEGVIDCN10_254 = true; |
865 | |
866 | if ((ctx->asic_id.chip_family == FAMILY_RV) && |
867 | ASICREV_IS_RAVEN2(ctx->asic_id.hw_internal_rev)) |
868 | switch (ctx->asic_id.pci_revision_id) { |
869 | case PRID_POLLOCK_94: |
870 | case PRID_POLLOCK_95: |
871 | case PRID_POLLOCK_E9: |
872 | case PRID_POLLOCK_EA: |
873 | case PRID_POLLOCK_EB: |
874 | hws->wa.wait_hubpret_read_start_during_mpo_transition = true; |
875 | break; |
876 | default: |
877 | hws->wa.wait_hubpret_read_start_during_mpo_transition = false; |
878 | break; |
879 | } |
880 | } |
881 | return hws; |
882 | } |
883 | |
884 | static const struct resource_create_funcs res_create_funcs = { |
885 | .read_dce_straps = read_dce_straps, |
886 | .create_audio = create_audio, |
887 | .create_stream_encoder = dcn10_stream_encoder_create, |
888 | .create_hwseq = dcn10_hwseq_create, |
889 | }; |
890 | |
891 | static void dcn10_clock_source_destroy(struct clock_source **clk_src) |
892 | { |
893 | kfree(TO_DCE110_CLK_SRC(*clk_src)); |
894 | *clk_src = NULL; |
895 | } |
896 | |
897 | static struct pp_smu_funcs *dcn10_pp_smu_create(struct dc_context *ctx) |
898 | { |
899 | struct pp_smu_funcs *pp_smu = kzalloc(size: sizeof(*pp_smu), GFP_KERNEL); |
900 | |
901 | if (!pp_smu) |
902 | return pp_smu; |
903 | |
904 | dm_pp_get_funcs(ctx, funcs: pp_smu); |
905 | return pp_smu; |
906 | } |
907 | |
908 | static void dcn10_resource_destruct(struct dcn10_resource_pool *pool) |
909 | { |
910 | unsigned int i; |
911 | |
912 | for (i = 0; i < pool->base.stream_enc_count; i++) { |
913 | if (pool->base.stream_enc[i] != NULL) { |
914 | kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); |
915 | pool->base.stream_enc[i] = NULL; |
916 | } |
917 | } |
918 | |
919 | if (pool->base.mpc != NULL) { |
920 | kfree(TO_DCN10_MPC(pool->base.mpc)); |
921 | pool->base.mpc = NULL; |
922 | } |
923 | |
924 | kfree(objp: pool->base.hubbub); |
925 | pool->base.hubbub = NULL; |
926 | |
927 | for (i = 0; i < pool->base.pipe_count; i++) { |
928 | if (pool->base.opps[i] != NULL) |
929 | pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); |
930 | |
931 | if (pool->base.dpps[i] != NULL) |
932 | dcn10_dpp_destroy(dpp: &pool->base.dpps[i]); |
933 | |
934 | if (pool->base.ipps[i] != NULL) |
935 | pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); |
936 | |
937 | if (pool->base.hubps[i] != NULL) { |
938 | kfree(TO_DCN10_HUBP(pool->base.hubps[i])); |
939 | pool->base.hubps[i] = NULL; |
940 | } |
941 | |
942 | if (pool->base.irqs != NULL) { |
943 | dal_irq_service_destroy(irq_service: &pool->base.irqs); |
944 | } |
945 | |
946 | if (pool->base.timing_generators[i] != NULL) { |
947 | kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); |
948 | pool->base.timing_generators[i] = NULL; |
949 | } |
950 | } |
951 | |
952 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { |
953 | if (pool->base.engines[i] != NULL) |
954 | dce110_engine_destroy(engine: &pool->base.engines[i]); |
955 | kfree(objp: pool->base.hw_i2cs[i]); |
956 | pool->base.hw_i2cs[i] = NULL; |
957 | kfree(objp: pool->base.sw_i2cs[i]); |
958 | pool->base.sw_i2cs[i] = NULL; |
959 | } |
960 | |
961 | for (i = 0; i < pool->base.audio_count; i++) { |
962 | if (pool->base.audios[i]) |
963 | dce_aud_destroy(audio: &pool->base.audios[i]); |
964 | } |
965 | |
966 | for (i = 0; i < pool->base.clk_src_count; i++) { |
967 | if (pool->base.clock_sources[i] != NULL) { |
968 | dcn10_clock_source_destroy(clk_src: &pool->base.clock_sources[i]); |
969 | pool->base.clock_sources[i] = NULL; |
970 | } |
971 | } |
972 | |
973 | if (pool->base.dp_clock_source != NULL) { |
974 | dcn10_clock_source_destroy(clk_src: &pool->base.dp_clock_source); |
975 | pool->base.dp_clock_source = NULL; |
976 | } |
977 | |
978 | if (pool->base.abm != NULL) |
979 | dce_abm_destroy(abm: &pool->base.abm); |
980 | |
981 | if (pool->base.dmcu != NULL) |
982 | dce_dmcu_destroy(dmcu: &pool->base.dmcu); |
983 | |
984 | kfree(objp: pool->base.pp_smu); |
985 | } |
986 | |
987 | static struct hubp *dcn10_hubp_create( |
988 | struct dc_context *ctx, |
989 | uint32_t inst) |
990 | { |
991 | struct dcn10_hubp *hubp1 = |
992 | kzalloc(size: sizeof(struct dcn10_hubp), GFP_KERNEL); |
993 | |
994 | if (!hubp1) |
995 | return NULL; |
996 | |
997 | dcn10_hubp_construct(hubp1, ctx, inst, |
998 | hubp_regs: &hubp_regs[inst], hubp_shift: &hubp_shift, hubp_mask: &hubp_mask); |
999 | return &hubp1->base; |
1000 | } |
1001 | |
1002 | static void get_pixel_clock_parameters( |
1003 | const struct pipe_ctx *pipe_ctx, |
1004 | struct pixel_clk_params *pixel_clk_params) |
1005 | { |
1006 | const struct dc_stream_state *stream = pipe_ctx->stream; |
1007 | pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; |
1008 | pixel_clk_params->encoder_object_id = stream->link->link_enc->id; |
1009 | pixel_clk_params->signal_type = pipe_ctx->stream->signal; |
1010 | pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; |
1011 | /* TODO: un-hardcode*/ |
1012 | pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * |
1013 | LINK_RATE_REF_FREQ_IN_KHZ; |
1014 | pixel_clk_params->flags.ENABLE_SS = 0; |
1015 | pixel_clk_params->color_depth = |
1016 | stream->timing.display_color_depth; |
1017 | pixel_clk_params->flags.DISPLAY_BLANKED = 1; |
1018 | pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; |
1019 | |
1020 | if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) |
1021 | pixel_clk_params->color_depth = COLOR_DEPTH_888; |
1022 | |
1023 | if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) |
1024 | pixel_clk_params->requested_pix_clk_100hz /= 2; |
1025 | if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) |
1026 | pixel_clk_params->requested_pix_clk_100hz *= 2; |
1027 | |
1028 | } |
1029 | |
1030 | static void build_clamping_params(struct dc_stream_state *stream) |
1031 | { |
1032 | stream->clamping.clamping_level = CLAMPING_FULL_RANGE; |
1033 | stream->clamping.c_depth = stream->timing.display_color_depth; |
1034 | stream->clamping.pixel_encoding = stream->timing.pixel_encoding; |
1035 | } |
1036 | |
1037 | static void build_pipe_hw_param(struct pipe_ctx *pipe_ctx) |
1038 | { |
1039 | |
1040 | get_pixel_clock_parameters(pipe_ctx, pixel_clk_params: &pipe_ctx->stream_res.pix_clk_params); |
1041 | |
1042 | pipe_ctx->clock_source->funcs->get_pix_clk_dividers( |
1043 | pipe_ctx->clock_source, |
1044 | &pipe_ctx->stream_res.pix_clk_params, |
1045 | &pipe_ctx->pll_settings); |
1046 | |
1047 | pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; |
1048 | |
1049 | resource_build_bit_depth_reduction_params(stream: pipe_ctx->stream, |
1050 | fmt_bit_depth: &pipe_ctx->stream->bit_depth_params); |
1051 | build_clamping_params(stream: pipe_ctx->stream); |
1052 | } |
1053 | |
1054 | static enum dc_status build_mapped_resource( |
1055 | const struct dc *dc, |
1056 | struct dc_state *context, |
1057 | struct dc_stream_state *stream) |
1058 | { |
1059 | struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(res_ctx: &context->res_ctx, stream); |
1060 | |
1061 | if (!pipe_ctx) |
1062 | return DC_ERROR_UNEXPECTED; |
1063 | |
1064 | build_pipe_hw_param(pipe_ctx); |
1065 | return DC_OK; |
1066 | } |
1067 | |
1068 | static enum dc_status dcn10_add_stream_to_ctx( |
1069 | struct dc *dc, |
1070 | struct dc_state *new_ctx, |
1071 | struct dc_stream_state *dc_stream) |
1072 | { |
1073 | enum dc_status result = DC_ERROR_UNEXPECTED; |
1074 | |
1075 | result = resource_map_pool_resources(dc, context: new_ctx, stream: dc_stream); |
1076 | |
1077 | if (result == DC_OK) |
1078 | result = resource_map_phy_clock_resources(dc, context: new_ctx, stream: dc_stream); |
1079 | |
1080 | |
1081 | if (result == DC_OK) |
1082 | result = build_mapped_resource(dc, context: new_ctx, stream: dc_stream); |
1083 | |
1084 | return result; |
1085 | } |
1086 | |
1087 | static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer( |
1088 | const struct dc_state *cur_ctx, |
1089 | struct dc_state *new_ctx, |
1090 | const struct resource_pool *pool, |
1091 | const struct pipe_ctx *opp_head_pipe) |
1092 | { |
1093 | struct resource_context *res_ctx = &new_ctx->res_ctx; |
1094 | struct pipe_ctx *head_pipe = resource_get_otg_master_for_stream(res_ctx, stream: opp_head_pipe->stream); |
1095 | struct pipe_ctx *idle_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, primary_pipe: head_pipe); |
1096 | |
1097 | if (!head_pipe) { |
1098 | ASSERT(0); |
1099 | return NULL; |
1100 | } |
1101 | |
1102 | if (!idle_pipe) |
1103 | return NULL; |
1104 | |
1105 | idle_pipe->stream = head_pipe->stream; |
1106 | idle_pipe->stream_res.tg = head_pipe->stream_res.tg; |
1107 | idle_pipe->stream_res.abm = head_pipe->stream_res.abm; |
1108 | idle_pipe->stream_res.opp = head_pipe->stream_res.opp; |
1109 | |
1110 | idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; |
1111 | idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; |
1112 | idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; |
1113 | idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; |
1114 | |
1115 | return idle_pipe; |
1116 | } |
1117 | |
1118 | static bool dcn10_get_dcc_compression_cap(const struct dc *dc, |
1119 | const struct dc_dcc_surface_param *input, |
1120 | struct dc_surface_dcc_cap *output) |
1121 | { |
1122 | return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( |
1123 | dc->res_pool->hubbub, |
1124 | input, |
1125 | output); |
1126 | } |
1127 | |
1128 | static void dcn10_destroy_resource_pool(struct resource_pool **pool) |
1129 | { |
1130 | struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); |
1131 | |
1132 | dcn10_resource_destruct(pool: dcn10_pool); |
1133 | kfree(objp: dcn10_pool); |
1134 | *pool = NULL; |
1135 | } |
1136 | |
1137 | static bool dcn10_validate_bandwidth( |
1138 | struct dc *dc, |
1139 | struct dc_state *context, |
1140 | bool fast_validate) |
1141 | { |
1142 | bool voltage_supported; |
1143 | |
1144 | DC_FP_START(); |
1145 | voltage_supported = dcn_validate_bandwidth(dc, context, fast_validate); |
1146 | DC_FP_END(); |
1147 | |
1148 | return voltage_supported; |
1149 | } |
1150 | |
1151 | static enum dc_status dcn10_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps) |
1152 | { |
1153 | if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN |
1154 | && caps->max_video_width != 0 |
1155 | && plane_state->src_rect.width > caps->max_video_width) |
1156 | return DC_FAIL_SURFACE_VALIDATE; |
1157 | |
1158 | return DC_OK; |
1159 | } |
1160 | |
1161 | static enum dc_status dcn10_validate_global(struct dc *dc, struct dc_state *context) |
1162 | { |
1163 | int i, j; |
1164 | bool video_down_scaled = false; |
1165 | bool video_large = false; |
1166 | bool desktop_large = false; |
1167 | bool dcc_disabled = false; |
1168 | bool mpo_enabled = false; |
1169 | |
1170 | for (i = 0; i < context->stream_count; i++) { |
1171 | if (context->stream_status[i].plane_count == 0) |
1172 | continue; |
1173 | |
1174 | if (context->stream_status[i].plane_count > 2) |
1175 | return DC_FAIL_UNSUPPORTED_1; |
1176 | |
1177 | if (context->stream_status[i].plane_count > 1) |
1178 | mpo_enabled = true; |
1179 | |
1180 | for (j = 0; j < context->stream_status[i].plane_count; j++) { |
1181 | struct dc_plane_state *plane = |
1182 | context->stream_status[i].plane_states[j]; |
1183 | |
1184 | |
1185 | if (plane->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { |
1186 | |
1187 | if (plane->src_rect.width > plane->dst_rect.width || |
1188 | plane->src_rect.height > plane->dst_rect.height) |
1189 | video_down_scaled = true; |
1190 | |
1191 | if (plane->src_rect.width >= 3840) |
1192 | video_large = true; |
1193 | |
1194 | } else { |
1195 | if (plane->src_rect.width >= 3840) |
1196 | desktop_large = true; |
1197 | if (!plane->dcc.enable) |
1198 | dcc_disabled = true; |
1199 | } |
1200 | } |
1201 | } |
1202 | |
1203 | /* Disable MPO in multi-display configurations. */ |
1204 | if (context->stream_count > 1 && mpo_enabled) |
1205 | return DC_FAIL_UNSUPPORTED_1; |
1206 | |
1207 | /* |
1208 | * Workaround: On DCN10 there is UMC issue that causes underflow when |
1209 | * playing 4k video on 4k desktop with video downscaled and single channel |
1210 | * memory |
1211 | */ |
1212 | if (video_large && desktop_large && video_down_scaled && dcc_disabled && |
1213 | dc->dcn_soc->number_of_channels == 1) |
1214 | return DC_FAIL_SURFACE_VALIDATE; |
1215 | |
1216 | return DC_OK; |
1217 | } |
1218 | |
1219 | static enum dc_status dcn10_patch_unknown_plane_state(struct dc_plane_state *plane_state) |
1220 | { |
1221 | enum surface_pixel_format surf_pix_format = plane_state->format; |
1222 | unsigned int bpp = resource_pixel_format_to_bpp(format: surf_pix_format); |
1223 | |
1224 | enum swizzle_mode_values swizzle = DC_SW_LINEAR; |
1225 | |
1226 | if (bpp == 64) |
1227 | swizzle = DC_SW_64KB_D; |
1228 | else |
1229 | swizzle = DC_SW_64KB_S; |
1230 | |
1231 | plane_state->tiling_info.gfx9.swizzle = swizzle; |
1232 | return DC_OK; |
1233 | } |
1234 | |
1235 | struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link( |
1236 | struct resource_context *res_ctx, |
1237 | const struct resource_pool *pool, |
1238 | struct dc_stream_state *stream) |
1239 | { |
1240 | int i; |
1241 | int j = -1; |
1242 | struct dc_link *link = stream->link; |
1243 | |
1244 | for (i = 0; i < pool->stream_enc_count; i++) { |
1245 | if (!res_ctx->is_stream_enc_acquired[i] && |
1246 | pool->stream_enc[i]) { |
1247 | /* Store first available for MST second display |
1248 | * in daisy chain use case |
1249 | */ |
1250 | j = i; |
1251 | if (link->ep_type == DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id == |
1252 | link->link_enc->preferred_engine) |
1253 | return pool->stream_enc[i]; |
1254 | } |
1255 | } |
1256 | |
1257 | /* |
1258 | * For CZ and later, we can allow DIG FE and BE to differ for all display types |
1259 | */ |
1260 | |
1261 | if (j >= 0) |
1262 | return pool->stream_enc[j]; |
1263 | |
1264 | return NULL; |
1265 | } |
1266 | |
1267 | static const struct dc_cap_funcs cap_funcs = { |
1268 | .get_dcc_compression_cap = dcn10_get_dcc_compression_cap |
1269 | }; |
1270 | |
1271 | static const struct resource_funcs dcn10_res_pool_funcs = { |
1272 | .destroy = dcn10_destroy_resource_pool, |
1273 | .link_enc_create = dcn10_link_encoder_create, |
1274 | .panel_cntl_create = dcn10_panel_cntl_create, |
1275 | .validate_bandwidth = dcn10_validate_bandwidth, |
1276 | .acquire_free_pipe_as_secondary_dpp_pipe = dcn10_acquire_free_pipe_for_layer, |
1277 | .validate_plane = dcn10_validate_plane, |
1278 | .validate_global = dcn10_validate_global, |
1279 | .add_stream_to_ctx = dcn10_add_stream_to_ctx, |
1280 | .patch_unknown_plane_state = dcn10_patch_unknown_plane_state, |
1281 | .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link |
1282 | }; |
1283 | |
1284 | static uint32_t read_pipe_fuses(struct dc_context *ctx) |
1285 | { |
1286 | uint32_t value = dm_read_reg_soc15(ctx, mmCC_DC_PIPE_DIS, 0); |
1287 | /* RV1 support max 4 pipes */ |
1288 | value = value & 0xf; |
1289 | return value; |
1290 | } |
1291 | |
1292 | static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) |
1293 | { |
1294 | int i; |
1295 | |
1296 | if (clks->num_levels == 0) |
1297 | return false; |
1298 | |
1299 | for (i = 0; i < clks->num_levels; i++) |
1300 | /* Ensure that the result is sane */ |
1301 | if (clks->data[i].clocks_in_khz == 0) |
1302 | return false; |
1303 | |
1304 | return true; |
1305 | } |
1306 | |
1307 | static bool dcn10_resource_construct( |
1308 | uint8_t num_virtual_links, |
1309 | struct dc *dc, |
1310 | struct dcn10_resource_pool *pool) |
1311 | { |
1312 | int i; |
1313 | int j; |
1314 | struct dc_context *ctx = dc->ctx; |
1315 | uint32_t pipe_fuses = read_pipe_fuses(ctx); |
1316 | struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; |
1317 | int min_fclk_khz, min_dcfclk_khz, socclk_khz; |
1318 | bool res; |
1319 | |
1320 | ctx->dc_bios->regs = &bios_regs; |
1321 | |
1322 | if (ctx->dce_version == DCN_VERSION_1_01) |
1323 | pool->base.res_cap = &rv2_res_cap; |
1324 | else |
1325 | pool->base.res_cap = &res_cap; |
1326 | pool->base.funcs = &dcn10_res_pool_funcs; |
1327 | |
1328 | /* |
1329 | * TODO fill in from actual raven resource when we create |
1330 | * more than virtual encoder |
1331 | */ |
1332 | |
1333 | /************************************************* |
1334 | * Resource + asic cap harcoding * |
1335 | *************************************************/ |
1336 | pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; |
1337 | |
1338 | /* max pipe num for ASIC before check pipe fuses */ |
1339 | pool->base.pipe_count = pool->base.res_cap->num_timing_generator; |
1340 | |
1341 | if (dc->ctx->dce_version == DCN_VERSION_1_01) |
1342 | pool->base.pipe_count = 3; |
1343 | dc->caps.max_video_width = 3840; |
1344 | dc->caps.max_downscale_ratio = 200; |
1345 | dc->caps.i2c_speed_in_khz = 100; |
1346 | dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ |
1347 | dc->caps.max_cursor_size = 256; |
1348 | dc->caps.min_horizontal_blanking_period = 80; |
1349 | dc->caps.max_slave_planes = 1; |
1350 | dc->caps.max_slave_yuv_planes = 1; |
1351 | dc->caps.max_slave_rgb_planes = 0; |
1352 | dc->caps.is_apu = true; |
1353 | dc->caps.post_blend_color_processing = false; |
1354 | dc->caps.extended_aux_timeout_support = false; |
1355 | |
1356 | /* Raven DP PHY HBR2 eye diagram pattern is not stable. Use TP4 */ |
1357 | dc->caps.force_dp_tps4_for_cp2520 = true; |
1358 | |
1359 | /* Color pipeline capabilities */ |
1360 | dc->caps.color.dpp.dcn_arch = 1; |
1361 | dc->caps.color.dpp.input_lut_shared = 1; |
1362 | dc->caps.color.dpp.icsc = 1; |
1363 | dc->caps.color.dpp.dgam_ram = 1; |
1364 | dc->caps.color.dpp.dgam_rom_caps.srgb = 1; |
1365 | dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; |
1366 | dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; |
1367 | dc->caps.color.dpp.dgam_rom_caps.pq = 0; |
1368 | dc->caps.color.dpp.dgam_rom_caps.hlg = 0; |
1369 | dc->caps.color.dpp.post_csc = 0; |
1370 | dc->caps.color.dpp.gamma_corr = 0; |
1371 | dc->caps.color.dpp.dgam_rom_for_yuv = 1; |
1372 | |
1373 | dc->caps.color.dpp.hw_3d_lut = 0; |
1374 | dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1 |
1375 | dc->caps.color.dpp.ogam_rom_caps.srgb = 1; |
1376 | dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1; |
1377 | dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; |
1378 | dc->caps.color.dpp.ogam_rom_caps.pq = 0; |
1379 | dc->caps.color.dpp.ogam_rom_caps.hlg = 0; |
1380 | dc->caps.color.dpp.ocsc = 1; |
1381 | |
1382 | /* no post-blend color operations */ |
1383 | dc->caps.color.mpc.gamut_remap = 0; |
1384 | dc->caps.color.mpc.num_3dluts = 0; |
1385 | dc->caps.color.mpc.shared_3d_lut = 0; |
1386 | dc->caps.color.mpc.ogam_ram = 0; |
1387 | dc->caps.color.mpc.ogam_rom_caps.srgb = 0; |
1388 | dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; |
1389 | dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; |
1390 | dc->caps.color.mpc.ogam_rom_caps.pq = 0; |
1391 | dc->caps.color.mpc.ogam_rom_caps.hlg = 0; |
1392 | dc->caps.color.mpc.ocsc = 0; |
1393 | |
1394 | if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) |
1395 | dc->debug = debug_defaults_drv; |
1396 | else |
1397 | dc->debug = debug_defaults_diags; |
1398 | |
1399 | /************************************************* |
1400 | * Create resources * |
1401 | *************************************************/ |
1402 | |
1403 | pool->base.clock_sources[DCN10_CLK_SRC_PLL0] = |
1404 | dcn10_clock_source_create(ctx, bios: ctx->dc_bios, |
1405 | id: CLOCK_SOURCE_COMBO_PHY_PLL0, |
1406 | regs: &clk_src_regs[0], dp_clk_src: false); |
1407 | pool->base.clock_sources[DCN10_CLK_SRC_PLL1] = |
1408 | dcn10_clock_source_create(ctx, bios: ctx->dc_bios, |
1409 | id: CLOCK_SOURCE_COMBO_PHY_PLL1, |
1410 | regs: &clk_src_regs[1], dp_clk_src: false); |
1411 | pool->base.clock_sources[DCN10_CLK_SRC_PLL2] = |
1412 | dcn10_clock_source_create(ctx, bios: ctx->dc_bios, |
1413 | id: CLOCK_SOURCE_COMBO_PHY_PLL2, |
1414 | regs: &clk_src_regs[2], dp_clk_src: false); |
1415 | |
1416 | if (dc->ctx->dce_version == DCN_VERSION_1_0) { |
1417 | pool->base.clock_sources[DCN10_CLK_SRC_PLL3] = |
1418 | dcn10_clock_source_create(ctx, bios: ctx->dc_bios, |
1419 | id: CLOCK_SOURCE_COMBO_PHY_PLL3, |
1420 | regs: &clk_src_regs[3], dp_clk_src: false); |
1421 | } |
1422 | |
1423 | pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL; |
1424 | |
1425 | if (dc->ctx->dce_version == DCN_VERSION_1_01) |
1426 | pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL; |
1427 | |
1428 | pool->base.dp_clock_source = |
1429 | dcn10_clock_source_create(ctx, bios: ctx->dc_bios, |
1430 | id: CLOCK_SOURCE_ID_DP_DTO, |
1431 | /* todo: not reuse phy_pll registers */ |
1432 | regs: &clk_src_regs[0], dp_clk_src: true); |
1433 | |
1434 | for (i = 0; i < pool->base.clk_src_count; i++) { |
1435 | if (pool->base.clock_sources[i] == NULL) { |
1436 | dm_error("DC: failed to create clock sources!\n" ); |
1437 | BREAK_TO_DEBUGGER(); |
1438 | goto fail; |
1439 | } |
1440 | } |
1441 | |
1442 | pool->base.dmcu = dcn10_dmcu_create(ctx, |
1443 | regs: &dmcu_regs, |
1444 | dmcu_shift: &dmcu_shift, |
1445 | dmcu_mask: &dmcu_mask); |
1446 | if (pool->base.dmcu == NULL) { |
1447 | dm_error("DC: failed to create dmcu!\n" ); |
1448 | BREAK_TO_DEBUGGER(); |
1449 | goto fail; |
1450 | } |
1451 | |
1452 | pool->base.abm = dce_abm_create(ctx, |
1453 | regs: &abm_regs, |
1454 | abm_shift: &abm_shift, |
1455 | abm_mask: &abm_mask); |
1456 | if (pool->base.abm == NULL) { |
1457 | dm_error("DC: failed to create abm!\n" ); |
1458 | BREAK_TO_DEBUGGER(); |
1459 | goto fail; |
1460 | } |
1461 | |
1462 | dml_init_instance(lib: &dc->dml, soc_bb: &dcn1_0_soc, ip_params: &dcn1_0_ip, project: DML_PROJECT_RAVEN1); |
1463 | memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults)); |
1464 | memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults)); |
1465 | |
1466 | DC_FP_START(); |
1467 | dcn10_resource_construct_fp(dc); |
1468 | DC_FP_END(); |
1469 | |
1470 | if (!dc->config.is_vmin_only_asic) |
1471 | if (ASICREV_IS_RAVEN2(dc->ctx->asic_id.hw_internal_rev)) |
1472 | switch (dc->ctx->asic_id.pci_revision_id) { |
1473 | case PRID_DALI_DE: |
1474 | case PRID_DALI_DF: |
1475 | case PRID_DALI_E3: |
1476 | case PRID_DALI_E4: |
1477 | case PRID_POLLOCK_94: |
1478 | case PRID_POLLOCK_95: |
1479 | case PRID_POLLOCK_E9: |
1480 | case PRID_POLLOCK_EA: |
1481 | case PRID_POLLOCK_EB: |
1482 | dc->config.is_vmin_only_asic = true; |
1483 | break; |
1484 | default: |
1485 | break; |
1486 | } |
1487 | |
1488 | pool->base.pp_smu = dcn10_pp_smu_create(ctx); |
1489 | |
1490 | /* |
1491 | * Right now SMU/PPLIB and DAL all have the AZ D3 force PME notification * |
1492 | * implemented. So AZ D3 should work.For issue 197007. * |
1493 | */ |
1494 | if (pool->base.pp_smu != NULL |
1495 | && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) |
1496 | dc->debug.az_endpoint_mute_only = false; |
1497 | |
1498 | |
1499 | if (!dc->debug.disable_pplib_clock_request) { |
1500 | /* |
1501 | * TODO: This is not the proper way to obtain |
1502 | * fabric_and_dram_bandwidth, should be min(fclk, memclk). |
1503 | */ |
1504 | res = dm_pp_get_clock_levels_by_type_with_voltage( |
1505 | ctx, clk_type: DM_PP_CLOCK_TYPE_FCLK, clk_level_info: &fclks); |
1506 | |
1507 | DC_FP_START(); |
1508 | |
1509 | if (res) |
1510 | res = verify_clock_values(clks: &fclks); |
1511 | |
1512 | if (res) |
1513 | dcn_bw_update_from_pplib_fclks(dc, fclks: &fclks); |
1514 | else |
1515 | BREAK_TO_DEBUGGER(); |
1516 | |
1517 | DC_FP_END(); |
1518 | |
1519 | res = dm_pp_get_clock_levels_by_type_with_voltage( |
1520 | ctx, clk_type: DM_PP_CLOCK_TYPE_DCFCLK, clk_level_info: &dcfclks); |
1521 | |
1522 | DC_FP_START(); |
1523 | |
1524 | if (res) |
1525 | res = verify_clock_values(clks: &dcfclks); |
1526 | |
1527 | if (res) |
1528 | dcn_bw_update_from_pplib_dcfclks(dc, dcfclks: &dcfclks); |
1529 | else |
1530 | BREAK_TO_DEBUGGER(); |
1531 | |
1532 | DC_FP_END(); |
1533 | } |
1534 | |
1535 | dcn_bw_sync_calcs_and_dml(dc); |
1536 | if (!dc->debug.disable_pplib_wm_range) { |
1537 | dc->res_pool = &pool->base; |
1538 | DC_FP_START(); |
1539 | dcn_get_soc_clks( |
1540 | dc, min_fclk_khz: &min_fclk_khz, min_dcfclk_khz: &min_dcfclk_khz, socclk_khz: &socclk_khz); |
1541 | DC_FP_END(); |
1542 | dcn_bw_notify_pplib_of_wm_ranges( |
1543 | dc, min_fclk_khz, min_dcfclk_khz, socclk_khz); |
1544 | } |
1545 | |
1546 | { |
1547 | struct irq_service_init_data init_data; |
1548 | init_data.ctx = dc->ctx; |
1549 | pool->base.irqs = dal_irq_service_dcn10_create(init_data: &init_data); |
1550 | if (!pool->base.irqs) |
1551 | goto fail; |
1552 | } |
1553 | |
1554 | /* index to valid pipe resource */ |
1555 | j = 0; |
1556 | /* mem input -> ipp -> dpp -> opp -> TG */ |
1557 | for (i = 0; i < pool->base.pipe_count; i++) { |
1558 | /* if pipe is disabled, skip instance of HW pipe, |
1559 | * i.e, skip ASIC register instance |
1560 | */ |
1561 | if ((pipe_fuses & (1 << i)) != 0) |
1562 | continue; |
1563 | |
1564 | pool->base.hubps[j] = dcn10_hubp_create(ctx, inst: i); |
1565 | if (pool->base.hubps[j] == NULL) { |
1566 | BREAK_TO_DEBUGGER(); |
1567 | dm_error( |
1568 | "DC: failed to create memory input!\n" ); |
1569 | goto fail; |
1570 | } |
1571 | |
1572 | pool->base.ipps[j] = dcn10_ipp_create(ctx, inst: i); |
1573 | if (pool->base.ipps[j] == NULL) { |
1574 | BREAK_TO_DEBUGGER(); |
1575 | dm_error( |
1576 | "DC: failed to create input pixel processor!\n" ); |
1577 | goto fail; |
1578 | } |
1579 | |
1580 | pool->base.dpps[j] = dcn10_dpp_create(ctx, inst: i); |
1581 | if (pool->base.dpps[j] == NULL) { |
1582 | BREAK_TO_DEBUGGER(); |
1583 | dm_error( |
1584 | "DC: failed to create dpp!\n" ); |
1585 | goto fail; |
1586 | } |
1587 | |
1588 | pool->base.opps[j] = dcn10_opp_create(ctx, inst: i); |
1589 | if (pool->base.opps[j] == NULL) { |
1590 | BREAK_TO_DEBUGGER(); |
1591 | dm_error( |
1592 | "DC: failed to create output pixel processor!\n" ); |
1593 | goto fail; |
1594 | } |
1595 | |
1596 | pool->base.timing_generators[j] = dcn10_timing_generator_create( |
1597 | ctx, instance: i); |
1598 | if (pool->base.timing_generators[j] == NULL) { |
1599 | BREAK_TO_DEBUGGER(); |
1600 | dm_error("DC: failed to create tg!\n" ); |
1601 | goto fail; |
1602 | } |
1603 | /* check next valid pipe */ |
1604 | j++; |
1605 | } |
1606 | |
1607 | for (i = 0; i < pool->base.res_cap->num_ddc; i++) { |
1608 | pool->base.engines[i] = dcn10_aux_engine_create(ctx, inst: i); |
1609 | if (pool->base.engines[i] == NULL) { |
1610 | BREAK_TO_DEBUGGER(); |
1611 | dm_error( |
1612 | "DC:failed to create aux engine!!\n" ); |
1613 | goto fail; |
1614 | } |
1615 | pool->base.hw_i2cs[i] = dcn10_i2c_hw_create(ctx, inst: i); |
1616 | if (pool->base.hw_i2cs[i] == NULL) { |
1617 | BREAK_TO_DEBUGGER(); |
1618 | dm_error( |
1619 | "DC:failed to create hw i2c!!\n" ); |
1620 | goto fail; |
1621 | } |
1622 | pool->base.sw_i2cs[i] = NULL; |
1623 | } |
1624 | |
1625 | /* valid pipe num */ |
1626 | pool->base.pipe_count = j; |
1627 | pool->base.timing_generator_count = j; |
1628 | |
1629 | /* within dml lib, it is hard code to 4. If ASIC pipe is fused, |
1630 | * the value may be changed |
1631 | */ |
1632 | dc->dml.ip.max_num_dpp = pool->base.pipe_count; |
1633 | dc->dcn_ip->max_num_dpp = pool->base.pipe_count; |
1634 | |
1635 | pool->base.mpc = dcn10_mpc_create(ctx); |
1636 | if (pool->base.mpc == NULL) { |
1637 | BREAK_TO_DEBUGGER(); |
1638 | dm_error("DC: failed to create mpc!\n" ); |
1639 | goto fail; |
1640 | } |
1641 | |
1642 | pool->base.hubbub = dcn10_hubbub_create(ctx); |
1643 | if (pool->base.hubbub == NULL) { |
1644 | BREAK_TO_DEBUGGER(); |
1645 | dm_error("DC: failed to create hubbub!\n" ); |
1646 | goto fail; |
1647 | } |
1648 | |
1649 | if (!resource_construct(num_virtual_links, dc, pool: &pool->base, |
1650 | create_funcs: &res_create_funcs)) |
1651 | goto fail; |
1652 | |
1653 | dcn10_hw_sequencer_construct(dc); |
1654 | dc->caps.max_planes = pool->base.pipe_count; |
1655 | |
1656 | for (i = 0; i < dc->caps.max_planes; ++i) |
1657 | dc->caps.planes[i] = plane_cap; |
1658 | |
1659 | dc->cap_funcs = cap_funcs; |
1660 | |
1661 | return true; |
1662 | |
1663 | fail: |
1664 | |
1665 | dcn10_resource_destruct(pool); |
1666 | |
1667 | return false; |
1668 | } |
1669 | |
1670 | struct resource_pool *dcn10_create_resource_pool( |
1671 | const struct dc_init_data *init_data, |
1672 | struct dc *dc) |
1673 | { |
1674 | struct dcn10_resource_pool *pool = |
1675 | kzalloc(size: sizeof(struct dcn10_resource_pool), GFP_KERNEL); |
1676 | |
1677 | if (!pool) |
1678 | return NULL; |
1679 | |
1680 | if (dcn10_resource_construct(num_virtual_links: init_data->num_virtual_links, dc, pool)) |
1681 | return &pool->base; |
1682 | |
1683 | kfree(objp: pool); |
1684 | BREAK_TO_DEBUGGER(); |
1685 | return NULL; |
1686 | } |
1687 | |