| 1 | /* |
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| 2 | * Copyright 2020-2021 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | * Authors: AMD |
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| 23 | * |
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| 24 | */ |
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| 25 | |
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| 26 | #ifndef __DCN30_FPU_H__ |
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| 27 | #define __DCN30_FPU_H__ |
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| 28 | |
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| 29 | #include "core_types.h" |
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| 30 | #include "dcn20/dcn20_optc.h" |
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| 31 | |
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| 32 | void optc3_fpu_set_vrr_m_const(struct timing_generator *optc, |
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| 33 | double vtotal_avg); |
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| 34 | |
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| 35 | void dcn30_fpu_populate_dml_writeback_from_context( |
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| 36 | struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes); |
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| 37 | |
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| 38 | void dcn30_fpu_set_mcif_arb_params(struct mcif_arb_params *wb_arb_params, |
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| 39 | struct display_mode_lib *dml, |
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| 40 | display_e2e_pipe_params_st *pipes, |
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| 41 | int pipe_cnt, |
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| 42 | int cur_pipe); |
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| 43 | |
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| 44 | void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context); |
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| 45 | |
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| 46 | void dcn30_fpu_calculate_wm_and_dlg( |
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| 47 | struct dc *dc, struct dc_state *context, |
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| 48 | display_e2e_pipe_params_st *pipes, |
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| 49 | int pipe_cnt, |
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| 50 | int vlevel); |
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| 51 | |
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| 52 | void dcn30_fpu_update_dram_channel_width_bytes(struct dc *dc); |
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| 53 | |
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| 54 | void dcn30_fpu_update_max_clk(struct dc_bounding_box_max_clk *dcn30_bb_max_clk); |
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| 55 | |
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| 56 | void dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, |
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| 57 | unsigned int *optimal_dcfclk, |
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| 58 | unsigned int *optimal_fclk); |
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| 59 | |
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| 60 | void dcn30_fpu_update_bw_bounding_box(struct dc *dc, |
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| 61 | struct clk_bw_params *bw_params, |
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| 62 | struct dc_bounding_box_max_clk *dcn30_bb_max_clk, |
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| 63 | unsigned int *dcfclk_mhz, |
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| 64 | unsigned int *dram_speed_mts); |
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| 65 | |
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| 66 | int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc, |
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| 67 | struct dc_state *context, |
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| 68 | display_e2e_pipe_params_st *pipes, |
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| 69 | int pipe_cnt, |
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| 70 | int vlevel); |
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| 71 | |
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| 72 | void dcn3_fpu_build_wm_range_table(struct clk_mgr *base); |
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| 73 | |
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| 74 | void patch_dcn30_soc_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *dcn3_0_ip); |
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| 75 | |
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| 76 | #endif /* __DCN30_FPU_H__*/ |
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| 77 | |
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