1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_DCN31_HPO_DP_STREAM_ENCODER_H__
27#define __DAL_DCN31_HPO_DP_STREAM_ENCODER_H__
28
29#include "dcn30/dcn30_vpg.h"
30#include "dcn31/dcn31_apg.h"
31#include "stream_encoder.h"
32
33
34#define DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(hpo_dp_stream_encoder)\
35 container_of(hpo_dp_stream_encoder, struct dcn31_hpo_dp_stream_encoder, base)
36
37
38/* Define MSA_DATA_LANE_[0-3] fields to make programming easier */
39#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_0__SHIFT 0x0
40#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_1__SHIFT 0x8
41#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_2__SHIFT 0x10
42#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_3__SHIFT 0x18
43#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_0_MASK 0x000000FFL
44#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_1_MASK 0x0000FF00L
45#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_2_MASK 0x00FF0000L
46#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_3_MASK 0xFF000000L
47
48
49#define DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id) \
50 SR(DP_STREAM_MAPPER_CONTROL0),\
51 SR(DP_STREAM_MAPPER_CONTROL1),\
52 SR(DP_STREAM_MAPPER_CONTROL2),\
53 SR(DP_STREAM_MAPPER_CONTROL3),\
54 SRI(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id),\
55 SRI(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id),\
56 SRI(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id),\
57 SRI(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id),\
58 SRI(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id),\
59 SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id),\
60 SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),\
61 SRI(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id),\
62 SRI(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id),\
63 SRI(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id),\
64 SRI(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id),\
65 SRI(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id),\
66 SRI(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id),\
67 SRI(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id),\
68 SRI(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id),\
69 SRI(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id),\
70 SRI(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id),\
71 SRI(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),\
72 SRI(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id),\
73 SRI(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id),\
74 SRI(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id),\
75 SRI(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id),\
76 SRI(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id),\
77 SRI(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id),\
78 SRI(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id),\
79 SRI(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id),\
80 SRI(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id),\
81 SRI(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id),\
82 SRI(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id),\
83 SRI(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id), \
84 SRI(DP_SYM32_ENC_HBLANK_CONTROL, DP_SYM32_ENC, id)
85
86#define DCN3_1_HPO_DP_STREAM_ENC_REGS \
87 uint32_t DP_STREAM_MAPPER_CONTROL0;\
88 uint32_t DP_STREAM_MAPPER_CONTROL1;\
89 uint32_t DP_STREAM_MAPPER_CONTROL2;\
90 uint32_t DP_STREAM_MAPPER_CONTROL3;\
91 uint32_t DP_STREAM_ENC_CLOCK_CONTROL;\
92 uint32_t DP_STREAM_ENC_INPUT_MUX_CONTROL;\
93 uint32_t DP_STREAM_ENC_AUDIO_CONTROL;\
94 uint32_t DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0;\
95 uint32_t DP_SYM32_ENC_CONTROL;\
96 uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT;\
97 uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL;\
98 uint32_t DP_SYM32_ENC_VID_MSA0;\
99 uint32_t DP_SYM32_ENC_VID_MSA1;\
100 uint32_t DP_SYM32_ENC_VID_MSA2;\
101 uint32_t DP_SYM32_ENC_VID_MSA3;\
102 uint32_t DP_SYM32_ENC_VID_MSA4;\
103 uint32_t DP_SYM32_ENC_VID_MSA5;\
104 uint32_t DP_SYM32_ENC_VID_MSA6;\
105 uint32_t DP_SYM32_ENC_VID_MSA7;\
106 uint32_t DP_SYM32_ENC_VID_MSA8;\
107 uint32_t DP_SYM32_ENC_VID_MSA_CONTROL;\
108 uint32_t DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL;\
109 uint32_t DP_SYM32_ENC_VID_FIFO_CONTROL;\
110 uint32_t DP_SYM32_ENC_VID_STREAM_CONTROL;\
111 uint32_t DP_SYM32_ENC_VID_VBID_CONTROL;\
112 uint32_t DP_SYM32_ENC_SDP_CONTROL;\
113 uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL0;\
114 uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL2;\
115 uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL3;\
116 uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL5;\
117 uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL11;\
118 uint32_t DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL;\
119 uint32_t DP_SYM32_ENC_SDP_AUDIO_CONTROL0;\
120 uint32_t DP_SYM32_ENC_VID_CRC_CONTROL;\
121 uint32_t DP_SYM32_ENC_HBLANK_CONTROL
122
123
124#define DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh)\
125 SE_SF(DP_STREAM_MAPPER_CONTROL0, DP_STREAM_LINK_TARGET, mask_sh),\
126 SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC_CLOCK_EN, mask_sh),\
127 SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL, mask_sh),\
128 SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, mask_sh),\
129 SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_RESET, mask_sh),\
130 SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_RESET_DONE, mask_sh),\
131 SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_ENABLE, mask_sh),\
132 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_RESET, mask_sh),\
133 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_RESET_DONE, mask_sh),\
134 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_ENABLE, mask_sh),\
135 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, mask_sh),\
136 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, UNCOMPRESSED_PIXEL_ENCODING, mask_sh),\
137 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, UNCOMPRESSED_COMPONENT_DEPTH, mask_sh),\
138 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE, mask_sh),\
139 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, MSA_DOUBLE_BUFFER_ENABLE, mask_sh),\
140 SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_0, mask_sh),\
141 SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_1, mask_sh),\
142 SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_2, mask_sh),\
143 SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_3, mask_sh),\
144 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_RESET, mask_sh),\
145 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_RESET_DONE, mask_sh),\
146 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_ENABLE, mask_sh),\
147 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL, VID_STREAM_ENABLE, mask_sh),\
148 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL, VID_STREAM_STATUS, mask_sh),\
149 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL, VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE, mask_sh),\
150 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL, VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER, mask_sh),\
151 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL, SDP_STREAM_ENABLE, mask_sh),\
152 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, mask_sh),\
153 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_PAYLOAD_SIZE, mask_sh),\
154 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_TRANSMISSION_LINE_NUMBER, mask_sh),\
155 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, mask_sh),\
156 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_TRANSMISSION_LINE_NUMBER, mask_sh),\
157 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_SOF_REFERENCE, mask_sh),\
158 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, METADATA_PACKET_ENABLE, mask_sh),\
159 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, AUDIO_MUTE, mask_sh),\
160 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ASP_ENABLE, mask_sh),\
161 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ATP_ENABLE, mask_sh),\
162 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, AIP_ENABLE, mask_sh),\
163 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ACM_ENABLE, mask_sh),\
164 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_ENABLE, mask_sh),\
165 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_CONT_MODE_ENABLE, mask_sh),\
166 SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL, HBLANK_MINIMUM_SYMBOL_WIDTH, mask_sh)
167
168
169#define DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \
170 type DP_STREAM_LINK_TARGET;\
171 type DP_STREAM_ENC_CLOCK_EN;\
172 type DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL;\
173 type DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL;\
174 type FIFO_RESET;\
175 type FIFO_RESET_DONE;\
176 type FIFO_ENABLE;\
177 type DP_SYM32_ENC_RESET;\
178 type DP_SYM32_ENC_RESET_DONE;\
179 type DP_SYM32_ENC_ENABLE;\
180 type PIXEL_ENCODING_TYPE;\
181 type UNCOMPRESSED_PIXEL_ENCODING;\
182 type UNCOMPRESSED_COMPONENT_DEPTH;\
183 type PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE;\
184 type MSA_DOUBLE_BUFFER_ENABLE;\
185 type MSA_DATA_LANE_0;\
186 type MSA_DATA_LANE_1;\
187 type MSA_DATA_LANE_2;\
188 type MSA_DATA_LANE_3;\
189 type PIXEL_TO_SYMBOL_FIFO_RESET;\
190 type PIXEL_TO_SYMBOL_FIFO_RESET_DONE;\
191 type PIXEL_TO_SYMBOL_FIFO_ENABLE;\
192 type VID_STREAM_ENABLE;\
193 type VID_STREAM_STATUS;\
194 type VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE;\
195 type VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER;\
196 type SDP_STREAM_ENABLE;\
197 type AUDIO_MUTE;\
198 type ASP_ENABLE;\
199 type ATP_ENABLE;\
200 type AIP_ENABLE;\
201 type ACM_ENABLE;\
202 type GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE;\
203 type GSP_PAYLOAD_SIZE;\
204 type GSP_TRANSMISSION_LINE_NUMBER;\
205 type GSP_SOF_REFERENCE;\
206 type METADATA_PACKET_ENABLE;\
207 type CRC_ENABLE;\
208 type CRC_CONT_MODE_ENABLE;\
209 type HBLANK_MINIMUM_SYMBOL_WIDTH
210
211
212struct dcn31_hpo_dp_stream_encoder_registers {
213 DCN3_1_HPO_DP_STREAM_ENC_REGS;
214};
215
216struct dcn31_hpo_dp_stream_encoder_shift {
217 DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t);
218};
219
220struct dcn31_hpo_dp_stream_encoder_mask {
221 DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);
222};
223
224struct dcn31_hpo_dp_stream_encoder {
225 struct hpo_dp_stream_encoder base;
226 const struct dcn31_hpo_dp_stream_encoder_registers *regs;
227 const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift;
228 const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask;
229};
230
231
232void dcn31_hpo_dp_stream_encoder_construct(
233 struct dcn31_hpo_dp_stream_encoder *enc3,
234 struct dc_context *ctx,
235 struct dc_bios *bp,
236 uint32_t inst,
237 enum engine_id eng_id,
238 struct vpg *vpg,
239 struct apg *apg,
240 const struct dcn31_hpo_dp_stream_encoder_registers *regs,
241 const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift,
242 const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask);
243
244
245#endif // __DAL_DCN31_HPO_STREAM_ENCODER_H__
246

source code of linux/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h