| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright 2023 Advanced Micro Devices, Inc. |
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| 4 | * |
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| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 6 | * copy of this software and associated documentation files (the "Software"), |
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| 7 | * to deal in the Software without restriction, including without limitation |
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| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 10 | * Software is furnished to do so, subject to the following conditions: |
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| 11 | * |
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| 12 | * The above copyright notice and this permission notice shall be included in |
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| 13 | * all copies or substantial portions of the Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: AMD |
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| 24 | * |
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| 25 | */ |
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| 26 | |
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| 27 | #ifndef __DC_HUBBUB_DCN35_H__ |
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| 28 | #define __DC_HUBBUB_DCN35_H__ |
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| 29 | |
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| 30 | #include "dcn32/dcn32_hubbub.h" |
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| 31 | |
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| 32 | #define HUBBUB_REG_LIST_DCN35(id)\ |
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| 33 | SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\ |
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| 34 | SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\ |
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| 35 | SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\ |
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| 36 | SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\ |
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| 37 | SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\ |
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| 38 | SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\ |
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| 39 | SR(DCHUBBUB_ARB_SAT_LEVEL),\ |
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| 40 | SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\ |
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| 41 | SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ |
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| 42 | SR(DCHUBBUB_SOFT_RESET),\ |
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| 43 | SR(DCHUBBUB_CRC_CTRL), \ |
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| 44 | SR(DCN_VM_FB_LOCATION_BASE),\ |
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| 45 | SR(DCN_VM_FB_LOCATION_TOP),\ |
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| 46 | SR(DCN_VM_FB_OFFSET),\ |
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| 47 | SR(DCN_VM_AGP_BOT),\ |
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| 48 | SR(DCN_VM_AGP_TOP),\ |
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| 49 | SR(DCN_VM_AGP_BASE),\ |
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| 50 | HUBBUB_SR_WATERMARK_REG_LIST(), \ |
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| 51 | SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A),\ |
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| 52 | SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B),\ |
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| 53 | SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C),\ |
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| 54 | SR(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D),\ |
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| 55 | SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A),\ |
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| 56 | SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\ |
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| 57 | SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\ |
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| 58 | SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\ |
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| 59 | SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\ |
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| 60 | SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\ |
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| 61 | SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\ |
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| 62 | SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\ |
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| 63 | SR(DCHUBBUB_DET0_CTRL),\ |
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| 64 | SR(DCHUBBUB_DET1_CTRL),\ |
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| 65 | SR(DCHUBBUB_DET2_CTRL),\ |
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| 66 | SR(DCHUBBUB_DET3_CTRL),\ |
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| 67 | SR(DCHUBBUB_COMPBUF_CTRL),\ |
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| 68 | SR(COMPBUF_RESERVED_SPACE),\ |
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| 69 | SR(DCHUBBUB_DEBUG_CTRL_0),\ |
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| 70 | SR(DCHUBBUB_ARB_USR_RETRAINING_CNTL),\ |
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| 71 | SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_A),\ |
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| 72 | SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_B),\ |
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| 73 | SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_C),\ |
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| 74 | SR(DCHUBBUB_ARB_USR_RETRAINING_WATERMARK_D),\ |
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| 75 | SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_A),\ |
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| 76 | SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_B),\ |
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| 77 | SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_C),\ |
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| 78 | SR(DCHUBBUB_ARB_UCLK_PSTATE_CHANGE_WATERMARK_D),\ |
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| 79 | SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A),\ |
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| 80 | SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),\ |
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| 81 | SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),\ |
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| 82 | SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),\ |
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| 83 | SR(DCN_VM_FAULT_ADDR_MSB),\ |
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| 84 | SR(DCN_VM_FAULT_ADDR_LSB),\ |
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| 85 | SR(DCN_VM_FAULT_CNTL),\ |
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| 86 | SR(DCN_VM_FAULT_STATUS),\ |
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| 87 | SR(SDPIF_REQUEST_RATE_LIMIT),\ |
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| 88 | SR(DCHUBBUB_CLOCK_CNTL),\ |
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| 89 | SR(DCHUBBUB_SDPIF_CFG0),\ |
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| 90 | SR(DCHUBBUB_SDPIF_CFG1),\ |
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| 91 | SR(DCHUBBUB_MEM_PWR_MODE_CTRL),\ |
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| 92 | SR(DCHUBBUB_ARB_HOSTVM_CNTL),\ |
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| 93 | SR(DCHVM_CTRL0),\ |
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| 94 | SR(DCHVM_MEM_CTRL),\ |
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| 95 | SR(DCHVM_CLK_CTRL),\ |
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| 96 | SR(DCHVM_RIOMMU_CTRL0),\ |
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| 97 | SR(DCHVM_RIOMMU_STAT0),\ |
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| 98 | SR(DCHUBBUB_COMPBUF_CTRL),\ |
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| 99 | SR(COMPBUF_RESERVED_SPACE),\ |
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| 100 | SR(DCHUBBUB_DEBUG_CTRL_0),\ |
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| 101 | SR(DCHUBBUB_CLOCK_CNTL),\ |
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| 102 | SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A),\ |
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| 103 | SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A),\ |
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| 104 | SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B),\ |
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| 105 | SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B),\ |
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| 106 | SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C),\ |
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| 107 | SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C),\ |
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| 108 | SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D),\ |
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| 109 | SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D),\ |
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| 110 | SR(DCHUBBUB_ARB_QOS_FORCE) |
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| 111 | |
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| 112 | |
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| 113 | #define HUBBUB_MASK_SH_LIST_DCN35(mask_sh)\ |
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| 114 | HUBBUB_MASK_SH_LIST_DCN32(mask_sh), \ |
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| 115 | HUBBUB_SF(DCHVM_CTRL0, HOSTVM_INIT_REQ, mask_sh),\ |
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| 116 | HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_PWR_REQ_DIS, mask_sh),\ |
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| 117 | HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_FORCE_REQ, mask_sh),\ |
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| 118 | HUBBUB_SF(DCHVM_MEM_CTRL, HVM_GPUVMRET_POWER_STATUS, mask_sh),\ |
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| 119 | HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_R_GATE_DIS, mask_sh),\ |
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| 120 | HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DISPCLK_G_GATE_DIS, mask_sh),\ |
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| 121 | HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_R_GATE_DIS, mask_sh),\ |
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| 122 | HUBBUB_SF(DCHVM_CLK_CTRL, HVM_DCFCLK_G_GATE_DIS, mask_sh),\ |
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| 123 | HUBBUB_SF(DCHVM_CLK_CTRL, TR_REQ_REQCLKREQ_MODE, mask_sh),\ |
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| 124 | HUBBUB_SF(DCHVM_CLK_CTRL, TW_RSP_COMPCLKREQ_MODE, mask_sh),\ |
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| 125 | HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, mask_sh),\ |
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| 126 | HUBBUB_SF(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, mask_sh),\ |
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| 127 | HUBBUB_SF(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, mask_sh),\ |
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| 128 | HUBBUB_SF(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, mask_sh),\ |
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| 129 | HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE, mask_sh),\ |
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| 130 | HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, COMPBUF_SIZE_CURRENT, mask_sh),\ |
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| 131 | HUBBUB_SF(DCHUBBUB_COMPBUF_CTRL, CONFIG_ERROR, mask_sh),\ |
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| 132 | HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_64B, mask_sh),\ |
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| 133 | HUBBUB_SF(COMPBUF_RESERVED_SPACE, COMPBUF_RESERVED_SPACE_ZS, mask_sh),\ |
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| 134 | HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCHUBBUB_FGCG_REP_DIS, mask_sh),\ |
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| 135 | HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_A, mask_sh), \ |
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| 136 | HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_B, mask_sh), \ |
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| 137 | HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_C, mask_sh), \ |
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| 138 | HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_Z8_D, mask_sh), \ |
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| 139 | HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_A, mask_sh), \ |
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| 140 | HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_B, mask_sh), \ |
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| 141 | HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_C, mask_sh), \ |
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| 142 | HUBBUB_SF(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_Z8_D, mask_sh), \ |
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| 143 | HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_CSTATE_DEEPSLEEP_LEGACY_MODE, mask_sh), \ |
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| 144 | HUBBUB_SF(DCHUBBUB_ARB_HOSTVM_CNTL, DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD, mask_sh),\ |
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| 145 | HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh) |
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| 146 | |
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| 147 | void hubbub35_construct(struct dcn20_hubbub *hubbub2, |
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| 148 | struct dc_context *ctx, |
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| 149 | const struct dcn_hubbub_registers *hubbub_regs, |
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| 150 | const struct dcn_hubbub_shift *hubbub_shift, |
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| 151 | const struct dcn_hubbub_mask *hubbub_mask, |
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| 152 | int det_size_kb, |
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| 153 | int pixel_chunk_size_kb, |
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| 154 | int config_return_buffer_size_kb); |
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| 155 | #endif |
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| 156 | |
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