1 | // SPDX-License-Identifier: MIT |
2 | /* |
3 | * Copyright 2021 Advanced Micro Devices, Inc. |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice shall be included in |
13 | * all copies or substantial portions of the Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
21 | * OTHER DEALINGS IN THE SOFTWARE. |
22 | * |
23 | * Authors: AMD |
24 | * |
25 | */ |
26 | |
27 | #include "dcn10/dcn10_resource.h" |
28 | |
29 | #include "dcn10_fpu.h" |
30 | #include "resource.h" |
31 | #include "amdgpu_dm/dc_fpu.h" |
32 | |
33 | /** |
34 | * DOC: DCN10 FPU manipulation Overview |
35 | * |
36 | * The DCN architecture relies on FPU operations, which require special |
37 | * compilation flags and the use of kernel_fpu_begin/end functions; ideally, we |
38 | * want to avoid spreading FPU access across multiple files. With this idea in |
39 | * mind, this file aims to centralize DCN10 functions that require FPU access |
40 | * in a single place. Code in this file follows the following code pattern: |
41 | * |
42 | * 1. Functions that use FPU operations should be isolated in static functions. |
43 | * 2. The FPU functions should have the noinline attribute to ensure anything |
44 | * that deals with FP register is contained within this call. |
45 | * 3. All function that needs to be accessed outside this file requires a |
46 | * public interface that not uses any FPU reference. |
47 | * 4. Developers **must not** use DC_FP_START/END in this file, but they need |
48 | * to ensure that the caller invokes it before access any function available |
49 | * in this file. For this reason, public functions in this file must invoke |
50 | * dc_assert_fp_enabled(); |
51 | * |
52 | * Let's expand a little bit more the idea in the code pattern. To fully |
53 | * isolate FPU operations in a single place, we must avoid situations where |
54 | * compilers spill FP values to registers due to FP enable in a specific C |
55 | * file. Note that even if we isolate all FPU functions in a single file and |
56 | * call its interface from other files, the compiler might enable the use of |
57 | * FPU before we call DC_FP_START. Nevertheless, it is the programmer's |
58 | * responsibility to invoke DC_FP_START/END in the correct place. To highlight |
59 | * situations where developers forgot to use the FP protection before calling |
60 | * the DC FPU interface functions, we introduce a helper that checks if the |
61 | * function is invoked under FP protection. If not, it will trigger a kernel |
62 | * warning. |
63 | */ |
64 | |
65 | struct _vcs_dpi_ip_params_st dcn1_0_ip = { |
66 | .rob_buffer_size_kbytes = 64, |
67 | .det_buffer_size_kbytes = 164, |
68 | .dpte_buffer_size_in_pte_reqs_luma = 42, |
69 | .dpp_output_buffer_pixels = 2560, |
70 | .opp_output_buffer_lines = 1, |
71 | .pixel_chunk_size_kbytes = 8, |
72 | .pte_enable = 1, |
73 | .pte_chunk_size_kbytes = 2, |
74 | .meta_chunk_size_kbytes = 2, |
75 | .writeback_chunk_size_kbytes = 2, |
76 | .line_buffer_size_bits = 589824, |
77 | .max_line_buffer_lines = 12, |
78 | .IsLineBufferBppFixed = 0, |
79 | .LineBufferFixedBpp = -1, |
80 | .writeback_luma_buffer_size_kbytes = 12, |
81 | .writeback_chroma_buffer_size_kbytes = 8, |
82 | .max_num_dpp = 4, |
83 | .max_num_wb = 2, |
84 | .max_dchub_pscl_bw_pix_per_clk = 4, |
85 | .max_pscl_lb_bw_pix_per_clk = 2, |
86 | .max_lb_vscl_bw_pix_per_clk = 4, |
87 | .max_vscl_hscl_bw_pix_per_clk = 4, |
88 | .max_hscl_ratio = 4, |
89 | .max_vscl_ratio = 4, |
90 | .hscl_mults = 4, |
91 | .vscl_mults = 4, |
92 | .max_hscl_taps = 8, |
93 | .max_vscl_taps = 8, |
94 | .dispclk_ramp_margin_percent = 1, |
95 | .underscan_factor = 1.10, |
96 | .min_vblank_lines = 14, |
97 | .dppclk_delay_subtotal = 90, |
98 | .dispclk_delay_subtotal = 42, |
99 | .dcfclk_cstate_latency = 10, |
100 | .max_inter_dcn_tile_repeaters = 8, |
101 | .can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one = 0, |
102 | .bug_forcing_LC_req_same_size_fixed = 0, |
103 | }; |
104 | |
105 | struct _vcs_dpi_soc_bounding_box_st dcn1_0_soc = { |
106 | .sr_exit_time_us = 9.0, |
107 | .sr_enter_plus_exit_time_us = 11.0, |
108 | .urgent_latency_us = 4.0, |
109 | .writeback_latency_us = 12.0, |
110 | .ideal_dram_bw_after_urgent_percent = 80.0, |
111 | .max_request_size_bytes = 256, |
112 | .downspread_percent = 0.5, |
113 | .dram_page_open_time_ns = 50.0, |
114 | .dram_rw_turnaround_time_ns = 17.5, |
115 | .dram_return_buffer_per_channel_bytes = 8192, |
116 | .round_trip_ping_latency_dcfclk_cycles = 128, |
117 | .urgent_out_of_order_return_per_channel_bytes = 256, |
118 | .channel_interleave_bytes = 256, |
119 | .num_banks = 8, |
120 | .num_chans = 2, |
121 | .vmm_page_size_bytes = 4096, |
122 | .dram_clock_change_latency_us = 17.0, |
123 | .writeback_dram_clock_change_latency_us = 23.0, |
124 | .return_bus_width_bytes = 64, |
125 | }; |
126 | |
127 | void dcn10_resource_construct_fp(struct dc *dc) |
128 | { |
129 | dc_assert_fp_enabled(); |
130 | if (dc->ctx->dce_version == DCN_VERSION_1_01) { |
131 | struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc; |
132 | struct dcn_ip_params *dcn_ip = dc->dcn_ip; |
133 | struct display_mode_lib *dml = &dc->dml; |
134 | |
135 | dml->ip.max_num_dpp = 3; |
136 | /* TODO how to handle 23.84? */ |
137 | dcn_soc->dram_clock_change_latency = 23; |
138 | dcn_ip->max_num_dpp = 3; |
139 | } |
140 | if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) { |
141 | dc->dcn_soc->urgent_latency = 3; |
142 | dc->debug.disable_dmcu = true; |
143 | dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 41.60f; |
144 | } |
145 | |
146 | dc->dcn_soc->number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width; |
147 | ASSERT(dc->dcn_soc->number_of_channels < 3); |
148 | if (dc->dcn_soc->number_of_channels == 0)/*old sbios bug*/ |
149 | dc->dcn_soc->number_of_channels = 2; |
150 | |
151 | if (dc->dcn_soc->number_of_channels == 1) { |
152 | dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 19.2f; |
153 | dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = 17.066f; |
154 | dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = 14.933f; |
155 | dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 12.8f; |
156 | if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) |
157 | dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = 20.80f; |
158 | } |
159 | } |
160 | |