1/*
2 * Copyright 2013-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27#include "include/gpio_types.h"
28#include "../hw_factory.h"
29
30#include "../hw_gpio.h"
31#include "../hw_ddc.h"
32#include "../hw_hpd.h"
33#include "../hw_generic.h"
34
35#include "hw_factory_dce120.h"
36
37#include "dce/dce_12_0_offset.h"
38#include "dce/dce_12_0_sh_mask.h"
39#include "soc15_hw_ip.h"
40#include "vega10_ip_offset.h"
41
42#define block HPD
43#define reg_num 0
44
45/* set field name */
46#define SF_HPD(reg_name, field_name, post_fix)\
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
48
49/* set field name */
50#define SF_HPD(reg_name, field_name, post_fix)\
51 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
52
53#define BASE_INNER(seg) \
54 DCE_BASE__INST0_SEG ## seg
55
56/* compile time expand base address. */
57#define BASE(seg) \
58 BASE_INNER(seg)
59
60#define REG(reg_name)\
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
62
63#define REGI(reg_name, block, id)\
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
66
67
68#include "reg_helper.h"
69#include "../hpd_regs.h"
70
71#define hpd_regs(id) \
72{\
73 HPD_REG_LIST(id)\
74}
75
76static const struct hpd_registers hpd_regs[] = {
77 hpd_regs(0),
78 hpd_regs(1),
79 hpd_regs(2),
80 hpd_regs(3),
81 hpd_regs(4),
82 hpd_regs(5)
83};
84
85static const struct hpd_sh_mask hpd_shift = {
86 HPD_MASK_SH_LIST(__SHIFT)
87};
88
89static const struct hpd_sh_mask hpd_mask = {
90 HPD_MASK_SH_LIST(_MASK)
91};
92
93#include "../ddc_regs.h"
94
95 /* set field name */
96#define SF_DDC(reg_name, field_name, post_fix)\
97 .field_name = reg_name ## __ ## field_name ## post_fix
98
99static const struct ddc_registers ddc_data_regs[] = {
100 ddc_data_regs(1),
101 ddc_data_regs(2),
102 ddc_data_regs(3),
103 ddc_data_regs(4),
104 ddc_data_regs(5),
105 ddc_data_regs(6),
106 ddc_vga_data_regs,
107 ddc_i2c_data_regs
108};
109
110static const struct ddc_registers ddc_clk_regs[] = {
111 ddc_clk_regs(1),
112 ddc_clk_regs(2),
113 ddc_clk_regs(3),
114 ddc_clk_regs(4),
115 ddc_clk_regs(5),
116 ddc_clk_regs(6),
117 ddc_vga_clk_regs,
118 ddc_i2c_clk_regs
119};
120
121static const struct ddc_sh_mask ddc_shift = {
122 DDC_MASK_SH_LIST(__SHIFT)
123};
124
125static const struct ddc_sh_mask ddc_mask = {
126 DDC_MASK_SH_LIST(_MASK)
127};
128
129static void define_ddc_registers(
130 struct hw_gpio_pin *pin,
131 uint32_t en)
132{
133 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
134
135 switch (pin->id) {
136 case GPIO_ID_DDC_DATA:
137 ddc->regs = &ddc_data_regs[en];
138 ddc->base.regs = &ddc_data_regs[en].gpio;
139 break;
140 case GPIO_ID_DDC_CLOCK:
141 ddc->regs = &ddc_clk_regs[en];
142 ddc->base.regs = &ddc_clk_regs[en].gpio;
143 break;
144 default:
145 ASSERT_CRITICAL(false);
146 return;
147 }
148
149 ddc->shifts = &ddc_shift;
150 ddc->masks = &ddc_mask;
151
152}
153
154static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
155{
156 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
157
158 hpd->regs = &hpd_regs[en];
159 hpd->shifts = &hpd_shift;
160 hpd->masks = &hpd_mask;
161 hpd->base.regs = &hpd_regs[en].gpio;
162}
163
164
165/* function table */
166static const struct hw_factory_funcs funcs = {
167 .init_ddc_data = dal_hw_ddc_init,
168 .init_generic = NULL,
169 .init_hpd = dal_hw_hpd_init,
170 .get_ddc_pin = dal_hw_ddc_get_pin,
171 .get_hpd_pin = dal_hw_hpd_get_pin,
172 .get_generic_pin = NULL,
173 .define_hpd_registers = define_hpd_registers,
174 .define_ddc_registers = define_ddc_registers
175};
176/*
177 * dal_hw_factory_dce120_init
178 *
179 * @brief
180 * Initialize HW factory function pointers and pin info
181 *
182 * @param
183 * struct hw_factory *factory - [out] struct of function pointers
184 */
185void dal_hw_factory_dce120_init(struct hw_factory *factory)
186{
187 /*TODO check ASIC CAPs*/
188 factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
189 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
190 factory->number_of_pins[GPIO_ID_GENERIC] = 7;
191 factory->number_of_pins[GPIO_ID_HPD] = 6;
192 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
193 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
194 factory->number_of_pins[GPIO_ID_SYNC] = 2;
195 factory->number_of_pins[GPIO_ID_GSL] = 4;
196
197 factory->funcs = &funcs;
198}
199

source code of linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c