1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | |
26 | #ifndef __DC_HWSS_DCN32_H__ |
27 | #define __DC_HWSS_DCN32_H__ |
28 | |
29 | #include "hw_sequencer_private.h" |
30 | |
31 | struct dc; |
32 | |
33 | void dcn32_dsc_pg_control( |
34 | struct dce_hwseq *hws, |
35 | unsigned int dsc_inst, |
36 | bool power_on); |
37 | |
38 | void dcn32_enable_power_gating_plane( |
39 | struct dce_hwseq *hws, |
40 | bool enable); |
41 | |
42 | void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); |
43 | |
44 | bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable); |
45 | |
46 | void dcn32_cab_for_ss_control(struct dc *dc, bool enable); |
47 | |
48 | void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context); |
49 | |
50 | bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx, |
51 | const struct dc_plane_state *plane_state); |
52 | |
53 | bool dcn32_set_input_transfer_func(struct dc *dc, |
54 | struct pipe_ctx *pipe_ctx, |
55 | const struct dc_plane_state *plane_state); |
56 | |
57 | bool dcn32_set_mpc_shaper_3dlut( |
58 | struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream); |
59 | |
60 | bool dcn32_set_output_transfer_func(struct dc *dc, |
61 | struct pipe_ctx *pipe_ctx, |
62 | const struct dc_stream_state *stream); |
63 | |
64 | void dcn32_init_hw(struct dc *dc); |
65 | |
66 | void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context); |
67 | |
68 | void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context); |
69 | |
70 | void dcn32_update_force_pstate(struct dc *dc, struct dc_state *context); |
71 | |
72 | void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx); |
73 | |
74 | unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div); |
75 | |
76 | void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx); |
77 | |
78 | void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context); |
79 | |
80 | void dcn32_subvp_pipe_control_lock(struct dc *dc, |
81 | struct dc_state *context, |
82 | bool lock, |
83 | bool should_lock_all_pipes, |
84 | struct pipe_ctx *top_pipe_to_program, |
85 | bool subvp_prev_use); |
86 | |
87 | void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params); |
88 | |
89 | void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx, |
90 | struct dc_link_settings *link_settings); |
91 | |
92 | bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx); |
93 | |
94 | void dcn32_disable_link_output(struct dc_link *link, |
95 | const struct link_resource *link_res, |
96 | enum signal_type signal); |
97 | |
98 | void dcn32_update_phantom_vp_position(struct dc *dc, |
99 | struct dc_state *context, |
100 | struct pipe_ctx *phantom_pipe); |
101 | |
102 | void dcn32_apply_update_flags_for_phantom(struct pipe_ctx *phantom_pipe); |
103 | |
104 | bool dcn32_dsc_pg_status( |
105 | struct dce_hwseq *hws, |
106 | unsigned int dsc_inst); |
107 | |
108 | void dcn32_update_dsc_pg(struct dc *dc, |
109 | struct dc_state *context, |
110 | bool safe_to_disable); |
111 | |
112 | void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context); |
113 | |
114 | void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context); |
115 | |
116 | void dcn32_init_blank( |
117 | struct dc *dc, |
118 | struct timing_generator *tg); |
119 | |
120 | void dcn32_blank_phantom(struct dc *dc, |
121 | struct timing_generator *tg, |
122 | int width, |
123 | int height); |
124 | |
125 | bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc, |
126 | const struct dc_state *cur_ctx, |
127 | const struct dc_state *new_ctx); |
128 | |
129 | void dcn32_prepare_bandwidth(struct dc *dc, |
130 | struct dc_state *context); |
131 | |
132 | void dcn32_interdependent_update_lock(struct dc *dc, |
133 | struct dc_state *context, bool lock); |
134 | #endif /* __DC_HWSS_DCN32_H__ */ |
135 | |