| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2022 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __ICL_DSI_REGS_H__ |
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| 7 | #define __ICL_DSI_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | /* Gen11 DSI */ |
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| 12 | #define _MMIO_DSI(tc, dsi0, dsi1) _MMIO_TRANS((tc) - TRANSCODER_DSI_0, \ |
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| 13 | dsi0, dsi1) |
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| 14 | #define _ICL_DSI_ESC_CLK_DIV0 0x6b090 |
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| 15 | #define _ICL_DSI_ESC_CLK_DIV1 0x6b890 |
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| 16 | #define ICL_DSI_ESC_CLK_DIV(port) _MMIO_PORT((port), \ |
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| 17 | _ICL_DSI_ESC_CLK_DIV0, \ |
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| 18 | _ICL_DSI_ESC_CLK_DIV1) |
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| 19 | #define _ICL_DPHY_ESC_CLK_DIV0 0x162190 |
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| 20 | #define _ICL_DPHY_ESC_CLK_DIV1 0x6C190 |
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| 21 | #define ICL_DPHY_ESC_CLK_DIV(port) _MMIO_PORT((port), \ |
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| 22 | _ICL_DPHY_ESC_CLK_DIV0, \ |
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| 23 | _ICL_DPHY_ESC_CLK_DIV1) |
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| 24 | #define ICL_BYTE_CLK_PER_ESC_CLK_MASK (0x1f << 16) |
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| 25 | #define ICL_BYTE_CLK_PER_ESC_CLK_SHIFT 16 |
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| 26 | #define ICL_ESC_CLK_DIV_MASK 0x1ff |
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| 27 | #define ICL_ESC_CLK_DIV_SHIFT 0 |
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| 28 | #define DSI_MAX_ESC_CLK 20000 /* in KHz */ |
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| 29 | |
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| 30 | #define _ADL_MIPIO_REG 0x180 |
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| 31 | #define ADL_MIPIO_DW(port, dw) _MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw)) |
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| 32 | #define TX_ESC_CLK_DIV_PHY_SEL REGBIT(16) |
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| 33 | #define TX_ESC_CLK_DIV_PHY_MASK REG_GENMASK(23, 16) |
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| 34 | #define TX_ESC_CLK_DIV_PHY REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f) |
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| 35 | |
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| 36 | #define _DSI_CMD_FRMCTL_0 0x6b034 |
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| 37 | #define _DSI_CMD_FRMCTL_1 0x6b834 |
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| 38 | #define DSI_CMD_FRMCTL(port) _MMIO_PORT(port, \ |
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| 39 | _DSI_CMD_FRMCTL_0,\ |
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| 40 | _DSI_CMD_FRMCTL_1) |
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| 41 | #define DSI_FRAME_UPDATE_REQUEST (1 << 31) |
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| 42 | #define DSI_PERIODIC_FRAME_UPDATE_ENABLE (1 << 29) |
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| 43 | #define DSI_NULL_PACKET_ENABLE (1 << 28) |
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| 44 | #define DSI_FRAME_IN_PROGRESS (1 << 0) |
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| 45 | |
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| 46 | #define _DSI_INTR_MASK_REG_0 0x6b070 |
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| 47 | #define _DSI_INTR_MASK_REG_1 0x6b870 |
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| 48 | #define DSI_INTR_MASK_REG(port) _MMIO_PORT(port, \ |
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| 49 | _DSI_INTR_MASK_REG_0,\ |
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| 50 | _DSI_INTR_MASK_REG_1) |
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| 51 | |
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| 52 | #define _DSI_INTR_IDENT_REG_0 0x6b074 |
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| 53 | #define _DSI_INTR_IDENT_REG_1 0x6b874 |
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| 54 | #define DSI_INTR_IDENT_REG(port) _MMIO_PORT(port, \ |
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| 55 | _DSI_INTR_IDENT_REG_0,\ |
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| 56 | _DSI_INTR_IDENT_REG_1) |
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| 57 | #define DSI_TE_EVENT (1 << 31) |
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| 58 | #define DSI_RX_DATA_OR_BTA_TERMINATED (1 << 30) |
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| 59 | #define DSI_TX_DATA (1 << 29) |
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| 60 | #define DSI_ULPS_ENTRY_DONE (1 << 28) |
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| 61 | #define DSI_NON_TE_TRIGGER_RECEIVED (1 << 27) |
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| 62 | #define DSI_HOST_CHKSUM_ERROR (1 << 26) |
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| 63 | #define DSI_HOST_MULTI_ECC_ERROR (1 << 25) |
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| 64 | #define DSI_HOST_SINGL_ECC_ERROR (1 << 24) |
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| 65 | #define DSI_HOST_CONTENTION_DETECTED (1 << 23) |
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| 66 | #define DSI_HOST_FALSE_CONTROL_ERROR (1 << 22) |
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| 67 | #define DSI_HOST_TIMEOUT_ERROR (1 << 21) |
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| 68 | #define DSI_HOST_LOW_POWER_TX_SYNC_ERROR (1 << 20) |
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| 69 | #define DSI_HOST_ESCAPE_MODE_ENTRY_ERROR (1 << 19) |
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| 70 | #define DSI_FRAME_UPDATE_DONE (1 << 16) |
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| 71 | #define DSI_PROTOCOL_VIOLATION_REPORTED (1 << 15) |
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| 72 | #define DSI_INVALID_TX_LENGTH (1 << 13) |
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| 73 | #define DSI_INVALID_VC (1 << 12) |
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| 74 | #define DSI_INVALID_DATA_TYPE (1 << 11) |
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| 75 | #define DSI_PERIPHERAL_CHKSUM_ERROR (1 << 10) |
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| 76 | #define DSI_PERIPHERAL_MULTI_ECC_ERROR (1 << 9) |
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| 77 | #define DSI_PERIPHERAL_SINGLE_ECC_ERROR (1 << 8) |
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| 78 | #define DSI_PERIPHERAL_CONTENTION_DETECTED (1 << 7) |
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| 79 | #define DSI_PERIPHERAL_FALSE_CTRL_ERROR (1 << 6) |
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| 80 | #define DSI_PERIPHERAL_TIMEOUT_ERROR (1 << 5) |
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| 81 | #define DSI_PERIPHERAL_LP_TX_SYNC_ERROR (1 << 4) |
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| 82 | #define DSI_PERIPHERAL_ESC_MODE_ENTRY_CMD_ERR (1 << 3) |
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| 83 | #define DSI_EOT_SYNC_ERROR (1 << 2) |
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| 84 | #define DSI_SOT_SYNC_ERROR (1 << 1) |
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| 85 | #define DSI_SOT_ERROR (1 << 0) |
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| 86 | |
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| 87 | /* ICL DSI MODE control */ |
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| 88 | #define _ICL_DSI_IO_MODECTL_0 0x6B094 |
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| 89 | #define _ICL_DSI_IO_MODECTL_1 0x6B894 |
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| 90 | #define ICL_DSI_IO_MODECTL(port) _MMIO_PORT(port, \ |
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| 91 | _ICL_DSI_IO_MODECTL_0, \ |
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| 92 | _ICL_DSI_IO_MODECTL_1) |
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| 93 | #define COMBO_PHY_MODE_DSI (1 << 0) |
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| 94 | |
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| 95 | /* TGL DSI Chicken register */ |
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| 96 | #define _TGL_DSI_CHKN_REG_0 0x6B0C0 |
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| 97 | #define _TGL_DSI_CHKN_REG_1 0x6B8C0 |
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| 98 | #define TGL_DSI_CHKN_REG(port) _MMIO_PORT(port, \ |
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| 99 | _TGL_DSI_CHKN_REG_0, \ |
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| 100 | _TGL_DSI_CHKN_REG_1) |
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| 101 | #define TGL_DSI_CHKN_LSHS_GB_MASK REG_GENMASK(15, 12) |
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| 102 | #define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \ |
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| 103 | (byte_clocks)) |
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| 104 | #define _ICL_DSI_T_INIT_MASTER_0 0x6b088 |
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| 105 | #define _ICL_DSI_T_INIT_MASTER_1 0x6b888 |
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| 106 | #define ICL_DSI_T_INIT_MASTER(port) _MMIO_PORT(port, \ |
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| 107 | _ICL_DSI_T_INIT_MASTER_0,\ |
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| 108 | _ICL_DSI_T_INIT_MASTER_1) |
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| 109 | #define DSI_T_INIT_MASTER_MASK REG_GENMASK(15, 0) |
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| 110 | |
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| 111 | #define _DPHY_CLK_TIMING_PARAM_0 0x162180 |
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| 112 | #define _DPHY_CLK_TIMING_PARAM_1 0x6c180 |
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| 113 | #define DPHY_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ |
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| 114 | _DPHY_CLK_TIMING_PARAM_0,\ |
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| 115 | _DPHY_CLK_TIMING_PARAM_1) |
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| 116 | #define _DSI_CLK_TIMING_PARAM_0 0x6b080 |
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| 117 | #define _DSI_CLK_TIMING_PARAM_1 0x6b880 |
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| 118 | #define DSI_CLK_TIMING_PARAM(port) _MMIO_PORT(port, \ |
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| 119 | _DSI_CLK_TIMING_PARAM_0,\ |
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| 120 | _DSI_CLK_TIMING_PARAM_1) |
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| 121 | #define CLK_PREPARE_OVERRIDE (1 << 31) |
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| 122 | #define CLK_PREPARE(x) ((x) << 28) |
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| 123 | #define CLK_PREPARE_MASK (0x7 << 28) |
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| 124 | #define CLK_PREPARE_SHIFT 28 |
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| 125 | #define CLK_ZERO_OVERRIDE (1 << 27) |
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| 126 | #define CLK_ZERO(x) ((x) << 20) |
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| 127 | #define CLK_ZERO_MASK (0xf << 20) |
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| 128 | #define CLK_ZERO_SHIFT 20 |
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| 129 | #define CLK_PRE_OVERRIDE (1 << 19) |
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| 130 | #define CLK_PRE(x) ((x) << 16) |
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| 131 | #define CLK_PRE_MASK (0x3 << 16) |
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| 132 | #define CLK_PRE_SHIFT 16 |
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| 133 | #define CLK_POST_OVERRIDE (1 << 15) |
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| 134 | #define CLK_POST(x) ((x) << 8) |
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| 135 | #define CLK_POST_MASK (0x7 << 8) |
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| 136 | #define CLK_POST_SHIFT 8 |
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| 137 | #define CLK_TRAIL_OVERRIDE (1 << 7) |
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| 138 | #define CLK_TRAIL(x) ((x) << 0) |
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| 139 | #define CLK_TRAIL_MASK (0xf << 0) |
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| 140 | #define CLK_TRAIL_SHIFT 0 |
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| 141 | |
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| 142 | #define _DPHY_DATA_TIMING_PARAM_0 0x162184 |
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| 143 | #define _DPHY_DATA_TIMING_PARAM_1 0x6c184 |
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| 144 | #define DPHY_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ |
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| 145 | _DPHY_DATA_TIMING_PARAM_0,\ |
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| 146 | _DPHY_DATA_TIMING_PARAM_1) |
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| 147 | #define _DSI_DATA_TIMING_PARAM_0 0x6B084 |
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| 148 | #define _DSI_DATA_TIMING_PARAM_1 0x6B884 |
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| 149 | #define DSI_DATA_TIMING_PARAM(port) _MMIO_PORT(port, \ |
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| 150 | _DSI_DATA_TIMING_PARAM_0,\ |
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| 151 | _DSI_DATA_TIMING_PARAM_1) |
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| 152 | #define HS_PREPARE_OVERRIDE (1 << 31) |
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| 153 | #define HS_PREPARE(x) ((x) << 24) |
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| 154 | #define HS_PREPARE_MASK (0x7 << 24) |
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| 155 | #define HS_PREPARE_SHIFT 24 |
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| 156 | #define HS_ZERO_OVERRIDE (1 << 23) |
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| 157 | #define HS_ZERO(x) ((x) << 16) |
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| 158 | #define HS_ZERO_MASK (0xf << 16) |
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| 159 | #define HS_ZERO_SHIFT 16 |
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| 160 | #define HS_TRAIL_OVERRIDE (1 << 15) |
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| 161 | #define HS_TRAIL(x) ((x) << 8) |
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| 162 | #define HS_TRAIL_MASK (0x7 << 8) |
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| 163 | #define HS_TRAIL_SHIFT 8 |
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| 164 | #define HS_EXIT_OVERRIDE (1 << 7) |
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| 165 | #define HS_EXIT(x) ((x) << 0) |
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| 166 | #define HS_EXIT_MASK (0x7 << 0) |
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| 167 | #define HS_EXIT_SHIFT 0 |
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| 168 | |
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| 169 | #define _DPHY_TA_TIMING_PARAM_0 0x162188 |
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| 170 | #define _DPHY_TA_TIMING_PARAM_1 0x6c188 |
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| 171 | #define DPHY_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ |
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| 172 | _DPHY_TA_TIMING_PARAM_0,\ |
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| 173 | _DPHY_TA_TIMING_PARAM_1) |
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| 174 | #define _DSI_TA_TIMING_PARAM_0 0x6b098 |
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| 175 | #define _DSI_TA_TIMING_PARAM_1 0x6b898 |
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| 176 | #define DSI_TA_TIMING_PARAM(port) _MMIO_PORT(port, \ |
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| 177 | _DSI_TA_TIMING_PARAM_0,\ |
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| 178 | _DSI_TA_TIMING_PARAM_1) |
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| 179 | #define TA_SURE_OVERRIDE (1 << 31) |
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| 180 | #define TA_SURE(x) ((x) << 16) |
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| 181 | #define TA_SURE_MASK (0x1f << 16) |
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| 182 | #define TA_SURE_SHIFT 16 |
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| 183 | #define TA_GO_OVERRIDE (1 << 15) |
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| 184 | #define TA_GO(x) ((x) << 8) |
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| 185 | #define TA_GO_MASK (0xf << 8) |
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| 186 | #define TA_GO_SHIFT 8 |
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| 187 | #define TA_GET_OVERRIDE (1 << 7) |
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| 188 | #define TA_GET(x) ((x) << 0) |
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| 189 | #define TA_GET_MASK (0xf << 0) |
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| 190 | #define TA_GET_SHIFT 0 |
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| 191 | |
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| 192 | /* DSI transcoder configuration */ |
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| 193 | #define _DSI_TRANS_FUNC_CONF_0 0x6b030 |
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| 194 | #define _DSI_TRANS_FUNC_CONF_1 0x6b830 |
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| 195 | #define DSI_TRANS_FUNC_CONF(tc) _MMIO_DSI(tc, \ |
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| 196 | _DSI_TRANS_FUNC_CONF_0,\ |
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| 197 | _DSI_TRANS_FUNC_CONF_1) |
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| 198 | #define OP_MODE_MASK (0x3 << 28) |
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| 199 | #define OP_MODE_SHIFT 28 |
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| 200 | #define CMD_MODE_NO_GATE (0x0 << 28) |
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| 201 | #define CMD_MODE_TE_GATE (0x1 << 28) |
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| 202 | #define VIDEO_MODE_SYNC_EVENT (0x2 << 28) |
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| 203 | #define VIDEO_MODE_SYNC_PULSE (0x3 << 28) |
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| 204 | #define TE_SOURCE_GPIO (1 << 27) |
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| 205 | #define LINK_READY (1 << 20) |
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| 206 | #define PIX_FMT_MASK (0x3 << 16) |
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| 207 | #define PIX_FMT_SHIFT 16 |
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| 208 | #define PIX_FMT_RGB565 (0x0 << 16) |
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| 209 | #define PIX_FMT_RGB666_PACKED (0x1 << 16) |
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| 210 | #define PIX_FMT_RGB666_LOOSE (0x2 << 16) |
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| 211 | #define PIX_FMT_RGB888 (0x3 << 16) |
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| 212 | #define PIX_FMT_RGB101010 (0x4 << 16) |
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| 213 | #define PIX_FMT_RGB121212 (0x5 << 16) |
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| 214 | #define PIX_FMT_COMPRESSED (0x6 << 16) |
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| 215 | #define BGR_TRANSMISSION (1 << 15) |
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| 216 | #define PIX_VIRT_CHAN(x) ((x) << 12) |
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| 217 | #define PIX_VIRT_CHAN_MASK (0x3 << 12) |
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| 218 | #define PIX_VIRT_CHAN_SHIFT 12 |
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| 219 | #define PIX_BUF_THRESHOLD_MASK (0x3 << 10) |
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| 220 | #define PIX_BUF_THRESHOLD_SHIFT 10 |
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| 221 | #define PIX_BUF_THRESHOLD_1_4 (0x0 << 10) |
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| 222 | #define PIX_BUF_THRESHOLD_1_2 (0x1 << 10) |
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| 223 | #define PIX_BUF_THRESHOLD_3_4 (0x2 << 10) |
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| 224 | #define PIX_BUF_THRESHOLD_FULL (0x3 << 10) |
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| 225 | #define CONTINUOUS_CLK_MASK (0x3 << 8) |
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| 226 | #define CONTINUOUS_CLK_SHIFT 8 |
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| 227 | #define CLK_ENTER_LP_AFTER_DATA (0x0 << 8) |
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| 228 | #define CLK_HS_OR_LP (0x2 << 8) |
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| 229 | #define CLK_HS_CONTINUOUS (0x3 << 8) |
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| 230 | #define LINK_CALIBRATION_MASK (0x3 << 4) |
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| 231 | #define LINK_CALIBRATION_SHIFT 4 |
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| 232 | #define CALIBRATION_DISABLED (0x0 << 4) |
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| 233 | #define CALIBRATION_ENABLED_INITIAL_ONLY (0x2 << 4) |
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| 234 | #define CALIBRATION_ENABLED_INITIAL_PERIODIC (0x3 << 4) |
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| 235 | #define BLANKING_PACKET_ENABLE (1 << 2) |
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| 236 | #define S3D_ORIENTATION_LANDSCAPE (1 << 1) |
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| 237 | #define EOTP_DISABLED (1 << 0) |
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| 238 | |
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| 239 | #define _DSI_CMD_RXCTL_0 0x6b0d4 |
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| 240 | #define _DSI_CMD_RXCTL_1 0x6b8d4 |
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| 241 | #define DSI_CMD_RXCTL(tc) _MMIO_DSI(tc, \ |
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| 242 | _DSI_CMD_RXCTL_0,\ |
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| 243 | _DSI_CMD_RXCTL_1) |
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| 244 | #define READ_UNLOADS_DW (1 << 16) |
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| 245 | #define RECEIVED_UNASSIGNED_TRIGGER (1 << 15) |
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| 246 | #define RECEIVED_ACKNOWLEDGE_TRIGGER (1 << 14) |
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| 247 | #define RECEIVED_TEAR_EFFECT_TRIGGER (1 << 13) |
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| 248 | #define RECEIVED_RESET_TRIGGER (1 << 12) |
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| 249 | #define RECEIVED_PAYLOAD_WAS_LOST (1 << 11) |
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| 250 | #define RECEIVED_CRC_WAS_LOST (1 << 10) |
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| 251 | #define NUMBER_RX_PLOAD_DW_MASK (0xff << 0) |
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| 252 | #define NUMBER_RX_PLOAD_DW_SHIFT 0 |
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| 253 | |
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| 254 | #define _DSI_CMD_TXCTL_0 0x6b0d0 |
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| 255 | #define _DSI_CMD_TXCTL_1 0x6b8d0 |
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| 256 | #define DSI_CMD_TXCTL(tc) _MMIO_DSI(tc, \ |
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| 257 | _DSI_CMD_TXCTL_0,\ |
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| 258 | _DSI_CMD_TXCTL_1) |
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| 259 | #define KEEP_LINK_IN_HS (1 << 24) |
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| 260 | #define (0x1f << 8) |
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| 261 | #define 0x8 |
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| 262 | #define FREE_PLOAD_CREDIT_MASK (0xff << 0) |
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| 263 | #define FREE_PLOAD_CREDIT_SHIFT 0 |
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| 264 | #define 0x10 |
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| 265 | #define MAX_PLOAD_CREDIT 0x40 |
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| 266 | |
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| 267 | #define _DSI_CMD_TXHDR_0 0x6b100 |
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| 268 | #define _DSI_CMD_TXHDR_1 0x6b900 |
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| 269 | #define DSI_CMD_TXHDR(tc) _MMIO_DSI(tc, \ |
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| 270 | _DSI_CMD_TXHDR_0,\ |
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| 271 | _DSI_CMD_TXHDR_1) |
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| 272 | #define PAYLOAD_PRESENT (1 << 31) |
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| 273 | #define LP_DATA_TRANSFER (1 << 30) |
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| 274 | #define VBLANK_FENCE (1 << 29) |
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| 275 | #define PARAM_WC_MASK (0xffff << 8) |
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| 276 | #define PARAM_WC_LOWER_SHIFT 8 |
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| 277 | #define PARAM_WC_UPPER_SHIFT 16 |
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| 278 | #define VC_MASK (0x3 << 6) |
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| 279 | #define VC_SHIFT 6 |
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| 280 | #define DT_MASK (0x3f << 0) |
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| 281 | #define DT_SHIFT 0 |
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| 282 | |
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| 283 | #define _DSI_CMD_TXPYLD_0 0x6b104 |
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| 284 | #define _DSI_CMD_TXPYLD_1 0x6b904 |
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| 285 | #define DSI_CMD_TXPYLD(tc) _MMIO_DSI(tc, \ |
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| 286 | _DSI_CMD_TXPYLD_0,\ |
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| 287 | _DSI_CMD_TXPYLD_1) |
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| 288 | |
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| 289 | #define _DSI_LP_MSG_0 0x6b0d8 |
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| 290 | #define _DSI_LP_MSG_1 0x6b8d8 |
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| 291 | #define DSI_LP_MSG(tc) _MMIO_DSI(tc, \ |
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| 292 | _DSI_LP_MSG_0,\ |
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| 293 | _DSI_LP_MSG_1) |
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| 294 | #define LPTX_IN_PROGRESS (1 << 17) |
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| 295 | #define LINK_IN_ULPS (1 << 16) |
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| 296 | #define LINK_ULPS_TYPE_LP11 (1 << 8) |
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| 297 | #define LINK_ENTER_ULPS (1 << 0) |
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| 298 | |
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| 299 | /* DSI timeout registers */ |
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| 300 | #define _DSI_HSTX_TO_0 0x6b044 |
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| 301 | #define _DSI_HSTX_TO_1 0x6b844 |
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| 302 | #define DSI_HSTX_TO(tc) _MMIO_DSI(tc, \ |
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| 303 | _DSI_HSTX_TO_0,\ |
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| 304 | _DSI_HSTX_TO_1) |
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| 305 | #define HSTX_TIMEOUT_VALUE_MASK (0xffff << 16) |
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| 306 | #define HSTX_TIMEOUT_VALUE_SHIFT 16 |
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| 307 | #define HSTX_TIMEOUT_VALUE(x) ((x) << 16) |
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| 308 | #define HSTX_TIMED_OUT (1 << 0) |
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| 309 | |
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| 310 | #define _DSI_LPRX_HOST_TO_0 0x6b048 |
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| 311 | #define _DSI_LPRX_HOST_TO_1 0x6b848 |
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| 312 | #define DSI_LPRX_HOST_TO(tc) _MMIO_DSI(tc, \ |
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| 313 | _DSI_LPRX_HOST_TO_0,\ |
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| 314 | _DSI_LPRX_HOST_TO_1) |
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| 315 | #define LPRX_TIMED_OUT (1 << 16) |
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| 316 | #define LPRX_TIMEOUT_VALUE_MASK (0xffff << 0) |
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| 317 | #define LPRX_TIMEOUT_VALUE_SHIFT 0 |
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| 318 | #define LPRX_TIMEOUT_VALUE(x) ((x) << 0) |
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| 319 | |
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| 320 | #define _DSI_PWAIT_TO_0 0x6b040 |
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| 321 | #define _DSI_PWAIT_TO_1 0x6b840 |
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| 322 | #define DSI_PWAIT_TO(tc) _MMIO_DSI(tc, \ |
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| 323 | _DSI_PWAIT_TO_0,\ |
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| 324 | _DSI_PWAIT_TO_1) |
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| 325 | #define PRESET_TIMEOUT_VALUE_MASK (0xffff << 16) |
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| 326 | #define PRESET_TIMEOUT_VALUE_SHIFT 16 |
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| 327 | #define PRESET_TIMEOUT_VALUE(x) ((x) << 16) |
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| 328 | #define PRESPONSE_TIMEOUT_VALUE_MASK (0xffff << 0) |
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| 329 | #define PRESPONSE_TIMEOUT_VALUE_SHIFT 0 |
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| 330 | #define PRESPONSE_TIMEOUT_VALUE(x) ((x) << 0) |
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| 331 | |
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| 332 | #define _DSI_TA_TO_0 0x6b04c |
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| 333 | #define _DSI_TA_TO_1 0x6b84c |
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| 334 | #define DSI_TA_TO(tc) _MMIO_DSI(tc, \ |
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| 335 | _DSI_TA_TO_0,\ |
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| 336 | _DSI_TA_TO_1) |
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| 337 | #define TA_TIMED_OUT (1 << 16) |
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| 338 | #define TA_TIMEOUT_VALUE_MASK (0xffff << 0) |
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| 339 | #define TA_TIMEOUT_VALUE_SHIFT 0 |
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| 340 | #define TA_TIMEOUT_VALUE(x) ((x) << 0) |
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| 341 | |
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| 342 | #endif /* __ICL_DSI_REGS_H__ */ |
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| 343 | |
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