1	/*
2	* Copyright © 2018 Intel Corporation
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.
14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21	* DEALINGS IN THE SOFTWARE.
22	*
23	* Authors:
24	* Madhav Chauhan <madhav.chauhan@intel.com>
25	* Jani Nikula <jani.nikula@intel.com>
26	*/
27
28	#include <drm/display/drm_dsc_helper.h>
29	#include <drm/drm_atomic_helper.h>
30	#include <drm/drm_fixed.h>
31	#include <drm/drm_mipi_dsi.h>
32	#include <drm/drm_print.h>
33	#include <drm/drm_probe_helper.h>
34
35	#include "i915_reg.h"
36	#include "i915_utils.h"
37	#include "icl_dsi.h"
38	#include "icl_dsi_regs.h"
39	#include "intel_atomic.h"
40	#include "intel_backlight.h"
41	#include "intel_backlight_regs.h"
42	#include "intel_combo_phy.h"
43	#include "intel_combo_phy_regs.h"
44	#include "intel_connector.h"
45	#include "intel_crtc.h"
46	#include "intel_ddi.h"
47	#include "intel_de.h"
48	#include "intel_dsi.h"
49	#include "intel_dsi_vbt.h"
50	#include "intel_panel.h"
51	#include "intel_pfit.h"
52	#include "intel_vdsc.h"
53	#include "intel_vdsc_regs.h"
54	#include "skl_scaler.h"
55	#include "skl_universal_plane.h"
56
57	static int header_credits_available(struct intel_display *display,
58	enum transcoder dsi_trans)
59	{
60	return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
61	>> FREE_HEADER_CREDIT_SHIFT;
62	}
63
64	static int payload_credits_available(struct intel_display *display,
65	enum transcoder dsi_trans)
66	{
67	return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
68	>> FREE_PLOAD_CREDIT_SHIFT;
69	}
70
71	static bool wait_for_header_credits(struct intel_display *display,
72	enum transcoder dsi_trans, int hdr_credit)
73	{
74	if (wait_for_us(header_credits_available(display, dsi_trans) >=
75	hdr_credit, 100)) {
76	drm_err(display->drm, "DSI header credits not released\n");
77	return false;
78	}
79
80	return true;
81	}
82
83	static bool wait_for_payload_credits(struct intel_display *display,
84	enum transcoder dsi_trans, int payld_credit)
85	{
86	if (wait_for_us(payload_credits_available(display, dsi_trans) >=
87	payld_credit, 100)) {
88	drm_err(display->drm, "DSI payload credits not released\n");
89	return false;
90	}
91
92	return true;
93	}
94
95	static enum transcoder dsi_port_to_transcoder(enum port port)
96	{
97	if (port == PORT_A)
98	return TRANSCODER_DSI_0;
99	else
100	return TRANSCODER_DSI_1;
101	}
102
103	static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
104	{
105	struct intel_display *display = to_intel_display(encoder);
106	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
107	struct mipi_dsi_device *dsi;
108	enum port port;
109	enum transcoder dsi_trans;
110	int ret;
111
112	/* wait for header/payload credits to be released */
113	for_each_dsi_port(port, intel_dsi->ports) {
114	dsi_trans = dsi_port_to_transcoder(port);
115	wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
116	wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);
117	}
118
119	/* send nop DCS command */
120	for_each_dsi_port(port, intel_dsi->ports) {
121	dsi = intel_dsi->dsi_hosts[port]->device;
122	dsi->mode_flags |= MIPI_DSI_MODE_LPM;
123	dsi->channel = 0;
124	ret = mipi_dsi_dcs_nop(dsi);
125	if (ret < 0)
126	drm_err(display->drm,
127	"error sending DCS NOP command\n");
128	}
129
130	/* wait for header credits to be released */
131	for_each_dsi_port(port, intel_dsi->ports) {
132	dsi_trans = dsi_port_to_transcoder(port);
133	wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
134	}
135
136	/* wait for LP TX in progress bit to be cleared */
137	for_each_dsi_port(port, intel_dsi->ports) {
138	dsi_trans = dsi_port_to_transcoder(port);
139	if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
140	LPTX_IN_PROGRESS), 20))
141	drm_err(display->drm, "LPTX bit not cleared\n");
142	}
143	}
144
145	static int dsi_send_pkt_payld(struct intel_dsi_host *host,
146	const struct mipi_dsi_packet *packet)
147	{
148	struct intel_dsi *intel_dsi = host->intel_dsi;
149	struct intel_display *display = to_intel_display(&intel_dsi->base);
150	enum transcoder dsi_trans = dsi_port_to_transcoder(port: host->port);
151	const u8 *data = packet->payload;
152	u32 len = packet->payload_length;
153	int i, j;
154
155	/* payload queue can accept *256 bytes*, check limit */
156	if (len > MAX_PLOAD_CREDIT * 4) {
157	drm_err(display->drm, "payload size exceeds max queue limit\n");
158	return -EINVAL;
159	}
160
161	for (i = 0; i < len; i += 4) {
162	u32 tmp = 0;
163
164	if (!wait_for_payload_credits(display, dsi_trans, payld_credit: 1))
165	return -EBUSY;
166
167	for (j = 0; j < min_t(u32, len - i, 4); j++)
168	tmp |= *data++ << 8 * j;
169
170	intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), val: tmp);
171	}
172
173	return 0;
174	}
175
176	static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
177	const struct mipi_dsi_packet *packet,
178	bool enable_lpdt)
179	{
180	struct intel_dsi *intel_dsi = host->intel_dsi;
181	struct intel_display *display = to_intel_display(&intel_dsi->base);
182	enum transcoder dsi_trans = dsi_port_to_transcoder(port: host->port);
183	u32 tmp;
184
185	if (!wait_for_header_credits(display, dsi_trans, hdr_credit: 1))
186	return -EBUSY;
187
188	tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));
189
190	if (packet->payload)
191	tmp |= PAYLOAD_PRESENT;
192	else
193	tmp &= ~PAYLOAD_PRESENT;
194
195	tmp &= ~VBLANK_FENCE;
196
197	if (enable_lpdt)
198	tmp |= LP_DATA_TRANSFER;
199	else
200	tmp &= ~LP_DATA_TRANSFER;
201
202	tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
203	tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
204	tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
205	tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
206	tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
207	intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), val: tmp);
208
209	return 0;
210	}
211
212	void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
213	{
214	struct intel_display *display = to_intel_display(crtc_state);
215	u32 mode_flags;
216	enum port port;
217
218	mode_flags = crtc_state->mode_flags;
219
220	/*
221	* case 1 also covers dual link
222	* In case of dual link, frame update should be set on
223	* DSI_0
224	*/
225	if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0)
226	port = PORT_A;
227	else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
228	port = PORT_B;
229	else
230	return;
231
232	intel_de_rmw(display, DSI_CMD_FRMCTL(port), clear: 0,
233	DSI_FRAME_UPDATE_REQUEST);
234	}
235
236	static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
237	{
238	struct intel_display *display = to_intel_display(encoder);
239	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
240	enum phy phy;
241	u32 tmp, mask, val;
242	int lane;
243
244	for_each_dsi_phy(phy, intel_dsi->phys) {
245	/*
246	* Program voltage swing and pre-emphasis level values as per
247	* table in BSPEC under DDI buffer programming.
248	*/
249	mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
250	val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
251	RTERM_SELECT(0x6);
252	tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
253	tmp &= ~mask;
254	tmp |= val;
255	intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val: tmp);
256	intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), clear: mask, set: val);
257
258	mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
259	RCOMP_SCALAR_MASK;
260	val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
261	RCOMP_SCALAR(0x98);
262	tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
263	tmp &= ~mask;
264	tmp |= val;
265	intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), val: tmp);
266	intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), clear: mask, set: val);
267
268	mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
269	CURSOR_COEFF_MASK;
270	val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
271	CURSOR_COEFF(0x3f);
272	intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), clear: mask, set: val);
273
274	/* Bspec: must not use GRP register for write */
275	for (lane = 0; lane <= 3; lane++)
276	intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
277	clear: mask, set: val);
278	}
279	}
280
281	static void configure_dual_link_mode(struct intel_encoder *encoder,
282	const struct intel_crtc_state *pipe_config)
283	{
284	struct intel_display *display = to_intel_display(encoder);
285	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
286	i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
287	u32 dss_ctl1;
288
289	/* FIXME: Move all DSS handling to intel_vdsc.c */
290	if (DISPLAY_VER(display) >= 12) {
291	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
292
293	dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
294	dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
295	} else {
296	dss_ctl1_reg = DSS_CTL1;
297	dss_ctl2_reg = DSS_CTL2;
298	}
299
300	dss_ctl1 = intel_de_read(display, reg: dss_ctl1_reg);
301	dss_ctl1 |= SPLITTER_ENABLE;
302	dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
303	dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
304
305	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
306	const struct drm_display_mode *adjusted_mode =
307	&pipe_config->hw.adjusted_mode;
308	u16 hactive = adjusted_mode->crtc_hdisplay;
309	u16 dl_buffer_depth;
310
311	dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
312	dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
313
314	if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
315	drm_err(display->drm,
316	"DL buffer depth exceed max value\n");
317
318	dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
319	dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
320	intel_de_rmw(display, reg: dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
321	RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
322	} else {
323	/* Interleave */
324	dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
325	}
326
327	intel_de_write(display, reg: dss_ctl1_reg, val: dss_ctl1);
328	}
329
330	/* aka DSI 8X clock */
331	static int afe_clk(struct intel_encoder *encoder,
332	const struct intel_crtc_state *crtc_state)
333	{
334	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
335	int bpp;
336
337	if (crtc_state->dsc.compression_enable)
338	bpp = fxp_q4_to_int(val_q4: crtc_state->dsc.compressed_bpp_x16);
339	else
340	bpp = mipi_dsi_pixel_format_to_bpp(fmt: intel_dsi->pixel_format);
341
342	return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
343	}
344
345	static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
346	const struct intel_crtc_state *crtc_state)
347	{
348	struct intel_display *display = to_intel_display(encoder);
349	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
350	enum port port;
351	int afe_clk_khz;
352	int theo_word_clk, act_word_clk;
353	u32 esc_clk_div_m, esc_clk_div_m_phy;
354
355	afe_clk_khz = afe_clk(encoder, crtc_state);
356
357	if (display->platform.alderlake_s || display->platform.alderlake_p) {
358	theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
359	act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
360	esc_clk_div_m = act_word_clk * 8;
361	esc_clk_div_m_phy = (act_word_clk - 1) / 2;
362	} else {
363	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
364	}
365
366	for_each_dsi_port(port, intel_dsi->ports) {
367	intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),
368	val: esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
369	intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));
370	}
371
372	for_each_dsi_port(port, intel_dsi->ports) {
373	intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),
374	val: esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
375	intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));
376	}
377
378	if (display->platform.alderlake_s || display->platform.alderlake_p) {
379	for_each_dsi_port(port, intel_dsi->ports) {
380	intel_de_write(display, ADL_MIPIO_DW(port, 8),
381	val: esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
382	intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));
383	}
384	}
385	}
386
387	static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi)
388	{
389	struct intel_display *display = to_intel_display(&intel_dsi->base);
390	enum port port;
391
392	for_each_dsi_port(port, intel_dsi->ports) {
393	drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);
394	intel_dsi->io_wakeref[port] =
395	intel_display_power_get(display,
396	domain: port == PORT_A ?
397	POWER_DOMAIN_PORT_DDI_IO_A :
398	POWER_DOMAIN_PORT_DDI_IO_B);
399	}
400	}
401
402	static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
403	{
404	struct intel_display *display = to_intel_display(encoder);
405	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
406	enum port port;
407
408	for_each_dsi_port(port, intel_dsi->ports)
409	intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
410	clear: 0, COMBO_PHY_MODE_DSI);
411
412	get_dsi_io_power_domains(intel_dsi);
413	}
414
415	static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
416	{
417	struct intel_display *display = to_intel_display(encoder);
418	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
419	enum phy phy;
420
421	for_each_dsi_phy(phy, intel_dsi->phys)
422	intel_combo_phy_power_up_lanes(display, phy, is_dsi: true,
423	lane_count: intel_dsi->lane_count, lane_reversal: false);
424	}
425
426	static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
427	{
428	struct intel_display *display = to_intel_display(encoder);
429	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
430	enum phy phy;
431	u32 tmp;
432	int lane;
433
434	/* Step 4b(i) set loadgen select for transmit and aux lanes */
435	for_each_dsi_phy(phy, intel_dsi->phys) {
436	intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),
437	LOADGEN_SELECT, set: 0);
438	for (lane = 0; lane <= 3; lane++)
439	intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
440	LOADGEN_SELECT, set: lane != 2 ? LOADGEN_SELECT : 0);
441	}
442
443	/* Step 4b(ii) set latency optimization for transmit and aux lanes */
444	for_each_dsi_phy(phy, intel_dsi->phys) {
445	intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),
446	FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5));
447	tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
448	tmp &= ~FRC_LATENCY_OPTIM_MASK;
449	tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
450	intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), val: tmp);
451
452	/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
453	if (display->platform.jasperlake || display->platform.elkhartlake ||
454	(DISPLAY_VER(display) >= 12)) {
455	intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),
456	LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
457
458	tmp = intel_de_read(display,
459	ICL_PORT_PCS_DW1_LN(0, phy));
460	tmp &= ~LATENCY_OPTIM_MASK;
461	tmp |= LATENCY_OPTIM_VAL(0x1);
462	intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),
463	val: tmp);
464	}
465	}
466
467	}
468
469	static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
470	{
471	struct intel_display *display = to_intel_display(encoder);
472	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
473	u32 tmp;
474	enum phy phy;
475
476	/* clear common keeper enable bit */
477	for_each_dsi_phy(phy, intel_dsi->phys) {
478	tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
479	tmp &= ~COMMON_KEEPER_EN;
480	intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val: tmp);
481	intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, set: 0);
482	}
483
484	/*
485	* Set SUS Clock Config bitfield to 11b
486	* Note: loadgen select program is done
487	* as part of lane phy sequence configuration
488	*/
489	for_each_dsi_phy(phy, intel_dsi->phys)
490	intel_de_rmw(display, ICL_PORT_CL_DW5(phy), clear: 0,
491	SUS_CLOCK_CONFIG);
492
493	/* Clear training enable to change swing values */
494	for_each_dsi_phy(phy, intel_dsi->phys) {
495	tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
496	tmp &= ~TX_TRAINING_EN;
497	intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val: tmp);
498	intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, set: 0);
499	}
500
501	/* Program swing and de-emphasis */
502	dsi_program_swing_and_deemphasis(encoder);
503
504	/* Set training enable to trigger update */
505	for_each_dsi_phy(phy, intel_dsi->phys) {
506	tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
507	tmp |= TX_TRAINING_EN;
508	intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val: tmp);
509	intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), clear: 0, TX_TRAINING_EN);
510	}
511	}
512
513	static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
514	{
515	struct intel_display *display = to_intel_display(encoder);
516	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
517	enum port port;
518
519	for_each_dsi_port(port, intel_dsi->ports) {
520	intel_de_rmw(display, DDI_BUF_CTL(port), clear: 0, DDI_BUF_CTL_ENABLE);
521
522	if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) &
523	DDI_BUF_IS_IDLE),
524	500))
525	drm_err(display->drm, "DDI port:%c buffer idle\n",
526	port_name(port));
527	}
528	}
529
530	static void
531	gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
532	const struct intel_crtc_state *crtc_state)
533	{
534	struct intel_display *display = to_intel_display(encoder);
535	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
536	enum port port;
537	enum phy phy;
538
539	/* Program DPHY clock lanes timings */
540	for_each_dsi_port(port, intel_dsi->ports)
541	intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),
542	val: intel_dsi->dphy_reg);
543
544	/* Program DPHY data lanes timings */
545	for_each_dsi_port(port, intel_dsi->ports)
546	intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),
547	val: intel_dsi->dphy_data_lane_reg);
548
549	/*
550	* If DSI link operating at or below an 800 MHz,
551	* TA_SURE should be override and programmed to
552	* a value '0' inside TA_PARAM_REGISTERS otherwise
553	* leave all fields at HW default values.
554	*/
555	if (DISPLAY_VER(display) == 11) {
556	if (afe_clk(encoder, crtc_state) <= 800000) {
557	for_each_dsi_port(port, intel_dsi->ports)
558	intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),
559	TA_SURE_MASK,
560	TA_SURE_OVERRIDE | TA_SURE(0));
561	}
562	}
563
564	if (display->platform.jasperlake || display->platform.elkhartlake) {
565	for_each_dsi_phy(phy, intel_dsi->phys)
566	intel_de_rmw(display, ICL_DPHY_CHKN(phy),
567	clear: 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
568	}
569	}
570
571	static void
572	gen11_dsi_setup_timings(struct intel_encoder *encoder,
573	const struct intel_crtc_state *crtc_state)
574	{
575	struct intel_display *display = to_intel_display(encoder);
576	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
577	enum port port;
578
579	/* Program T-INIT master registers */
580	for_each_dsi_port(port, intel_dsi->ports)
581	intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),
582	DSI_T_INIT_MASTER_MASK, set: intel_dsi->init_count);
583
584	/* shadow register inside display core */
585	for_each_dsi_port(port, intel_dsi->ports)
586	intel_de_write(display, DSI_CLK_TIMING_PARAM(port),
587	val: intel_dsi->dphy_reg);
588
589	/* shadow register inside display core */
590	for_each_dsi_port(port, intel_dsi->ports)
591	intel_de_write(display, DSI_DATA_TIMING_PARAM(port),
592	val: intel_dsi->dphy_data_lane_reg);
593
594	/* shadow register inside display core */
595	if (DISPLAY_VER(display) == 11) {
596	if (afe_clk(encoder, crtc_state) <= 800000) {
597	for_each_dsi_port(port, intel_dsi->ports) {
598	intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),
599	TA_SURE_MASK,
600	TA_SURE_OVERRIDE | TA_SURE(0));
601	}
602	}
603	}
604	}
605
606	static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
607	{
608	struct intel_display *display = to_intel_display(encoder);
609	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
610	u32 tmp;
611	enum phy phy;
612
613	mutex_lock(&display->dpll.lock);
614	tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
615	for_each_dsi_phy(phy, intel_dsi->phys)
616	tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
617
618	intel_de_write(display, ICL_DPCLKA_CFGCR0, val: tmp);
619	mutex_unlock(lock: &display->dpll.lock);
620	}
621
622	static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
623	{
624	struct intel_display *display = to_intel_display(encoder);
625	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
626	u32 tmp;
627	enum phy phy;
628
629	mutex_lock(&display->dpll.lock);
630	tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
631	for_each_dsi_phy(phy, intel_dsi->phys)
632	tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
633
634	intel_de_write(display, ICL_DPCLKA_CFGCR0, val: tmp);
635	mutex_unlock(lock: &display->dpll.lock);
636	}
637
638	static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
639	{
640	struct intel_display *display = to_intel_display(encoder);
641	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
642	bool clock_enabled = false;
643	enum phy phy;
644	u32 tmp;
645
646	tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
647
648	for_each_dsi_phy(phy, intel_dsi->phys) {
649	if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
650	clock_enabled = true;
651	}
652
653	return clock_enabled;
654	}
655
656	static void gen11_dsi_map_pll(struct intel_encoder *encoder,
657	const struct intel_crtc_state *crtc_state)
658	{
659	struct intel_display *display = to_intel_display(encoder);
660	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
661	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
662	enum phy phy;
663	u32 val;
664
665	mutex_lock(&display->dpll.lock);
666
667	val = intel_de_read(display, ICL_DPCLKA_CFGCR0);
668	for_each_dsi_phy(phy, intel_dsi->phys) {
669	val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
670	val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
671	}
672	intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
673
674	for_each_dsi_phy(phy, intel_dsi->phys) {
675	val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
676	}
677	intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
678
679	intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);
680
681	mutex_unlock(lock: &display->dpll.lock);
682	}
683
684	static void
685	gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
686	const struct intel_crtc_state *pipe_config)
687	{
688	struct intel_display *display = to_intel_display(encoder);
689	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
690	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
691	enum pipe pipe = crtc->pipe;
692	u32 tmp;
693	enum port port;
694	enum transcoder dsi_trans;
695
696	for_each_dsi_port(port, intel_dsi->ports) {
697	dsi_trans = dsi_port_to_transcoder(port);
698	tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
699
700	if (intel_dsi->eotp_pkt)
701	tmp &= ~EOTP_DISABLED;
702	else
703	tmp |= EOTP_DISABLED;
704
705	/* enable link calibration if freq > 1.5Gbps */
706	if (afe_clk(encoder, crtc_state: pipe_config) >= 1500 * 1000) {
707	tmp &= ~LINK_CALIBRATION_MASK;
708	tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
709	}
710
711	/* configure continuous clock */
712	tmp &= ~CONTINUOUS_CLK_MASK;
713	if (intel_dsi->clock_stop)
714	tmp |= CLK_ENTER_LP_AFTER_DATA;
715	else
716	tmp |= CLK_HS_CONTINUOUS;
717
718	/* configure buffer threshold limit to minimum */
719	tmp &= ~PIX_BUF_THRESHOLD_MASK;
720	tmp |= PIX_BUF_THRESHOLD_1_4;
721
722	/* set virtual channel to '0' */
723	tmp &= ~PIX_VIRT_CHAN_MASK;
724	tmp |= PIX_VIRT_CHAN(0);
725
726	/* program BGR transmission */
727	if (intel_dsi->bgr_enabled)
728	tmp |= BGR_TRANSMISSION;
729
730	/* select pixel format */
731	tmp &= ~PIX_FMT_MASK;
732	if (pipe_config->dsc.compression_enable) {
733	tmp |= PIX_FMT_COMPRESSED;
734	} else {
735	switch (intel_dsi->pixel_format) {
736	default:
737	MISSING_CASE(intel_dsi->pixel_format);
738	fallthrough;
739	case MIPI_DSI_FMT_RGB565:
740	tmp |= PIX_FMT_RGB565;
741	break;
742	case MIPI_DSI_FMT_RGB666_PACKED:
743	tmp |= PIX_FMT_RGB666_PACKED;
744	break;
745	case MIPI_DSI_FMT_RGB666:
746	tmp |= PIX_FMT_RGB666_LOOSE;
747	break;
748	case MIPI_DSI_FMT_RGB888:
749	tmp |= PIX_FMT_RGB888;
750	break;
751	}
752	}
753
754	if (DISPLAY_VER(display) >= 12) {
755	if (is_vid_mode(intel_dsi))
756	tmp |= BLANKING_PACKET_ENABLE;
757	}
758
759	/* program DSI operation mode */
760	if (is_vid_mode(intel_dsi)) {
761	tmp &= ~OP_MODE_MASK;
762	switch (intel_dsi->video_mode) {
763	default:
764	MISSING_CASE(intel_dsi->video_mode);
765	fallthrough;
766	case NON_BURST_SYNC_EVENTS:
767	tmp |= VIDEO_MODE_SYNC_EVENT;
768	break;
769	case NON_BURST_SYNC_PULSE:
770	tmp |= VIDEO_MODE_SYNC_PULSE;
771	break;
772	}
773	} else {
774	/*
775	* FIXME: Retrieve this info from VBT.
776	* As per the spec when dsi transcoder is operating
777	* in TE GATE mode, TE comes from GPIO
778	* which is UTIL PIN for DSI 0.
779	* Also this GPIO would not be used for other
780	* purposes is an assumption.
781	*/
782	tmp &= ~OP_MODE_MASK;
783	tmp |= CMD_MODE_TE_GATE;
784	tmp |= TE_SOURCE_GPIO;
785	}
786
787	intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), val: tmp);
788	}
789
790	/* enable port sync mode if dual link */
791	if (intel_dsi->dual_link) {
792	for_each_dsi_port(port, intel_dsi->ports) {
793	dsi_trans = dsi_port_to_transcoder(port);
794	intel_de_rmw(display,
795	TRANS_DDI_FUNC_CTL2(display, dsi_trans),
796	clear: 0, PORT_SYNC_MODE_ENABLE);
797	}
798
799	/* configure stream splitting */
800	configure_dual_link_mode(encoder, pipe_config);
801	}
802
803	for_each_dsi_port(port, intel_dsi->ports) {
804	dsi_trans = dsi_port_to_transcoder(port);
805
806	/* select data lane width */
807	tmp = intel_de_read(display,
808	TRANS_DDI_FUNC_CTL(display, dsi_trans));
809	tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
810	tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
811
812	/* select input pipe */
813	tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
814	switch (pipe) {
815	default:
816	MISSING_CASE(pipe);
817	fallthrough;
818	case PIPE_A:
819	tmp |= TRANS_DDI_EDP_INPUT_A_ON;
820	break;
821	case PIPE_B:
822	tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
823	break;
824	case PIPE_C:
825	tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
826	break;
827	case PIPE_D:
828	tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
829	break;
830	}
831
832	/* enable DDI buffer */
833	tmp |= TRANS_DDI_FUNC_ENABLE;
834	intel_de_write(display,
835	TRANS_DDI_FUNC_CTL(display, dsi_trans), val: tmp);
836	}
837
838	/* wait for link ready */
839	for_each_dsi_port(port, intel_dsi->ports) {
840	dsi_trans = dsi_port_to_transcoder(port);
841	if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) &
842	LINK_READY), 2500))
843	drm_err(display->drm, "DSI link not ready\n");
844	}
845	}
846
847	static void
848	gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
849	const struct intel_crtc_state *crtc_state)
850	{
851	struct intel_display *display = to_intel_display(encoder);
852	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
853	const struct drm_display_mode *adjusted_mode =
854	&crtc_state->hw.adjusted_mode;
855	enum port port;
856	enum transcoder dsi_trans;
857	/* horizontal timings */
858	u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
859	u16 hback_porch;
860	/* vertical timings */
861	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
862	int mul = 1, div = 1;
863
864	/*
865	* Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
866	* for slower link speed if DSC is enabled.
867	*
868	* The compression frequency ratio is the ratio between compressed and
869	* non-compressed link speeds, and simplifies down to the ratio between
870	* compressed and non-compressed bpp.
871	*/
872	if (crtc_state->dsc.compression_enable) {
873	mul = fxp_q4_to_int(val_q4: crtc_state->dsc.compressed_bpp_x16);
874	div = mipi_dsi_pixel_format_to_bpp(fmt: intel_dsi->pixel_format);
875	}
876
877	hactive = adjusted_mode->crtc_hdisplay;
878
879	if (is_vid_mode(intel_dsi))
880	htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
881	else
882	htotal = DIV_ROUND_UP((hactive + 160) * mul, div);
883
884	hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
885	hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
886	hsync_size = hsync_end - hsync_start;
887	hback_porch = (adjusted_mode->crtc_htotal -
888	adjusted_mode->crtc_hsync_end);
889	vactive = adjusted_mode->crtc_vdisplay;
890
891	if (is_vid_mode(intel_dsi)) {
892	vtotal = adjusted_mode->crtc_vtotal;
893	} else {
894	int bpp, line_time_us, byte_clk_period_ns;
895
896	if (crtc_state->dsc.compression_enable)
897	bpp = fxp_q4_to_int(val_q4: crtc_state->dsc.compressed_bpp_x16);
898	else
899	bpp = mipi_dsi_pixel_format_to_bpp(fmt: intel_dsi->pixel_format);
900
901	byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
902	line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
903	vtotal = vactive + DIV_ROUND_UP(400, line_time_us);
904	}
905	vsync_start = adjusted_mode->crtc_vsync_start;
906	vsync_end = adjusted_mode->crtc_vsync_end;
907	vsync_shift = hsync_start - htotal / 2;
908
909	if (intel_dsi->dual_link) {
910	hactive /= 2;
911	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
912	hactive += intel_dsi->pixel_overlap;
913	htotal /= 2;
914	}
915
916	/* minimum hactive as per bspec: 256 pixels */
917	if (adjusted_mode->crtc_hdisplay < 256)
918	drm_err(display->drm, "hactive is less then 256 pixels\n");
919
920	/* if RGB666 format, then hactive must be multiple of 4 pixels */
921	if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
922	drm_err(display->drm,
923	"hactive pixels are not multiple of 4\n");
924
925	/* program TRANS_HTOTAL register */
926	for_each_dsi_port(port, intel_dsi->ports) {
927	dsi_trans = dsi_port_to_transcoder(port);
928	intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),
929	HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
930	}
931
932	/* TRANS_HSYNC register to be programmed only for video mode */
933	if (is_vid_mode(intel_dsi)) {
934	if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
935	/* BSPEC: hsync size should be atleast 16 pixels */
936	if (hsync_size < 16)
937	drm_err(display->drm,
938	"hsync size < 16 pixels\n");
939	}
940
941	if (hback_porch < 16)
942	drm_err(display->drm, "hback porch < 16 pixels\n");
943
944	if (intel_dsi->dual_link) {
945	hsync_start /= 2;
946	hsync_end /= 2;
947	}
948
949	for_each_dsi_port(port, intel_dsi->ports) {
950	dsi_trans = dsi_port_to_transcoder(port);
951	intel_de_write(display,
952	TRANS_HSYNC(display, dsi_trans),
953	HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
954	}
955	}
956
957	/* program TRANS_VTOTAL register */
958	for_each_dsi_port(port, intel_dsi->ports) {
959	dsi_trans = dsi_port_to_transcoder(port);
960	/*
961	* FIXME: Programming this by assuming progressive mode, since
962	* non-interlaced info from VBT is not saved inside
963	* struct drm_display_mode.
964	* For interlace mode: program required pixel minus 2
965	*/
966	intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),
967	VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
968	}
969
970	if (vsync_end < vsync_start || vsync_end > vtotal)
971	drm_err(display->drm, "Invalid vsync_end value\n");
972
973	if (vsync_start < vactive)
974	drm_err(display->drm, "vsync_start less than vactive\n");
975
976	/* program TRANS_VSYNC register for video mode only */
977	if (is_vid_mode(intel_dsi)) {
978	for_each_dsi_port(port, intel_dsi->ports) {
979	dsi_trans = dsi_port_to_transcoder(port);
980	intel_de_write(display,
981	TRANS_VSYNC(display, dsi_trans),
982	VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
983	}
984	}
985
986	/*
987	* FIXME: It has to be programmed only for video modes and interlaced
988	* modes. Put the check condition here once interlaced
989	* info available as described above.
990	* program TRANS_VSYNCSHIFT register
991	*/
992	if (is_vid_mode(intel_dsi)) {
993	for_each_dsi_port(port, intel_dsi->ports) {
994	dsi_trans = dsi_port_to_transcoder(port);
995	intel_de_write(display,
996	TRANS_VSYNCSHIFT(display, dsi_trans),
997	val: vsync_shift);
998	}
999	}
1000
1001	/*
1002	* program TRANS_VBLANK register, should be same as vtotal programmed
1003	*
1004	* FIXME get rid of these local hacks and do it right,
1005	* this will not handle eg. delayed vblank correctly.
1006	*/
1007	if (DISPLAY_VER(display) >= 12) {
1008	for_each_dsi_port(port, intel_dsi->ports) {
1009	dsi_trans = dsi_port_to_transcoder(port);
1010	intel_de_write(display,
1011	TRANS_VBLANK(display, dsi_trans),
1012	VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
1013	}
1014	}
1015	}
1016
1017	static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
1018	{
1019	struct intel_display *display = to_intel_display(encoder);
1020	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1021	enum port port;
1022	enum transcoder dsi_trans;
1023
1024	for_each_dsi_port(port, intel_dsi->ports) {
1025	dsi_trans = dsi_port_to_transcoder(port);
1026	intel_de_rmw(display, TRANSCONF(display, dsi_trans), clear: 0,
1027	TRANSCONF_ENABLE);
1028
1029	/* wait for transcoder to be enabled */
1030	if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),
1031	TRANSCONF_STATE_ENABLE, timeout: 10))
1032	drm_err(display->drm,
1033	"DSI transcoder not enabled\n");
1034	}
1035	}
1036
1037	static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1038	const struct intel_crtc_state *crtc_state)
1039	{
1040	struct intel_display *display = to_intel_display(encoder);
1041	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1042	enum port port;
1043	enum transcoder dsi_trans;
1044	u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
1045
1046	/*
1047	* escape clock count calculation:
1048	* BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1049	* UI (nsec) = (10^6)/Bitrate
1050	* TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1051	* ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS
1052	*/
1053	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
1054	mul = 8 * 1000000;
1055	hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1056	divisor);
1057	lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1058	ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1059
1060	for_each_dsi_port(port, intel_dsi->ports) {
1061	dsi_trans = dsi_port_to_transcoder(port);
1062
1063	/* program hst_tx_timeout */
1064	intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),
1065	HSTX_TIMEOUT_VALUE_MASK,
1066	HSTX_TIMEOUT_VALUE(hs_tx_timeout));
1067
1068	/* FIXME: DSI_CALIB_TO */
1069
1070	/* program lp_rx_host timeout */
1071	intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),
1072	LPRX_TIMEOUT_VALUE_MASK,
1073	LPRX_TIMEOUT_VALUE(lp_rx_timeout));
1074
1075	/* FIXME: DSI_PWAIT_TO */
1076
1077	/* program turn around timeout */
1078	intel_de_rmw(display, DSI_TA_TO(dsi_trans),
1079	TA_TIMEOUT_VALUE_MASK,
1080	TA_TIMEOUT_VALUE(ta_timeout));
1081	}
1082	}
1083
1084	static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1085	bool enable)
1086	{
1087	struct intel_display *display = to_intel_display(encoder);
1088	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1089	u32 tmp;
1090
1091	/*
1092	* used as TE i/p for DSI0,
1093	* for dual link/DSI1 TE is from slave DSI1
1094	* through GPIO.
1095	*/
1096	if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1097	return;
1098
1099	tmp = intel_de_read(display, UTIL_PIN_CTL);
1100
1101	if (enable) {
1102	tmp |= UTIL_PIN_DIRECTION_INPUT;
1103	tmp |= UTIL_PIN_ENABLE;
1104	} else {
1105	tmp &= ~UTIL_PIN_ENABLE;
1106	}
1107	intel_de_write(display, UTIL_PIN_CTL, val: tmp);
1108	}
1109
1110	static void
1111	gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1112	const struct intel_crtc_state *crtc_state)
1113	{
1114	/* step 4a: power up all lanes of the DDI used by DSI */
1115	gen11_dsi_power_up_lanes(encoder);
1116
1117	/* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1118	gen11_dsi_config_phy_lanes_sequence(encoder);
1119
1120	/* step 4c: configure voltage swing and skew */
1121	gen11_dsi_voltage_swing_program_seq(encoder);
1122
1123	/* setup D-PHY timings */
1124	gen11_dsi_setup_dphy_timings(encoder, crtc_state);
1125
1126	/* enable DDI buffer */
1127	gen11_dsi_enable_ddi_buffer(encoder);
1128
1129	gen11_dsi_gate_clocks(encoder);
1130
1131	gen11_dsi_setup_timings(encoder, crtc_state);
1132
1133	/* Since transcoder is configured to take events from GPIO */
1134	gen11_dsi_config_util_pin(encoder, enable: true);
1135
1136	/* step 4h: setup DSI protocol timeouts */
1137	gen11_dsi_setup_timeouts(encoder, crtc_state);
1138
1139	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
1140	gen11_dsi_configure_transcoder(encoder, pipe_config: crtc_state);
1141	}
1142
1143	static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1144	{
1145	struct intel_display *display = to_intel_display(encoder);
1146	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1147	struct mipi_dsi_device *dsi;
1148	enum port port;
1149	enum transcoder dsi_trans;
1150	u32 tmp;
1151	int ret;
1152
1153	/* set maximum return packet size */
1154	for_each_dsi_port(port, intel_dsi->ports) {
1155	dsi_trans = dsi_port_to_transcoder(port);
1156
1157	/*
1158	* FIXME: This uses the number of DW's currently in the payload
1159	* receive queue. This is probably not what we want here.
1160	*/
1161	tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));
1162	tmp &= NUMBER_RX_PLOAD_DW_MASK;
1163	/* multiply "Number Rx Payload DW" by 4 to get max value */
1164	tmp = tmp * 4;
1165	dsi = intel_dsi->dsi_hosts[port]->device;
1166	ret = mipi_dsi_set_maximum_return_packet_size(dsi, value: tmp);
1167	if (ret < 0)
1168	drm_err(display->drm,
1169	"error setting max return pkt size%d\n", tmp);
1170	}
1171
1172	intel_dsi_vbt_exec_sequence(intel_dsi, seq_id: MIPI_SEQ_INIT_OTP);
1173
1174	/* ensure all panel commands dispatched before enabling transcoder */
1175	wait_for_cmds_dispatched_to_panel(encoder);
1176	}
1177
1178	static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state,
1179	struct intel_encoder *encoder,
1180	const struct intel_crtc_state *crtc_state,
1181	const struct drm_connector_state *conn_state)
1182	{
1183	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1184
1185	intel_dsi_wait_panel_power_cycle(intel_dsi);
1186
1187	intel_dsi_vbt_exec_sequence(intel_dsi, seq_id: MIPI_SEQ_POWER_ON);
1188	msleep(msecs: intel_dsi->panel_on_delay);
1189	intel_dsi_vbt_exec_sequence(intel_dsi, seq_id: MIPI_SEQ_DEASSERT_RESET);
1190
1191	/* step2: enable IO power */
1192	gen11_dsi_enable_io_power(encoder);
1193
1194	/* step3: enable DSI PLL */
1195	gen11_dsi_program_esc_clk_div(encoder, crtc_state);
1196	}
1197
1198	static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
1199	struct intel_encoder *encoder,
1200	const struct intel_crtc_state *pipe_config,
1201	const struct drm_connector_state *conn_state)
1202	{
1203	/* step3b */
1204	gen11_dsi_map_pll(encoder, crtc_state: pipe_config);
1205
1206	/* step4: enable DSI port and DPHY */
1207	gen11_dsi_enable_port_and_phy(encoder, crtc_state: pipe_config);
1208
1209	/* step5: program and powerup panel */
1210	gen11_dsi_powerup_panel(encoder);
1211
1212	intel_dsc_dsi_pps_write(encoder, crtc_state: pipe_config);
1213
1214	/* step6c: configure transcoder timings */
1215	gen11_dsi_set_transcoder_timings(encoder, crtc_state: pipe_config);
1216	}
1217
1218	/*
1219	* Wa_1409054076:icl,jsl,ehl
1220	* When pipe A is disabled and MIPI DSI is enabled on pipe B,
1221	* the AMT KVMR feature will incorrectly see pipe A as enabled.
1222	* Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
1223	* it set while DSI is enabled on pipe B
1224	*/
1225	static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
1226	enum pipe pipe, bool enable)
1227	{
1228	struct intel_display *display = to_intel_display(encoder);
1229
1230	if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)
1231	intel_de_rmw(display, CHICKEN_PAR1_1,
1232	IGNORE_KVMR_PIPE_A,
1233	set: enable ? IGNORE_KVMR_PIPE_A : 0);
1234	}
1235
1236	/*
1237	* Wa_16012360555:adl-p
1238	* SW will have to program the "LP to HS Wakeup Guardband"
1239	* to account for the repeaters on the HS Request/Ready
1240	* PPI signaling between the Display engine and the DPHY.
1241	*/
1242	static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
1243	{
1244	struct intel_display *display = to_intel_display(encoder);
1245	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1246	enum port port;
1247
1248	if (DISPLAY_VER(display) == 13) {
1249	for_each_dsi_port(port, intel_dsi->ports)
1250	intel_de_rmw(display, TGL_DSI_CHKN_REG(port),
1251	TGL_DSI_CHKN_LSHS_GB_MASK,
1252	TGL_DSI_CHKN_LSHS_GB(4));
1253	}
1254	}
1255
1256	static void gen11_dsi_enable(struct intel_atomic_state *state,
1257	struct intel_encoder *encoder,
1258	const struct intel_crtc_state *crtc_state,
1259	const struct drm_connector_state *conn_state)
1260	{
1261	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1262	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1263
1264	/* Wa_1409054076:icl,jsl,ehl */
1265	icl_apply_kvmr_pipe_a_wa(encoder, pipe: crtc->pipe, enable: true);
1266
1267	/* Wa_16012360555:adl-p */
1268	adlp_set_lp_hs_wakeup_gb(encoder);
1269
1270	/* step6d: enable dsi transcoder */
1271	gen11_dsi_enable_transcoder(encoder);
1272
1273	intel_dsi_vbt_exec_sequence(intel_dsi, seq_id: MIPI_SEQ_DISPLAY_ON);
1274
1275	/* step7: enable backlight */
1276	intel_backlight_enable(crtc_state, conn_state);
1277	intel_dsi_vbt_exec_sequence(intel_dsi, seq_id: MIPI_SEQ_BACKLIGHT_ON);
1278
1279	intel_crtc_vblank_on(crtc_state);
1280	}
1281
1282	static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1283	{
1284	struct intel_display *display = to_intel_display(encoder);
1285	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1286	enum port port;
1287	enum transcoder dsi_trans;
1288
1289	for_each_dsi_port(port, intel_dsi->ports) {
1290	dsi_trans = dsi_port_to_transcoder(port);
1291
1292	/* disable transcoder */
1293	intel_de_rmw(display, TRANSCONF(display, dsi_trans),
1294	TRANSCONF_ENABLE, set: 0);
1295
1296	/* wait for transcoder to be disabled */
1297	if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),
1298	TRANSCONF_STATE_ENABLE, timeout: 50))
1299	drm_err(display->drm,
1300	"DSI trancoder not disabled\n");
1301	}
1302	}
1303
1304	static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1305	{
1306	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1307
1308	intel_dsi_vbt_exec_sequence(intel_dsi, seq_id: MIPI_SEQ_DISPLAY_OFF);
1309
1310	/* ensure cmds dispatched to panel */
1311	wait_for_cmds_dispatched_to_panel(encoder);
1312	}
1313
1314	static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1315	{
1316	struct intel_display *display = to_intel_display(encoder);
1317	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1318	enum port port;
1319	enum transcoder dsi_trans;
1320	u32 tmp;
1321
1322	/* disable periodic update mode */
1323	if (is_cmd_mode(intel_dsi)) {
1324	for_each_dsi_port(port, intel_dsi->ports)
1325	intel_de_rmw(display, DSI_CMD_FRMCTL(port),
1326	DSI_PERIODIC_FRAME_UPDATE_ENABLE, set: 0);
1327	}
1328
1329	/* put dsi link in ULPS */
1330	for_each_dsi_port(port, intel_dsi->ports) {
1331	dsi_trans = dsi_port_to_transcoder(port);
1332	tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));
1333	tmp |= LINK_ENTER_ULPS;
1334	tmp &= ~LINK_ULPS_TYPE_LP11;
1335	intel_de_write(display, DSI_LP_MSG(dsi_trans), val: tmp);
1336
1337	if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
1338	LINK_IN_ULPS),
1339	10))
1340	drm_err(display->drm, "DSI link not in ULPS\n");
1341	}
1342
1343	/* disable ddi function */
1344	for_each_dsi_port(port, intel_dsi->ports) {
1345	dsi_trans = dsi_port_to_transcoder(port);
1346	intel_de_rmw(display,
1347	TRANS_DDI_FUNC_CTL(display, dsi_trans),
1348	TRANS_DDI_FUNC_ENABLE, set: 0);
1349	}
1350
1351	/* disable port sync mode if dual link */
1352	if (intel_dsi->dual_link) {
1353	for_each_dsi_port(port, intel_dsi->ports) {
1354	dsi_trans = dsi_port_to_transcoder(port);
1355	intel_de_rmw(display,
1356	TRANS_DDI_FUNC_CTL2(display, dsi_trans),
1357	PORT_SYNC_MODE_ENABLE, set: 0);
1358	}
1359	}
1360	}
1361
1362	static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1363	{
1364	struct intel_display *display = to_intel_display(encoder);
1365	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1366	enum port port;
1367
1368	gen11_dsi_ungate_clocks(encoder);
1369	for_each_dsi_port(port, intel_dsi->ports) {
1370	intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, set: 0);
1371
1372	if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) &
1373	DDI_BUF_IS_IDLE),
1374	8))
1375	drm_err(display->drm,
1376	"DDI port:%c buffer not idle\n",
1377	port_name(port));
1378	}
1379	gen11_dsi_gate_clocks(encoder);
1380	}
1381
1382	static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1383	{
1384	struct intel_display *display = to_intel_display(encoder);
1385	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1386	enum port port;
1387
1388	for_each_dsi_port(port, intel_dsi->ports) {
1389	intel_wakeref_t wakeref;
1390
1391	wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1392	intel_display_power_put(display,
1393	domain: port == PORT_A ?
1394	POWER_DOMAIN_PORT_DDI_IO_A :
1395	POWER_DOMAIN_PORT_DDI_IO_B,
1396	wakeref);
1397	}
1398
1399	/* set mode to DDI */
1400	for_each_dsi_port(port, intel_dsi->ports)
1401	intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
1402	COMBO_PHY_MODE_DSI, set: 0);
1403	}
1404
1405	static void gen11_dsi_disable(struct intel_atomic_state *state,
1406	struct intel_encoder *encoder,
1407	const struct intel_crtc_state *old_crtc_state,
1408	const struct drm_connector_state *old_conn_state)
1409	{
1410	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1411
1412	/* step1: turn off backlight */
1413	intel_dsi_vbt_exec_sequence(intel_dsi, seq_id: MIPI_SEQ_BACKLIGHT_OFF);
1414	intel_backlight_disable(old_conn_state);
1415	}
1416
1417	static void gen11_dsi_post_disable(struct intel_atomic_state *state,
1418	struct intel_encoder *encoder,
1419	const struct intel_crtc_state *old_crtc_state,
1420	const struct drm_connector_state *old_conn_state)
1421	{
1422	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1423	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1424
1425	intel_crtc_vblank_off(crtc_state: old_crtc_state);
1426
1427	/* step2d,e: disable transcoder and wait */
1428	gen11_dsi_disable_transcoder(encoder);
1429
1430	/* Wa_1409054076:icl,jsl,ehl */
1431	icl_apply_kvmr_pipe_a_wa(encoder, pipe: crtc->pipe, enable: false);
1432
1433	/* step2f,g: powerdown panel */
1434	gen11_dsi_powerdown_panel(encoder);
1435
1436	/* step2h,i,j: deconfig trancoder */
1437	gen11_dsi_deconfigure_trancoder(encoder);
1438
1439	intel_dsc_disable(crtc_state: old_crtc_state);
1440	skl_scaler_disable(old_crtc_state);
1441
1442	/* step3: disable port */
1443	gen11_dsi_disable_port(encoder);
1444
1445	gen11_dsi_config_util_pin(encoder, enable: false);
1446
1447	/* step4: disable IO power */
1448	gen11_dsi_disable_io_power(encoder);
1449
1450	intel_dsi_vbt_exec_sequence(intel_dsi, seq_id: MIPI_SEQ_ASSERT_RESET);
1451
1452	msleep(msecs: intel_dsi->panel_off_delay);
1453	intel_dsi_vbt_exec_sequence(intel_dsi, seq_id: MIPI_SEQ_POWER_OFF);
1454
1455	intel_dsi->panel_power_off_time = ktime_get_boottime();
1456	}
1457
1458	static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1459	const struct drm_display_mode *mode)
1460	{
1461	struct intel_display *display = to_intel_display(connector->dev);
1462	enum drm_mode_status status;
1463
1464	status = intel_cpu_transcoder_mode_valid(display, mode);
1465	if (status != MODE_OK)
1466	return status;
1467
1468	/* FIXME: DSC? */
1469	return intel_dsi_mode_valid(connector, mode);
1470	}
1471
1472	static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1473	struct intel_crtc_state *pipe_config)
1474	{
1475	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1476	struct drm_display_mode *adjusted_mode =
1477	&pipe_config->hw.adjusted_mode;
1478
1479	if (pipe_config->dsc.compressed_bpp_x16) {
1480	int div = fxp_q4_to_int(val_q4: pipe_config->dsc.compressed_bpp_x16);
1481	int mul = mipi_dsi_pixel_format_to_bpp(fmt: intel_dsi->pixel_format);
1482
1483	adjusted_mode->crtc_htotal =
1484	DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1485	adjusted_mode->crtc_hsync_start =
1486	DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1487	adjusted_mode->crtc_hsync_end =
1488	DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1489	}
1490
1491	if (intel_dsi->dual_link) {
1492	adjusted_mode->crtc_hdisplay *= 2;
1493	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1494	adjusted_mode->crtc_hdisplay -=
1495	intel_dsi->pixel_overlap;
1496	adjusted_mode->crtc_htotal *= 2;
1497	}
1498	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1499	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1500
1501	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1502	if (intel_dsi->dual_link) {
1503	adjusted_mode->crtc_hsync_start *= 2;
1504	adjusted_mode->crtc_hsync_end *= 2;
1505	}
1506	}
1507	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1508	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1509	}
1510
1511	static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1512	{
1513	struct intel_display *display = to_intel_display(&intel_dsi->base);
1514	enum transcoder dsi_trans;
1515	u32 val;
1516
1517	if (intel_dsi->ports == BIT(PORT_B))
1518	dsi_trans = TRANSCODER_DSI_1;
1519	else
1520	dsi_trans = TRANSCODER_DSI_0;
1521
1522	val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
1523	return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1524	}
1525
1526	static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
1527	struct intel_crtc_state *pipe_config)
1528	{
1529	if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1530	pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
1531	I915_MODE_FLAG_DSI_USE_TE0;
1532	else if (intel_dsi->ports == BIT(PORT_B))
1533	pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
1534	else
1535	pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
1536	}
1537
1538	static void gen11_dsi_get_config(struct intel_encoder *encoder,
1539	struct intel_crtc_state *pipe_config)
1540	{
1541	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1542	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1543
1544	intel_ddi_get_clock(encoder, crtc_state: pipe_config, pll: icl_ddi_combo_get_pll(encoder));
1545
1546	pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1547	if (intel_dsi->dual_link)
1548	pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1549
1550	gen11_dsi_get_timings(encoder, pipe_config);
1551	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1552	pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1553
1554	/* Get the details on which TE should be enabled */
1555	if (is_cmd_mode(intel_dsi))
1556	gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1557
1558	if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
1559	pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1560	}
1561
1562	static void gen11_dsi_sync_state(struct intel_encoder *encoder,
1563	const struct intel_crtc_state *crtc_state)
1564	{
1565	struct intel_display *display = to_intel_display(encoder);
1566	struct intel_crtc *intel_crtc;
1567	enum pipe pipe;
1568
1569	if (!crtc_state)
1570	return;
1571
1572	intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1573	pipe = intel_crtc->pipe;
1574
1575	/* wa verify 1409054076:icl,jsl,ehl */
1576	if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&
1577	!(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1578	drm_dbg_kms(display->drm,
1579	"[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
1580	encoder->base.base.id,
1581	encoder->base.name);
1582	}
1583
1584	static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1585	struct intel_crtc_state *crtc_state)
1586	{
1587	struct intel_display *display = to_intel_display(encoder);
1588	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1589	int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;
1590	bool use_dsc;
1591	int ret;
1592
1593	use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
1594	if (!use_dsc)
1595	return 0;
1596
1597	if (crtc_state->pipe_bpp < 8 * 3)
1598	return -EINVAL;
1599
1600	/* FIXME: split only when necessary */
1601	if (crtc_state->dsc.slice_count > 1)
1602	crtc_state->dsc.num_streams = 2;
1603	else
1604	crtc_state->dsc.num_streams = 1;
1605
1606	/* FIXME: initialize from VBT */
1607	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1608
1609	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1610
1611	ret = intel_dsc_compute_params(pipe_config: crtc_state);
1612	if (ret)
1613	return ret;
1614
1615	/* DSI specific sanity checks on the common code */
1616	drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);
1617	drm_WARN_ON(display->drm, vdsc_cfg->simple_422);
1618	drm_WARN_ON(display->drm,
1619	vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1620	drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);
1621	drm_WARN_ON(display->drm,
1622	vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1623
1624	ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
1625	if (ret)
1626	return ret;
1627
1628	crtc_state->dsc.compression_enable = true;
1629
1630	return 0;
1631	}
1632
1633	static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1634	struct intel_crtc_state *pipe_config,
1635	struct drm_connector_state *conn_state)
1636	{
1637	struct intel_display *display = to_intel_display(encoder);
1638	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1639	struct intel_connector *intel_connector = intel_dsi->attached_connector;
1640	struct drm_display_mode *adjusted_mode =
1641	&pipe_config->hw.adjusted_mode;
1642	int ret;
1643
1644	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
1645	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1646
1647	ret = intel_panel_compute_config(connector: intel_connector, adjusted_mode);
1648	if (ret)
1649	return ret;
1650
1651	ret = intel_pfit_compute_config(crtc_state: pipe_config, conn_state);
1652	if (ret)
1653	return ret;
1654
1655	adjusted_mode->flags = 0;
1656
1657	/* Dual link goes to trancoder DSI'0' */
1658	if (intel_dsi->ports == BIT(PORT_B))
1659	pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1660	else
1661	pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1662
1663	if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1664	pipe_config->pipe_bpp = 24;
1665	else
1666	pipe_config->pipe_bpp = 18;
1667
1668	pipe_config->clock_set = true;
1669
1670	if (gen11_dsi_dsc_compute_config(encoder, crtc_state: pipe_config))
1671	drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");
1672
1673	pipe_config->port_clock = afe_clk(encoder, crtc_state: pipe_config) / 5;
1674
1675	/*
1676	* In case of TE GATE cmd mode, we
1677	* receive TE from the slave if
1678	* dual link is enabled
1679	*/
1680	if (is_cmd_mode(intel_dsi))
1681	gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1682
1683	return 0;
1684	}
1685
1686	static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1687	struct intel_crtc_state *crtc_state)
1688	{
1689	get_dsi_io_power_domains(intel_dsi: enc_to_intel_dsi(encoder));
1690	}
1691
1692	static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1693	enum pipe *pipe)
1694	{
1695	struct intel_display *display = to_intel_display(encoder);
1696	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1697	enum transcoder dsi_trans;
1698	intel_wakeref_t wakeref;
1699	enum port port;
1700	bool ret = false;
1701	u32 tmp;
1702
1703	wakeref = intel_display_power_get_if_enabled(display,
1704	domain: encoder->power_domain);
1705	if (!wakeref)
1706	return false;
1707
1708	for_each_dsi_port(port, intel_dsi->ports) {
1709	dsi_trans = dsi_port_to_transcoder(port);
1710	tmp = intel_de_read(display,
1711	TRANS_DDI_FUNC_CTL(display, dsi_trans));
1712	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1713	case TRANS_DDI_EDP_INPUT_A_ON:
1714	*pipe = PIPE_A;
1715	break;
1716	case TRANS_DDI_EDP_INPUT_B_ONOFF:
1717	*pipe = PIPE_B;
1718	break;
1719	case TRANS_DDI_EDP_INPUT_C_ONOFF:
1720	*pipe = PIPE_C;
1721	break;
1722	case TRANS_DDI_EDP_INPUT_D_ONOFF:
1723	*pipe = PIPE_D;
1724	break;
1725	default:
1726	drm_err(display->drm, "Invalid PIPE input\n");
1727	goto out;
1728	}
1729
1730	tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
1731	ret = tmp & TRANSCONF_ENABLE;
1732	}
1733	out:
1734	intel_display_power_put(display, domain: encoder->power_domain, wakeref);
1735	return ret;
1736	}
1737
1738	static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
1739	struct intel_crtc_state *crtc_state)
1740	{
1741	if (crtc_state->dsc.compression_enable) {
1742	drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
1743	crtc_state->uapi.mode_changed = true;
1744
1745	return false;
1746	}
1747
1748	return true;
1749	}
1750
1751	static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1752	{
1753	intel_encoder_destroy(encoder);
1754	}
1755
1756	static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1757	.destroy = gen11_dsi_encoder_destroy,
1758	};
1759
1760	static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1761	.detect = intel_panel_detect,
1762	.late_register = intel_connector_register,
1763	.early_unregister = intel_connector_unregister,
1764	.destroy = intel_connector_destroy,
1765	.fill_modes = drm_helper_probe_single_connector_modes,
1766	.atomic_get_property = intel_digital_connector_atomic_get_property,
1767	.atomic_set_property = intel_digital_connector_atomic_set_property,
1768	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1769	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
1770	};
1771
1772	static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1773	.get_modes = intel_dsi_get_modes,
1774	.mode_valid = gen11_dsi_mode_valid,
1775	.atomic_check = intel_digital_connector_atomic_check,
1776	};
1777
1778	static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1779	struct mipi_dsi_device *dsi)
1780	{
1781	return 0;
1782	}
1783
1784	static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1785	struct mipi_dsi_device *dsi)
1786	{
1787	return 0;
1788	}
1789
1790	static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1791	const struct mipi_dsi_msg *msg)
1792	{
1793	struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(h: host);
1794	struct mipi_dsi_packet dsi_pkt;
1795	ssize_t ret;
1796	bool enable_lpdt = false;
1797
1798	ret = mipi_dsi_create_packet(packet: &dsi_pkt, msg);
1799	if (ret < 0)
1800	return ret;
1801
1802	if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1803	enable_lpdt = true;
1804
1805	/* only long packet contains payload */
1806	if (mipi_dsi_packet_format_is_long(type: msg->type)) {
1807	ret = dsi_send_pkt_payld(host: intel_dsi_host, packet: &dsi_pkt);
1808	if (ret < 0)
1809	return ret;
1810	}
1811
1812	/* send packet header */
1813	ret = dsi_send_pkt_hdr(host: intel_dsi_host, packet: &dsi_pkt, enable_lpdt);
1814	if (ret < 0)
1815	return ret;
1816
1817	//TODO: add payload receive code if needed
1818
1819	ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1820
1821	return ret;
1822	}
1823
1824	static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1825	.attach = gen11_dsi_host_attach,
1826	.detach = gen11_dsi_host_detach,
1827	.transfer = gen11_dsi_host_transfer,
1828	};
1829
1830	static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1831	{
1832	struct intel_connector *connector = intel_dsi->attached_connector;
1833	struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1834	u32 tlpx_ns;
1835	u32 tclk_prepare_esc_clk, tclk_zero_esc_clk, tclk_pre_esc_clk;
1836	u32 ths_prepare_esc_clk, ths_zero_esc_clk, ths_exit_esc_clk;
1837
1838	tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1839
1840	/*
1841	* The clock and data lane prepare timing parameters are in expressed in
1842	* units of 1/4 escape clocks, and all the other timings parameters in
1843	* escape clocks.
1844	*/
1845	tclk_prepare_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare * 4, tlpx_ns);
1846	tclk_prepare_esc_clk = min(tclk_prepare_esc_clk, 7);
1847
1848	tclk_zero_esc_clk = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1849	mipi_config->tclk_prepare, tlpx_ns);
1850	tclk_zero_esc_clk = min(tclk_zero_esc_clk, 15);
1851
1852	tclk_pre_esc_clk = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1853	tclk_pre_esc_clk = min(tclk_pre_esc_clk, 3);
1854
1855	ths_prepare_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare * 4, tlpx_ns);
1856	ths_prepare_esc_clk = min(ths_prepare_esc_clk, 7);
1857
1858	ths_zero_esc_clk = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1859	mipi_config->ths_prepare, tlpx_ns);
1860	ths_zero_esc_clk = min(ths_zero_esc_clk, 15);
1861
1862	ths_exit_esc_clk = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1863	ths_exit_esc_clk = min(ths_exit_esc_clk, 7);
1864
1865	/* clock lane dphy timings */
1866	intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1867	CLK_PREPARE(tclk_prepare_esc_clk) |
1868	CLK_ZERO_OVERRIDE |
1869	CLK_ZERO(tclk_zero_esc_clk) |
1870	CLK_PRE_OVERRIDE |
1871	CLK_PRE(tclk_pre_esc_clk));
1872
1873	/* data lanes dphy timings */
1874	intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1875	HS_PREPARE(ths_prepare_esc_clk) |
1876	HS_ZERO_OVERRIDE |
1877	HS_ZERO(ths_zero_esc_clk) |
1878	HS_EXIT_OVERRIDE |
1879	HS_EXIT(ths_exit_esc_clk));
1880
1881	intel_dsi_log_params(intel_dsi);
1882	}
1883
1884	static void icl_dsi_add_properties(struct intel_connector *connector)
1885	{
1886	const struct drm_display_mode *fixed_mode =
1887	intel_panel_preferred_fixed_mode(connector);
1888
1889	intel_attach_scaling_mode_property(connector: &connector->base);
1890
1891	drm_connector_set_panel_orientation_with_quirk(connector: &connector->base,
1892	panel_orientation: intel_dsi_get_panel_orientation(connector),
1893	width: fixed_mode->hdisplay,
1894	height: fixed_mode->vdisplay);
1895	}
1896
1897	void icl_dsi_init(struct intel_display *display,
1898	const struct intel_bios_encoder_data *devdata)
1899	{
1900	struct intel_dsi *intel_dsi;
1901	struct intel_encoder *encoder;
1902	struct intel_connector *intel_connector;
1903	struct drm_connector *connector;
1904	enum port port;
1905
1906	port = intel_bios_encoder_port(devdata);
1907	if (port == PORT_NONE)
1908	return;
1909
1910	intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1911	if (!intel_dsi)
1912	return;
1913
1914	intel_connector = intel_connector_alloc();
1915	if (!intel_connector) {
1916	kfree(objp: intel_dsi);
1917	return;
1918	}
1919
1920	encoder = &intel_dsi->base;
1921	intel_dsi->attached_connector = intel_connector;
1922	connector = &intel_connector->base;
1923
1924	encoder->devdata = devdata;
1925
1926	/* register DSI encoder with DRM subsystem */
1927	drm_encoder_init(dev: display->drm, encoder: &encoder->base,
1928	funcs: &gen11_dsi_encoder_funcs,
1929	DRM_MODE_ENCODER_DSI, name: "DSI %c", port_name(port));
1930
1931	encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1932	encoder->pre_enable = gen11_dsi_pre_enable;
1933	encoder->enable = gen11_dsi_enable;
1934	encoder->disable = gen11_dsi_disable;
1935	encoder->post_disable = gen11_dsi_post_disable;
1936	encoder->port = port;
1937	encoder->get_config = gen11_dsi_get_config;
1938	encoder->sync_state = gen11_dsi_sync_state;
1939	encoder->update_pipe = intel_backlight_update;
1940	encoder->compute_config = gen11_dsi_compute_config;
1941	encoder->get_hw_state = gen11_dsi_get_hw_state;
1942	encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
1943	encoder->type = INTEL_OUTPUT_DSI;
1944	encoder->cloneable = 0;
1945	encoder->pipe_mask = ~0;
1946	encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1947	encoder->get_power_domains = gen11_dsi_get_power_domains;
1948	encoder->disable_clock = gen11_dsi_gate_clocks;
1949	encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
1950	encoder->shutdown = intel_dsi_shutdown;
1951
1952	/* register DSI connector with DRM subsystem */
1953	drm_connector_init(dev: display->drm, connector,
1954	funcs: &gen11_dsi_connector_funcs,
1955	DRM_MODE_CONNECTOR_DSI);
1956	drm_connector_helper_add(connector, funcs: &gen11_dsi_connector_helper_funcs);
1957	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1958	intel_connector->get_hw_state = intel_connector_get_hw_state;
1959
1960	/* attach connector to encoder */
1961	intel_connector_attach_encoder(connector: intel_connector, encoder);
1962
1963	intel_dsi->panel_power_off_time = ktime_get_boottime();
1964
1965	intel_bios_init_panel_late(display, panel: &intel_connector->panel, devdata: encoder->devdata, NULL);
1966
1967	mutex_lock(&display->drm->mode_config.mutex);
1968	intel_panel_add_vbt_lfp_fixed_mode(connector: intel_connector);
1969	mutex_unlock(lock: &display->drm->mode_config.mutex);
1970
1971	if (!intel_panel_preferred_fixed_mode(connector: intel_connector)) {
1972	drm_err(display->drm, "DSI fixed mode info missing\n");
1973	goto err;
1974	}
1975
1976	intel_panel_init(connector: intel_connector, NULL);
1977
1978	intel_backlight_setup(connector: intel_connector, pipe: INVALID_PIPE);
1979
1980	if (intel_connector->panel.vbt.dsi.config->dual_link)
1981	intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
1982	else
1983	intel_dsi->ports = BIT(port);
1984
1985	if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1986	intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1987
1988	if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1989	intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1990
1991	for_each_dsi_port(port, intel_dsi->ports) {
1992	struct intel_dsi_host *host;
1993
1994	host = intel_dsi_host_init(intel_dsi, funcs: &gen11_dsi_host_ops, port);
1995	if (!host)
1996	goto err;
1997
1998	intel_dsi->dsi_hosts[port] = host;
1999	}
2000
2001	if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
2002	drm_dbg_kms(display->drm, "no device found\n");
2003	goto err;
2004	}
2005
2006	icl_dphy_param_init(intel_dsi);
2007
2008	icl_dsi_add_properties(connector: intel_connector);
2009	return;
2010
2011	err:
2012	drm_connector_cleanup(connector);
2013	drm_encoder_cleanup(encoder: &encoder->base);
2014	kfree(objp: intel_dsi);
2015	kfree(objp: intel_connector);
2016	}
2017