| 1 | /* SPDX-License-Identifier: MIT */ |
|---|
| 2 | /* |
|---|
| 3 | * Copyright © 2023 Intel Corporation |
|---|
| 4 | */ |
|---|
| 5 | |
|---|
| 6 | #ifndef __INTEL_VDSC_REGS_H__ |
|---|
| 7 | #define __INTEL_VDSC_REGS_H__ |
|---|
| 8 | |
|---|
| 9 | #include "intel_display_reg_defs.h" |
|---|
| 10 | |
|---|
| 11 | /* Display Stream Splitter Control */ |
|---|
| 12 | #define DSS_CTL1 _MMIO(0x67400) |
|---|
| 13 | #define SPLITTER_ENABLE (1 << 31) |
|---|
| 14 | #define JOINER_ENABLE (1 << 30) |
|---|
| 15 | #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) |
|---|
| 16 | #define DUAL_LINK_MODE_FRONTBACK (0 << 24) |
|---|
| 17 | #define OVERLAP_PIXELS_MASK (0xf << 16) |
|---|
| 18 | #define OVERLAP_PIXELS(pixels) ((pixels) << 16) |
|---|
| 19 | #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) |
|---|
| 20 | #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) |
|---|
| 21 | #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 |
|---|
| 22 | |
|---|
| 23 | #define DSS_CTL2 _MMIO(0x67404) |
|---|
| 24 | #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) |
|---|
| 25 | #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) |
|---|
| 26 | #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) |
|---|
| 27 | #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) |
|---|
| 28 | |
|---|
| 29 | #define _ICL_PIPE_DSS_CTL1_PB 0x78200 |
|---|
| 30 | #define _ICL_PIPE_DSS_CTL1_PC 0x78400 |
|---|
| 31 | #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 32 | _ICL_PIPE_DSS_CTL1_PB, \ |
|---|
| 33 | _ICL_PIPE_DSS_CTL1_PC) |
|---|
| 34 | #define BIG_JOINER_ENABLE (1 << 29) |
|---|
| 35 | #define MASTER_BIG_JOINER_ENABLE (1 << 28) |
|---|
| 36 | #define VGA_CENTERING_ENABLE (1 << 27) |
|---|
| 37 | #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) |
|---|
| 38 | #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) |
|---|
| 39 | #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) |
|---|
| 40 | #define UNCOMPRESSED_JOINER_MASTER (1 << 21) |
|---|
| 41 | #define UNCOMPRESSED_JOINER_SLAVE (1 << 20) |
|---|
| 42 | |
|---|
| 43 | #define _ICL_PIPE_DSS_CTL2_PB 0x78204 |
|---|
| 44 | #define _ICL_PIPE_DSS_CTL2_PC 0x78404 |
|---|
| 45 | #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 46 | _ICL_PIPE_DSS_CTL2_PB, \ |
|---|
| 47 | _ICL_PIPE_DSS_CTL2_PC) |
|---|
| 48 | |
|---|
| 49 | /* Icelake Display Stream Compression Registers */ |
|---|
| 50 | #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) |
|---|
| 51 | #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) |
|---|
| 52 | #define _DSCA_PPS_0 0x6B200 |
|---|
| 53 | #define _DSCC_PPS_0 0x6BA00 |
|---|
| 54 | #define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) |
|---|
| 55 | #define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) |
|---|
| 56 | #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 |
|---|
| 57 | #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 |
|---|
| 58 | #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 |
|---|
| 59 | #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 |
|---|
| 60 | #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 61 | _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ |
|---|
| 62 | _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) |
|---|
| 63 | #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 64 | _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ |
|---|
| 65 | _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) |
|---|
| 66 | #define _ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ |
|---|
| 67 | _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ |
|---|
| 68 | _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) |
|---|
| 69 | #define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \ |
|---|
| 70 | _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ |
|---|
| 71 | _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) |
|---|
| 72 | #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) |
|---|
| 73 | #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) |
|---|
| 74 | |
|---|
| 75 | /* PPS 0 */ |
|---|
| 76 | #define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23) |
|---|
| 77 | #define DSC_PPS0_NATIVE_420_ENABLE REG_BIT(22) |
|---|
| 78 | #define DSC_PPS0_ALT_ICH_SEL REG_BIT(20) |
|---|
| 79 | #define DSC_PPS0_VBR_ENABLE REG_BIT(19) |
|---|
| 80 | #define DSC_PPS0_422_ENABLE REG_BIT(18) |
|---|
| 81 | #define DSC_PPS0_COLOR_SPACE_CONVERSION REG_BIT(17) |
|---|
| 82 | #define DSC_PPS0_BLOCK_PREDICTION REG_BIT(16) |
|---|
| 83 | #define DSC_PPS0_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12) |
|---|
| 84 | #define DSC_PPS0_LINE_BUF_DEPTH(depth) REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth) |
|---|
| 85 | #define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8) |
|---|
| 86 | #define DSC_PPS0_BPC(bpc) REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc) |
|---|
| 87 | #define DSC_PPS0_VER_MINOR_MASK REG_GENMASK(7, 4) |
|---|
| 88 | #define DSC_PPS0_VER_MINOR(minor) REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor) |
|---|
| 89 | #define DSC_PPS0_VER_MAJOR_MASK REG_GENMASK(3, 0) |
|---|
| 90 | #define DSC_PPS0_VER_MAJOR(major) REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major) |
|---|
| 91 | |
|---|
| 92 | /* PPS 1 */ |
|---|
| 93 | #define DSC_PPS1_BPP_MASK REG_GENMASK(9, 0) |
|---|
| 94 | #define DSC_PPS1_BPP(bpp) REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp) |
|---|
| 95 | |
|---|
| 96 | /* PPS 2 */ |
|---|
| 97 | #define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16) |
|---|
| 98 | #define DSC_PPS2_PIC_HEIGHT_MASK REG_GENMASK(15, 0) |
|---|
| 99 | #define DSC_PPS2_PIC_WIDTH(pic_width) REG_FIELD_PREP(DSC_PPS2_PIC_WIDTH_MASK, pic_width) |
|---|
| 100 | #define DSC_PPS2_PIC_HEIGHT(pic_height) REG_FIELD_PREP(DSC_PPS2_PIC_HEIGHT_MASK, pic_height) |
|---|
| 101 | |
|---|
| 102 | /* PPS 3 */ |
|---|
| 103 | #define DSC_PPS3_SLICE_WIDTH_MASK REG_GENMASK(31, 16) |
|---|
| 104 | #define DSC_PPS3_SLICE_HEIGHT_MASK REG_GENMASK(15, 0) |
|---|
| 105 | #define DSC_PPS3_SLICE_WIDTH(slice_width) REG_FIELD_PREP(DSC_PPS3_SLICE_WIDTH_MASK, slice_width) |
|---|
| 106 | #define DSC_PPS3_SLICE_HEIGHT(slice_height) REG_FIELD_PREP(DSC_PPS3_SLICE_HEIGHT_MASK, slice_height) |
|---|
| 107 | |
|---|
| 108 | /* PPS 4 */ |
|---|
| 109 | #define DSC_PPS4_INITIAL_DEC_DELAY_MASK REG_GENMASK(31, 16) |
|---|
| 110 | #define DSC_PPS4_INITIAL_XMIT_DELAY_MASK REG_GENMASK(9, 0) |
|---|
| 111 | #define DSC_PPS4_INITIAL_DEC_DELAY(dec_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_DEC_DELAY_MASK, \ |
|---|
| 112 | dec_delay) |
|---|
| 113 | #define DSC_PPS4_INITIAL_XMIT_DELAY(xmit_delay) REG_FIELD_PREP(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, \ |
|---|
| 114 | xmit_delay) |
|---|
| 115 | |
|---|
| 116 | /* PPS 5 */ |
|---|
| 117 | #define DSC_PPS5_SCALE_DEC_INT_MASK REG_GENMASK(27, 16) |
|---|
| 118 | #define DSC_PPS5_SCALE_INC_INT_MASK REG_GENMASK(15, 0) |
|---|
| 119 | #define DSC_PPS5_SCALE_DEC_INT(scale_dec) REG_FIELD_PREP(DSC_PPS5_SCALE_DEC_INT_MASK, scale_dec) |
|---|
| 120 | #define DSC_PPS5_SCALE_INC_INT(scale_inc) REG_FIELD_PREP(DSC_PPS5_SCALE_INC_INT_MASK, scale_inc) |
|---|
| 121 | |
|---|
| 122 | /* PPS 6 */ |
|---|
| 123 | #define DSC_PPS6_FLATNESS_MAX_QP_MASK REG_GENMASK(28, 24) |
|---|
| 124 | #define DSC_PPS6_FLATNESS_MIN_QP_MASK REG_GENMASK(20, 16) |
|---|
| 125 | #define DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK REG_GENMASK(12, 8) |
|---|
| 126 | #define DSC_PPS6_INITIAL_SCALE_VALUE_MASK REG_GENMASK(5, 0) |
|---|
| 127 | #define DSC_PPS6_FLATNESS_MAX_QP(max_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MAX_QP_MASK, max_qp) |
|---|
| 128 | #define DSC_PPS6_FLATNESS_MIN_QP(min_qp) REG_FIELD_PREP(DSC_PPS6_FLATNESS_MIN_QP_MASK, min_qp) |
|---|
| 129 | #define DSC_PPS6_FIRST_LINE_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, \ |
|---|
| 130 | offset) |
|---|
| 131 | #define DSC_PPS6_INITIAL_SCALE_VALUE(value) REG_FIELD_PREP(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, \ |
|---|
| 132 | value) |
|---|
| 133 | |
|---|
| 134 | /* PPS 7 */ |
|---|
| 135 | #define DSC_PPS7_NFL_BPG_OFFSET_MASK REG_GENMASK(31, 16) |
|---|
| 136 | #define DSC_PPS7_SLICE_BPG_OFFSET_MASK REG_GENMASK(15, 0) |
|---|
| 137 | #define DSC_PPS7_NFL_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_NFL_BPG_OFFSET_MASK, bpg_offset) |
|---|
| 138 | #define DSC_PPS7_SLICE_BPG_OFFSET(bpg_offset) REG_FIELD_PREP(DSC_PPS7_SLICE_BPG_OFFSET_MASK, \ |
|---|
| 139 | bpg_offset) |
|---|
| 140 | /* PPS 8 */ |
|---|
| 141 | #define DSC_PPS8_INITIAL_OFFSET_MASK REG_GENMASK(31, 16) |
|---|
| 142 | #define DSC_PPS8_FINAL_OFFSET_MASK REG_GENMASK(15, 0) |
|---|
| 143 | #define DSC_PPS8_INITIAL_OFFSET(initial_offset) REG_FIELD_PREP(DSC_PPS8_INITIAL_OFFSET_MASK, \ |
|---|
| 144 | initial_offset) |
|---|
| 145 | #define DSC_PPS8_FINAL_OFFSET(final_offset) REG_FIELD_PREP(DSC_PPS8_FINAL_OFFSET_MASK, \ |
|---|
| 146 | final_offset) |
|---|
| 147 | |
|---|
| 148 | /* PPS 9 */ |
|---|
| 149 | #define DSC_PPS9_RC_EDGE_FACTOR_MASK REG_GENMASK(19, 16) |
|---|
| 150 | #define DSC_PPS9_RC_MODEL_SIZE_MASK REG_GENMASK(15, 0) |
|---|
| 151 | #define DSC_PPS9_RC_EDGE_FACTOR(rc_edge_fact) REG_FIELD_PREP(DSC_PPS9_RC_EDGE_FACTOR_MASK, \ |
|---|
| 152 | rc_edge_fact) |
|---|
| 153 | #define DSC_PPS9_RC_MODEL_SIZE(rc_model_size) REG_FIELD_PREP(DSC_PPS9_RC_MODEL_SIZE_MASK, \ |
|---|
| 154 | rc_model_size) |
|---|
| 155 | |
|---|
| 156 | /* PPS 10 */ |
|---|
| 157 | #define DSC_PPS10_RC_TGT_OFF_LOW_MASK REG_GENMASK(23, 20) |
|---|
| 158 | #define DSC_PPS10_RC_TGT_OFF_HIGH_MASK REG_GENMASK(19, 16) |
|---|
| 159 | #define DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK REG_GENMASK(12, 8) |
|---|
| 160 | #define DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK REG_GENMASK(4, 0) |
|---|
| 161 | #define DSC_PPS10_RC_TARGET_OFF_LOW(rc_tgt_off_low) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_LOW_MASK, \ |
|---|
| 162 | rc_tgt_off_low) |
|---|
| 163 | #define DSC_PPS10_RC_TARGET_OFF_HIGH(rc_tgt_off_high) REG_FIELD_PREP(DSC_PPS10_RC_TGT_OFF_HIGH_MASK, \ |
|---|
| 164 | rc_tgt_off_high) |
|---|
| 165 | #define DSC_PPS10_RC_QUANT_INC_LIMIT1(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, lim) |
|---|
| 166 | #define DSC_PPS10_RC_QUANT_INC_LIMIT0(lim) REG_FIELD_PREP(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, lim) |
|---|
| 167 | |
|---|
| 168 | /* PPS 16 */ |
|---|
| 169 | #define DSC_PPS16_SLICE_ROW_PR_FRME_MASK REG_GENMASK(31, 20) |
|---|
| 170 | #define DSC_PPS16_SLICE_PER_LINE_MASK REG_GENMASK(18, 16) |
|---|
| 171 | #define DSC_PPS16_SLICE_CHUNK_SIZE_MASK REG_GENMASK(15, 0) |
|---|
| 172 | #define DSC_PPS16_SLICE_ROW_PER_FRAME(slice_row_per_frame) REG_FIELD_PREP(DSC_PPS16_SLICE_ROW_PR_FRME_MASK, \ |
|---|
| 173 | slice_row_per_frame) |
|---|
| 174 | #define DSC_PPS16_SLICE_PER_LINE(slice_per_line) REG_FIELD_PREP(DSC_PPS16_SLICE_PER_LINE_MASK, \ |
|---|
| 175 | slice_per_line) |
|---|
| 176 | #define DSC_PPS16_SLICE_CHUNK_SIZE(slice_chunk_size) REG_FIELD_PREP(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, \ |
|---|
| 177 | slice_chunk_size) |
|---|
| 178 | |
|---|
| 179 | /* PPS 17 (MTL+) */ |
|---|
| 180 | #define DSC_PPS17_SL_BPG_OFFSET_MASK REG_GENMASK(31, 27) |
|---|
| 181 | #define DSC_PPS17_SL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS17_SL_BPG_OFFSET_MASK, offset) |
|---|
| 182 | |
|---|
| 183 | /* PPS 18 (MTL+) */ |
|---|
| 184 | #define DSC_PPS18_NSL_BPG_OFFSET_MASK REG_GENMASK(31, 16) |
|---|
| 185 | #define DSC_PPS18_SL_OFFSET_ADJ_MASK REG_GENMASK(15, 0) |
|---|
| 186 | #define DSC_PPS18_NSL_BPG_OFFSET(offset) REG_FIELD_PREP(DSC_PPS18_NSL_BPG_OFFSET_MASK, offset) |
|---|
| 187 | #define DSC_PPS18_SL_OFFSET_ADJ(offset) REG_FIELD_PREP(DSC_PPS18_SL_OFFSET_ADJ_MASK, offset) |
|---|
| 188 | |
|---|
| 189 | /* Icelake Rate Control Buffer Threshold Registers */ |
|---|
| 190 | #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) |
|---|
| 191 | #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) |
|---|
| 192 | #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) |
|---|
| 193 | #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) |
|---|
| 194 | #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) |
|---|
| 195 | #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) |
|---|
| 196 | #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) |
|---|
| 197 | #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) |
|---|
| 198 | #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) |
|---|
| 199 | #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) |
|---|
| 200 | #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) |
|---|
| 201 | #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) |
|---|
| 202 | #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 203 | _ICL_DSC0_RC_BUF_THRESH_0_PB, \ |
|---|
| 204 | _ICL_DSC0_RC_BUF_THRESH_0_PC) |
|---|
| 205 | #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 206 | _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ |
|---|
| 207 | _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) |
|---|
| 208 | #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 209 | _ICL_DSC1_RC_BUF_THRESH_0_PB, \ |
|---|
| 210 | _ICL_DSC1_RC_BUF_THRESH_0_PC) |
|---|
| 211 | #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 212 | _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ |
|---|
| 213 | _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) |
|---|
| 214 | |
|---|
| 215 | #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) |
|---|
| 216 | #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) |
|---|
| 217 | #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) |
|---|
| 218 | #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) |
|---|
| 219 | #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) |
|---|
| 220 | #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) |
|---|
| 221 | #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) |
|---|
| 222 | #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) |
|---|
| 223 | #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) |
|---|
| 224 | #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) |
|---|
| 225 | #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) |
|---|
| 226 | #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) |
|---|
| 227 | #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 228 | _ICL_DSC0_RC_BUF_THRESH_1_PB, \ |
|---|
| 229 | _ICL_DSC0_RC_BUF_THRESH_1_PC) |
|---|
| 230 | #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 231 | _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ |
|---|
| 232 | _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) |
|---|
| 233 | #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 234 | _ICL_DSC1_RC_BUF_THRESH_1_PB, \ |
|---|
| 235 | _ICL_DSC1_RC_BUF_THRESH_1_PC) |
|---|
| 236 | #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 237 | _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ |
|---|
| 238 | _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) |
|---|
| 239 | |
|---|
| 240 | /* Icelake DSC Rate Control Range Parameter Registers */ |
|---|
| 241 | #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) |
|---|
| 242 | #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) |
|---|
| 243 | #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) |
|---|
| 244 | #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) |
|---|
| 245 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) |
|---|
| 246 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) |
|---|
| 247 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) |
|---|
| 248 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) |
|---|
| 249 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) |
|---|
| 250 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) |
|---|
| 251 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) |
|---|
| 252 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) |
|---|
| 253 | #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 254 | _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ |
|---|
| 255 | _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) |
|---|
| 256 | #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 257 | _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ |
|---|
| 258 | _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) |
|---|
| 259 | #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 260 | _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ |
|---|
| 261 | _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) |
|---|
| 262 | #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 263 | _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ |
|---|
| 264 | _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) |
|---|
| 265 | #define RC_BPG_OFFSET_SHIFT 10 |
|---|
| 266 | #define RC_MAX_QP_SHIFT 5 |
|---|
| 267 | #define RC_MIN_QP_SHIFT 0 |
|---|
| 268 | |
|---|
| 269 | #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) |
|---|
| 270 | #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) |
|---|
| 271 | #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) |
|---|
| 272 | #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) |
|---|
| 273 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) |
|---|
| 274 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) |
|---|
| 275 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) |
|---|
| 276 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) |
|---|
| 277 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) |
|---|
| 278 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) |
|---|
| 279 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) |
|---|
| 280 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) |
|---|
| 281 | #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 282 | _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ |
|---|
| 283 | _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) |
|---|
| 284 | #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 285 | _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ |
|---|
| 286 | _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) |
|---|
| 287 | #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 288 | _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ |
|---|
| 289 | _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) |
|---|
| 290 | #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 291 | _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ |
|---|
| 292 | _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) |
|---|
| 293 | |
|---|
| 294 | #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) |
|---|
| 295 | #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) |
|---|
| 296 | #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) |
|---|
| 297 | #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) |
|---|
| 298 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) |
|---|
| 299 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) |
|---|
| 300 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) |
|---|
| 301 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) |
|---|
| 302 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) |
|---|
| 303 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) |
|---|
| 304 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) |
|---|
| 305 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) |
|---|
| 306 | #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 307 | _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ |
|---|
| 308 | _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) |
|---|
| 309 | #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 310 | _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ |
|---|
| 311 | _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) |
|---|
| 312 | #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 313 | _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ |
|---|
| 314 | _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) |
|---|
| 315 | #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 316 | _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ |
|---|
| 317 | _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) |
|---|
| 318 | |
|---|
| 319 | #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) |
|---|
| 320 | #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) |
|---|
| 321 | #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) |
|---|
| 322 | #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) |
|---|
| 323 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) |
|---|
| 324 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) |
|---|
| 325 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) |
|---|
| 326 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) |
|---|
| 327 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) |
|---|
| 328 | #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) |
|---|
| 329 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) |
|---|
| 330 | #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) |
|---|
| 331 | #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 332 | _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ |
|---|
| 333 | _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) |
|---|
| 334 | #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 335 | _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ |
|---|
| 336 | _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) |
|---|
| 337 | #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 338 | _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ |
|---|
| 339 | _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) |
|---|
| 340 | #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ |
|---|
| 341 | _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ |
|---|
| 342 | _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) |
|---|
| 343 | |
|---|
| 344 | #endif /* __INTEL_VDSC_REGS_H__ */ |
|---|
| 345 | |
|---|
