| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2022 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_BACKLIGHT_REGS_H__ |
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| 7 | #define __INTEL_BACKLIGHT_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | #define _VLV_BLC_PWM_CTL2_A (VLV_DISPLAY_BASE + 0x61250) |
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| 12 | #define _VLV_BLC_PWM_CTL2_B (VLV_DISPLAY_BASE + 0x61350) |
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| 13 | #define VLV_BLC_PWM_CTL2(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL2_A, _VLV_BLC_PWM_CTL2_B) |
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| 14 | |
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| 15 | #define _VLV_BLC_PWM_CTL_A (VLV_DISPLAY_BASE + 0x61254) |
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| 16 | #define _VLV_BLC_PWM_CTL_B (VLV_DISPLAY_BASE + 0x61354) |
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| 17 | #define VLV_BLC_PWM_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_PWM_CTL_A, _VLV_BLC_PWM_CTL_B) |
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| 18 | |
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| 19 | #define _VLV_BLC_HIST_CTL_A (VLV_DISPLAY_BASE + 0x61260) |
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| 20 | #define _VLV_BLC_HIST_CTL_B (VLV_DISPLAY_BASE + 0x61360) |
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| 21 | #define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A, _VLV_BLC_HIST_CTL_B) |
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| 22 | |
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| 23 | /* Backlight control */ |
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| 24 | #define BLC_PWM_CTL2 _MMIO(0x61250) /* 965+ only */ |
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| 25 | #define BLM_PWM_ENABLE (1 << 31) |
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| 26 | #define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ |
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| 27 | #define BLM_PIPE_SELECT (1 << 29) |
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| 28 | #define BLM_PIPE_SELECT_IVB (3 << 29) |
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| 29 | #define BLM_PIPE_A (0 << 29) |
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| 30 | #define BLM_PIPE_B (1 << 29) |
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| 31 | #define BLM_PIPE_C (2 << 29) /* ivb + */ |
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| 32 | #define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */ |
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| 33 | #define BLM_TRANSCODER_B BLM_PIPE_B |
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| 34 | #define BLM_TRANSCODER_C BLM_PIPE_C |
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| 35 | #define BLM_TRANSCODER_EDP (3 << 29) |
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| 36 | #define BLM_PIPE(pipe) ((pipe) << 29) |
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| 37 | #define BLM_POLARITY_I965 (1 << 28) /* gen4 only */ |
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| 38 | #define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26) |
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| 39 | #define BLM_PHASE_IN_ENABLE (1 << 25) |
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| 40 | #define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24) |
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| 41 | #define BLM_PHASE_IN_TIME_BASE_SHIFT (16) |
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| 42 | #define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16) |
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| 43 | #define BLM_PHASE_IN_COUNT_SHIFT (8) |
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| 44 | #define BLM_PHASE_IN_COUNT_MASK (0xff << 8) |
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| 45 | #define BLM_PHASE_IN_INCR_SHIFT (0) |
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| 46 | #define BLM_PHASE_IN_INCR_MASK (0xff << 0) |
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| 47 | #define BLC_PWM_CTL _MMIO(0x61254) |
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| 48 | /* |
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| 49 | * This is the most significant 15 bits of the number of backlight cycles in a |
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| 50 | * complete cycle of the modulated backlight control. |
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| 51 | * |
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| 52 | * The actual value is this field multiplied by two. |
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| 53 | */ |
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| 54 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) |
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| 55 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) |
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| 56 | #define BLM_LEGACY_MODE (1 << 16) /* gen2 only */ |
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| 57 | /* |
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| 58 | * This is the number of cycles out of the backlight modulation cycle for which |
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| 59 | * the backlight is on. |
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| 60 | * |
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| 61 | * This field must be no greater than the number of cycles in the complete |
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| 62 | * backlight modulation cycle. |
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| 63 | */ |
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| 64 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) |
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| 65 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) |
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| 66 | #define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) |
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| 67 | #define BLM_POLARITY_PNV (1 << 0) /* pnv only */ |
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| 68 | |
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| 69 | #define BLC_HIST_CTL _MMIO(0x61260) |
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| 70 | #define BLM_HISTOGRAM_ENABLE (1 << 31) |
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| 71 | |
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| 72 | /* New registers for PCH-split platforms. Safe where new bits show up, the |
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| 73 | * register layout machtes with gen4 BLC_PWM_CTL[12]. */ |
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| 74 | #define BLC_PWM_CPU_CTL2 _MMIO(0x48250) |
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| 75 | #define BLC_PWM_CPU_CTL _MMIO(0x48254) |
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| 76 | |
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| 77 | #define HSW_BLC_PWM2_CTL _MMIO(0x48350) |
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| 78 | |
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| 79 | /* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is |
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| 80 | * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */ |
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| 81 | #define BLC_PWM_PCH_CTL1 _MMIO(0xc8250) |
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| 82 | #define BLM_PCH_PWM_ENABLE (1 << 31) |
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| 83 | #define BLM_PCH_OVERRIDE_ENABLE (1 << 30) |
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| 84 | #define BLM_PCH_POLARITY (1 << 29) |
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| 85 | #define BLC_PWM_PCH_CTL2 _MMIO(0xc8254) |
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| 86 | |
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| 87 | /* BXT backlight register definition. */ |
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| 88 | #define _BXT_BLC_PWM_CTL1 0xC8250 |
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| 89 | #define BXT_BLC_PWM_ENABLE (1 << 31) |
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| 90 | #define BXT_BLC_PWM_POLARITY (1 << 29) |
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| 91 | #define _BXT_BLC_PWM_FREQ1 0xC8254 |
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| 92 | #define _BXT_BLC_PWM_DUTY1 0xC8258 |
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| 93 | |
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| 94 | #define _BXT_BLC_PWM_CTL2 0xC8350 |
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| 95 | #define _BXT_BLC_PWM_FREQ2 0xC8354 |
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| 96 | #define _BXT_BLC_PWM_DUTY2 0xC8358 |
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| 97 | |
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| 98 | #define BXT_BLC_PWM_CTL(controller) _MMIO_PIPE(controller, \ |
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| 99 | _BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2) |
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| 100 | #define BXT_BLC_PWM_FREQ(controller) _MMIO_PIPE(controller, \ |
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| 101 | _BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2) |
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| 102 | #define BXT_BLC_PWM_DUTY(controller) _MMIO_PIPE(controller, \ |
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| 103 | _BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2) |
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| 104 | |
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| 105 | /* Utility pin */ |
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| 106 | #define UTIL_PIN_CTL _MMIO(0x48400) |
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| 107 | #define UTIL_PIN_ENABLE (1 << 31) |
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| 108 | #define UTIL_PIN_PIPE_MASK (3 << 29) |
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| 109 | #define UTIL_PIN_PIPE(x) ((x) << 29) |
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| 110 | #define UTIL_PIN_MODE_MASK (0xf << 24) |
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| 111 | #define UTIL_PIN_MODE_DATA (0 << 24) |
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| 112 | #define UTIL_PIN_MODE_PWM (1 << 24) |
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| 113 | #define UTIL_PIN_MODE_VBLANK (4 << 24) |
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| 114 | #define UTIL_PIN_MODE_VSYNC (5 << 24) |
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| 115 | #define UTIL_PIN_MODE_EYE_LEVEL (8 << 24) |
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| 116 | #define UTIL_PIN_OUTPUT_DATA (1 << 23) |
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| 117 | #define UTIL_PIN_POLARITY (1 << 22) |
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| 118 | #define UTIL_PIN_DIRECTION_INPUT (1 << 19) |
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| 119 | #define UTIL_PIN_INPUT_DATA (1 << 16) |
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| 120 | |
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| 121 | #endif /* __INTEL_BACKLIGHT_REGS_H__ */ |
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| 122 | |
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